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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-02-05 18:09:33 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-02-09 09:21:10 +0800 |
| commit | c3ab02a8ab26971871905cdf63849a3461e7c89e (patch) | |
| tree | 5ba80114a35dc66ce4f69ed20aaffb4590c1d161 | |
| parent | 322e1c291b31998e6f197ecdc3336c2be0223532 (diff) | |
| download | u-boot-imx-c3ab02a8ab26971871905cdf63849a3461e7c89e.zip u-boot-imx-c3ab02a8ab26971871905cdf63849a3461e7c89e.tar.gz u-boot-imx-c3ab02a8ab26971871905cdf63849a3461e7c89e.tar.bz2 | |
MLK-10208 qspi: fix at least 16 bytes fifo issue
This patch "http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=uboot-imx.git;
a=commitdiff;h=71779872ed7072f0ca90dd4db776dd8960b595f4" does not
consider the corner case, such as 2, 3, 6, 7, 10 bytes.
If len is 2, then t1 is 0, t2 is 2.
The original way: t3 = t1 + t2 --> t3 = 2 --> 12 bytes are wrote but not 16.
The new way: t3 = t1 + ((t2 + 3) >> 2) --> t3 = 1 --> 16 bytes are wrote.
Here t2 is not zero, 4 bytes are wrote, there are still 12 bytes need to be
wrote. Since t1 is 0, t3 = 1, for (t3 = 1; t3 < 4; t3++) will write
the other 12 bytes.
In this patch, when write data, QUADSPI_MCR_CLR_TXF_MASK should be used
to clear TXFIFO, but not QUADSPI_MCR_CLR_RXF_MASK.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index de9cb41..6c33c91 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -785,17 +785,16 @@ static void fsl_qspi_ip_read(struct fsl_qspi *q, int len, u8 *rxbuf) static void fsl_qspi_write_data(struct fsl_qspi *q, int len, u8* txbuf) { u32 tmp; - u32 t1, t2, t3; + u32 t1, t2; int j; /* clear the TX FIFO. */ tmp = readl(q->iobase + QUADSPI_MCR); - writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR); + writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); /* fill the TX data to the FIFO */ t2 = len % 4; t1 = len >> 2; /* 4 Bytes aligned */ - t3 = t1 + t2; for (j = 0; j < t1; j++) { memcpy(&tmp, txbuf, 4); @@ -812,9 +811,11 @@ static void fsl_qspi_write_data(struct fsl_qspi *q, int len, u8* txbuf) } #if defined(CONFIG_MX7D) + u32 t3; /* iMX7D TXFIFO must be at least 16 bytes*/ + t3 = t1 + ((t2 + 3) >> 2); for (; t3 < 4; t3++) - writel(tmp, q->iobase + QUADSPI_TBDR); + writel(0, q->iobase + QUADSPI_TBDR); #endif } |