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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-06-11 18:19:45 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-06-12 14:58:06 +0800 |
| commit | 2bc93d766dee5d5dc33035446f82622c4f1fb784 (patch) | |
| tree | 71a67fcea3033f851b318c19d8ae447cd068f0d3 | |
| parent | f907b7642860d984beddcf10ff686a8636202087 (diff) | |
| download | u-boot-imx-2bc93d766dee5d5dc33035446f82622c4f1fb784.zip u-boot-imx-2bc93d766dee5d5dc33035446f82622c4f1fb784.tar.gz u-boot-imx-2bc93d766dee5d5dc33035446f82622c4f1fb784.tar.bz2 | |
MLK-11028 imx: mx6qp change L2 prefetch offset to 0
Change L2 prefetch offset to 0 to make system stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 5cab58016a032ea364c8e5df3994ac51fdf60b0a)
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 9aacc18..660e084 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -1075,7 +1075,7 @@ void v7_outer_cache_enable(void) /* Turn on the L2 I/D prefetch, double linefill */ /* Set prefetch offset with any value except 23 as per errata 765569 */ - val |= 0x7000000f; + val |= 0x70000000; /* * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 |