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| author | Ye.Li <B37916@freescale.com> | 2014-10-23 16:48:20 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-10-24 20:42:43 +0800 |
| commit | 9a59a130162120551ba8e1b89ebcb37aa8fe3c3a (patch) | |
| tree | 9844ab7c8c17c68d85784b274080b3c47035a67c | |
| parent | 5047d3e58d95f84838cd52fd306e0ce87b15391b (diff) | |
| download | u-boot-imx-9a59a130162120551ba8e1b89ebcb37aa8fe3c3a.zip u-boot-imx-9a59a130162120551ba8e1b89ebcb37aa8fe3c3a.tar.gz u-boot-imx-9a59a130162120551ba8e1b89ebcb37aa8fe3c3a.tar.bz2 | |
MLK-9733 imx: mx6sxsabreauto/mx6sxarm2: Fix nand clock glitch
Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk,
before switching the parent of qspi2_clk_root, we must gate off it.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c | 7 | ||||
| -rw-r--r-- | board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c | 7 | ||||
| -rw-r--r-- | board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 7 |
3 files changed, 18 insertions, 3 deletions
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c index cbb632a..d163631 100644 --- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c @@ -500,6 +500,10 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + /* Disable the QSPI2 root clock */ + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + /* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | @@ -515,7 +519,8 @@ static void setup_gpmi_nand(void) MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK | + MXC_CCM_CCGR4_QSPI2_ENFC_MASK); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); diff --git a/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c index 285fdb4..f99f27d 100644 --- a/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c +++ b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c @@ -541,6 +541,10 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + /* Disable the QSPI2 root clock */ + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + /* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | @@ -556,7 +560,8 @@ static void setup_gpmi_nand(void) MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK | + MXC_CCM_CCGR4_QSPI2_ENFC_MASK); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 9a24c99..3fcbdb5 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -288,6 +288,10 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + /* Disable the QSPI2 root clock */ + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + /* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | @@ -303,7 +307,8 @@ static void setup_gpmi_nand(void) MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK | + MXC_CCM_CCGR4_QSPI2_ENFC_MASK); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |