Merge branch 'master' of git://git.denx.de/u-boot-arm

61 files changed, 983 insertions, 91 deletions

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 2c5cd63..168f525 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
 void halt_avp(void)
 {
 	for (;;) {
-		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
-			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
-			FLOW_CTLR_HALT_COP_EVENTS);
+		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+		       FLOW_CTLR_HALT_COP_EVENTS);
 	}
 }
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
index c03aaf1..97f5928 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
 	tegra124_init_clocks();
 
 	/* Set power-gating timer multiplier */
-	clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
-	setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+	writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+	       &pmc->pmc_pwrgate_timer_mult);
 
 	enable_cpu_power_rail();
 	enable_cpu_clocks();
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 99a3913..6b51d5f 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 }
 #endif
 
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+	/* Enable mci clock */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
+
+	at91_set_a_periph(AT91_PIO_PORTA, 6, PUP);	/* MCI1_CK */
+
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);	/* MCI1_CDB */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);	/* MCI1_DB0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, PUP);	/* MCI1_DB1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 24, PUP);	/* MCI1_DB2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* MCI1_DB3 */
+#else
+	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);	/* MCI1_CDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 8, PUP);	/* MCI1_DA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 9, PUP);	/* MCI1_DA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, PUP);	/* MCI1_DA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, PUP);	/* MCI1_DA3 */
+#endif
+}
+#endif
+
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 57f5949..d0bc234 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -97,6 +97,7 @@ void enable_basic_clocks(void)
 		&cmper->gpio4clkctrl,
 		&cmper->gpio5clkctrl,
 		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
 		&cmper->emiffwclkctrl,
 		&cmper->emifclkctrl,
 		&cmper->otfaemifclkctrl,
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index d05e666..9a625c4 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -80,8 +80,8 @@ static void configure_mr(int nr, u32 cs)
  */
 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 {
-	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
-	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
 	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
 	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 
@@ -96,6 +96,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 
 	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
 		configure_mr(nr, 0);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index d28fceb..3e39752 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -113,7 +113,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
 	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
 		;
-	writel(0x0, &ddrctrl->ddrioctrl);
+	writel(0x80000000, &ddrctrl->ddrioctrl);
 
 	config_io_ctrl(ioregs);
 
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
index 37c0cc4..7f4debb 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -52,6 +52,10 @@ u32 spl_boot_device(void)
 {
 #ifdef CONFIG_SYS_USE_MMC
 	return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+	return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+	return BOOT_DEVICE_SPI;
 #endif
 	return BOOT_DEVICE_NONE;
 }
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
index ff6142b..7121388 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/include/asm/arch-at91/gpio.h
@@ -214,7 +214,7 @@ static inline unsigned pin_to_mask(unsigned pin)
 
 /* The following macros are need for backward compatibility */
 #define at91_set_GPIO_periph(x, y) \
-	at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
+	at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_A_periph(x, y) \
 	at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_B_periph(x, y) \
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
index 68c5349..d8a87da 100644
--- a/arch/arm/include/asm/arch-at91/spl.h
+++ b/arch/arm/include/asm/arch-at91/spl.h
@@ -14,6 +14,10 @@ enum {
 	BOOT_DEVICE_MMC1,
 	BOOT_DEVICE_MMC2,
 	BOOT_DEVICE_MMC2_2,
+#elif CONFIG_SYS_USE_NANDFLASH
+	BOOT_DEVICE_NAND,
+#elif CONFIG_SYS_USE_SERIALFLASH
+	BOOT_DEVICE_SPI,
 #endif
 };
 
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 4c3264b..1dd3154 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -298,14 +298,25 @@ struct pmc_ctlr {
 #define PMC_XOFS_SHIFT	1
 #define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
 
+#if defined(CONFIG_TEGRA114)
 #define TIMER_MULT_SHIFT	0
 #define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
 #define TIMER_MULT_CPU_SHIFT	2
 #define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	3
+#define TIMER_MULT_CPU_MASK	(7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
 #define MULT_1			0
 #define MULT_2			1
 #define MULT_4			2
 #define MULT_8			3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16			4
+#endif
 
 #define AMAP_WRITE_SHIFT	20
 #define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 5fe19ae..d63af0e 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -34,7 +34,12 @@
 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+	defined(CONFIG_TEGRA114)
 #define NV_PA_CSITE_BASE	0x70040000
+#else
+#define NV_PA_CSITE_BASE	0x70800000
+#endif
 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
 
 #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index 5d426b5..705ca57 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA114_H_
 #define _TEGRA114_H_
 
+#define CONFIG_TEGRA114
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
index db3d837..86ebd19 100644
--- a/arch/arm/include/asm/arch-tegra124/tegra.h
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -8,6 +8,8 @@
 #ifndef _TEGRA124_H_
 #define _TEGRA124_H_
 
+#define CONFIG_TEGRA124
+
 #define NV_PA_SDRAM_BASE	0x80000000
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 #define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 18856ac..6a4b40e 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -8,6 +8,8 @@
 #ifndef _TEGRA20_H_
 #define _TEGRA20_H_
 
+#define CONFIG_TEGRA20
+
 #define NV_PA_SDRAM_BASE	0x00000000
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index c02c5d8..4ad8b1c 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA30_H_
 #define _TEGRA30_H_
 
+#define CONFIG_TEGRA30
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 6d187ea..4c926ce 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -141,12 +141,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 1,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 2,
 	},
 };
 
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 7784cd7..db29879 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -24,6 +24,7 @@
 #include <net.h>
 #endif
 #include <netdev.h>
+#include <atmel_mci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -214,6 +215,15 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
diff --git a/board/atmel/sama5d3_xplained/Makefile b/board/atmel/sama5d3_xplained/Makefile
new file mode 100644
index 0000000..ec82b06
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2014
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d3_xplained.o
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
new file mode 100644
index 0000000..39f2dc6
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <atmel_mci.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3_xplained_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3_xplained_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3_xplained_mci0_hw_init(void)
+{
+	at91_mci_hw_init();
+
+	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* MCI0 Power */
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3_xplained_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91_gmac_hw_init();
+	at91_macb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_MACB
+	macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+	return 0;
+}
+#endif
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index eff94a4..c835c12 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -307,6 +307,10 @@ void spl_board_init(void)
 {
 #ifdef CONFIG_SYS_USE_MMC
 	sama5d3xek_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	sama5d3xek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+	at91_spi0_hw_init(1 << 0);
 #endif
 }
 
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
index 01019e8..9583149 100644
--- a/board/compulab/cm_t335/cm_t335.c
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -47,7 +47,7 @@ static void cpsw_control(int enabled)
 static struct cpsw_slave_data cpsw_slave = {
 	.slave_reg_ofs	= 0x208,
 	.sliver_reg_ofs	= 0xd80,
-	.phy_id		= 0,
+	.phy_addr	= 0,
 	.phy_if		= PHY_INTERFACE_MODE_RGMII,
 };
 
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 089a835..9f8fcf2 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -116,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 7e5e07f..1071662 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -176,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RGMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RGMII,
 	},
 };
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index 6c316fa..2172379 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -198,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_MII,
 	},
 };
@@ -232,6 +232,13 @@ int board_eth_init(bd_t *bis)
 
 	factoryset_setenv();
 
+	/* Reset SMSC LAN9303 switch for default configuration */
+	gpio_request(GPIO_LAN9303_NRST, "nRST");
+	gpio_direction_output(GPIO_LAN9303_NRST, 0);
+	/* assert active low reset for 200us */
+	udelay(200);
+	gpio_set_value(GPIO_LAN9303_NRST, 1);
+
 	/* Set rgmii mode and enable rmii clock to be sourced from chip */
 	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 
diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c
index 5c22999..f2314b5 100644
--- a/board/siemens/dxr2/mux.c
+++ b/board/siemens/dxr2/mux.c
@@ -221,6 +221,8 @@ static struct module_pin_mux gpios_pin_mux[] = {
 	{OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
 	{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
 	{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+	/* nRST for SMSC LAN9303 switch - GPIO2_24 */
+	{OFFSET(lcd_pclk), MODE(7) },			/* LAN9303 nRST */
 	{-1},
 };
 
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index ef3d6cc..98083d5 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -181,13 +181,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 25ab54d..e0ada3f 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -143,13 +143,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
index a553129..ee88b6f 100644
--- a/board/silica/pengwyn/board.c
+++ b/board/silica/pengwyn/board.c
@@ -141,13 +141,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_MII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_MII,
 	},
 };
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5721768..7609a18 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -544,12 +544,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 	},
 };
 
@@ -602,6 +602,21 @@ int board_eth_init(bd_t *bis)
 	}
 
 #ifdef CONFIG_DRIVER_TI_CPSW
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 95fd137..d744977 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,9 +19,13 @@
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <miiphy.h>
+#include <cpsw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -200,7 +204,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x50074BE4,
 	.temp_alert_config		= 0x0,
-	.emif_ddr_phy_ctlr_1		= 0x0E084008,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
 	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
 	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
@@ -402,3 +406,97 @@ int board_late_init(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+	/* Additional controls can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 16,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
+	if (board_is_eposevm()) {
+		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[0].phy_addr = 16;
+	} else {
+		writel(RGMII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+		cpsw_slaves[0].phy_addr = 0;
+	}
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+
+	return rv;
+}
+#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index c330a81..77c53d2 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -11,6 +11,41 @@
 #include <asm/arch/mux.h>
 #include "board.h"
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
+	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
 static struct module_pin_mux uart0_pin_mux[] = {
 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
 	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
@@ -57,10 +92,15 @@ void enable_board_pin_mux(void)
 {
 	configure_module_pin_mux(mmc0_pin_mux);
 	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mdio_pin_mux);
 
-	if (board_is_gpevm())
+	if (board_is_gpevm()) {
 		configure_module_pin_mux(gpio5_7_pin_mux);
-	configure_module_pin_mux(qspi_pin_mux);
+		configure_module_pin_mux(rgmii1_pin_mux);
+	} else if (board_is_eposevm()) {
+		configure_module_pin_mux(rmii1_pin_mux);
+		configure_module_pin_mux(qspi_pin_mux);
+	}
 }
 
 void enable_i2c0_pin_mux(void)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index bed8285..c6c4fd1 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -149,12 +149,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 2,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 3,
 	},
 };
 
@@ -216,6 +216,21 @@ int board_eth_init(bd_t *bis)
 		if (is_valid_ether_addr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
+
+	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = mac_hi & 0xFF;
+	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+	mac_addr[5] = mac_lo & 0xFF;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
 	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 140ad71..54b3dfb 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -132,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x50,
 		.sliver_reg_ofs	= 0x700,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 	},
 	{
 		.slave_reg_ofs	= 0x90,
 		.sliver_reg_ofs	= 0x740,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 	},
 };
 
diff --git a/boards.cfg b/boards.cfg
index f36c3b4..a32f46b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -278,6 +278,8 @@ Active  arm         armv7          am33xx      ti              am335x
 Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   Lokesh Vutla <lokeshvutla@ti.com>
 Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <matt.porter@linaro.org>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                           -                                                                                                                                 -
+Active  arm         armv7          at91        atmel           sama5d3_xplained    sama5d3_xplained_mmc                 sama5d3_xplained:SAMA5D3,SYS_USE_MMC                                                                                              Bo Shen <voice.shen@atmel.com>
+Active  arm         armv7          at91        atmel           sama5d3_xplained    sama5d3_xplained_nandflash           sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH                                                                                        Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_mmc                       sama5d3xek:SAMA5D3,SYS_USE_MMC                                                                                                    Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_nandflash                 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH                                                                                              Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_spiflash                  sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH                                                                                            Bo Shen <voice.shen@atmel.com>
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 05ddfbb..e1fc48f 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -31,6 +31,10 @@
 
 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
 
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
 struct atmel_nand_host {
 	struct pmecc_regs __iomem *pmecc;
 	struct pmecc_errloc_regs __iomem *pmerrloc;
@@ -1169,6 +1173,209 @@ static int at91_nand_ready(struct mtd_info *mtd)
 }
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+/* The following code is for SPL */
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static int nand_command(int block, int page, uint32_t offs, u8 cmd)
+{
+	struct nand_chip *this = mtd.priv;
+	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+	void (*hwctrl)(struct mtd_info *mtd, int cmd,
+			unsigned int ctrl) = this->cmd_ctrl;
+
+	while (this->dev_ready(&mtd))
+		;
+
+	if (cmd == NAND_CMD_READOOB) {
+		offs += CONFIG_SYS_NAND_PAGE_SIZE;
+		cmd = NAND_CMD_READ0;
+	}
+
+	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+
+	if (this->options & NAND_BUSWIDTH_16)
+		offs >>= 1;
+
+	hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+	hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+	hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+#endif
+	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+	hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+	while (this->dev_ready(&mtd))
+		;
+
+	return 0;
+}
+
+static int nand_is_bad_block(int block)
+{
+	struct nand_chip *this = mtd.priv;
+
+	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
+
+	if (this->options & NAND_BUSWIDTH_16) {
+		if (readw(this->IO_ADDR_R) != 0xffff)
+			return 1;
+	} else {
+		if (readb(this->IO_ADDR_R) != 0xff)
+			return 1;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_NAND_ECC
+static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+		  CONFIG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+
+static int nand_read_page(int block, int page, void *dst)
+{
+	struct nand_chip *this = mtd.priv;
+	u_char ecc_calc[ECCTOTAL];
+	u_char ecc_code[ECCTOTAL];
+	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
+	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsteps = ECCSTEPS;
+	int i;
+	uint8_t *p = dst;
+	nand_command(block, page, 0, NAND_CMD_READ0);
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		if (this->ecc.mode != NAND_ECC_SOFT)
+			this->ecc.hwctl(&mtd, NAND_ECC_READ);
+		this->read_buf(&mtd, p, eccsize);
+		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+	}
+	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+
+	for (i = 0; i < ECCTOTAL; i++)
+		ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+	eccsteps = ECCSTEPS;
+	p = dst;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+
+	return 0;
+}
+#else
+static int nand_read_page(int block, int page, void *dst)
+{
+	struct nand_chip *this = mtd.priv;
+
+	nand_command(block, page, 0, NAND_CMD_READ0);
+	atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+
+	return 0;
+}
+#endif /* CONFIG_SPL_NAND_ECC */
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	unsigned int block, lastblock;
+	unsigned int page;
+
+	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
+	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
+	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+
+	while (block <= lastblock) {
+		if (!nand_is_bad_block(block)) {
+			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+				nand_read_page(block, page, dst);
+				dst += CONFIG_SYS_NAND_PAGE_SIZE;
+				page++;
+			}
+
+			page = 0;
+		} else {
+			lastblock++;
+		}
+
+		block++;
+	}
+
+	return 0;
+}
+
+int at91_nand_wait_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	udelay(this->chip_delay);
+
+	return 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	int ret = 0;
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+#ifdef CONFIG_SYS_NAND_DBW_16
+	nand->options = NAND_BUSWIDTH_16;
+	nand->read_buf = nand_read_buf16;
+#else
+	nand->read_buf = nand_read_buf;
+#endif
+	nand->cmd_ctrl = at91_nand_hwcontrol;
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	nand->dev_ready = at91_nand_ready;
+#else
+	nand->dev_ready = at91_nand_wait_ready;
+#endif
+	nand->chip_delay = 20;
+
+#ifdef CONFIG_ATMEL_NAND_HWECC
+#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+	ret = atmel_pmecc_nand_init_params(nand, &mtd);
+#endif
+#endif
+
+	return ret;
+}
+
+void nand_init(void)
+{
+	mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+	mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
+	mtd.priv = &nand_chip;
+	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	board_nand_init(&nand_chip);
+
+#ifdef CONFIG_SPL_NAND_ECC
+	if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
+		nand_chip.ecc.calculate = nand_calculate_ecc;
+		nand_chip.ecc.correct = nand_correct_data;
+	}
+#endif
+
+	if (nand_chip.select_chip)
+		nand_chip.select_chip(&mtd, 0);
+}
+
+void nand_deselect(void)
+{
+	if (nand_chip.select_chip)
+		nand_chip.select_chip(&mtd, -1);
+}
+
+#else
+
 #ifndef CONFIG_SYS_NAND_BASE_LIST
 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 #endif
@@ -1227,3 +1434,4 @@ void board_nand_init(void)
 			dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
 				i);
 }
+#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 50167aa..dd6c26a 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -656,7 +656,7 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 
 	cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
 
-	priv->phy_mask |= 1 << slave->data->phy_id;
+	priv->phy_mask |= 1 << slave->data->phy_addr;
 }
 
 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
@@ -948,7 +948,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
 			SUPPORTED_1000baseT_Full);
 
 	phydev = phy_connect(priv->bus,
-			CONFIG_PHY_ADDR,
+			slave->data->phy_addr,
 			dev,
 			slave->data->phy_if);
 
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a5736b7..2020e7f 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -398,7 +398,6 @@
 /* Network. */
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 /* NAND support */
diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h
index c00d54f..c17327f 100644
--- a/include/configs/am335x_igep0033.h
+++ b/include/configs/am335x_igep0033.h
@@ -181,7 +181,6 @@
 #define CONFIG_NET_RETRY_COUNT         10
 #define CONFIG_NET_MULTI
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 /* NAND support */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index c773a18..614857d 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -205,4 +205,30 @@
 	"run usbboot;"
 
 #endif
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM43xx U-Boot SPL"
+
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SYS_RX_ETH_BUFFER	64
+
 #endif	/* __CONFIG_AM43XX_EVM_H */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index b9aa036..48c12ea 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -103,6 +103,7 @@
 #define CONFIG_CMD_PING		1
 #define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_USB		1
 
 /* SDRAM */
@@ -123,6 +124,18 @@
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /* NOR flash, if populated */
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define CONFIG_SYS_FLASH_CFI			1
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 1f57bd2..7bbe596 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -51,7 +51,6 @@
 #define CONFIG_MII			/* Required in net/eth.c */
 #define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			1
 #define CONFIG_PHY_NATSEMI
 #define CONFIG_SPL_NET_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT		/* used for a fetching MAC-Address */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 56e9a8e..26b615b 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -114,7 +114,6 @@
 /* Network. */
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_ATHEROS
 
 /* NAND support */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index c67cf60..291c538 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -62,7 +62,6 @@
 #define CONFIG_MII			/* Required in net/eth.c */
 #define CONFIG_PHY_GIGE			/* per-board part of CPSW */
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			2
 
 /* SPI */
 #undef	CONFIG_OMAP3_SPI
diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h
index 1e42f5c..75f7812 100644
--- a/include/configs/dxr2.h
+++ b/include/configs/dxr2.h
@@ -26,6 +26,7 @@
 
 #define BOARD_DFU_BUTTON_GPIO	27
 #define BOARD_DFU_BUTTON_LED	64
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
 
 #undef CONFIG_DOS_PARTITION
 #undef CONFIG_CMD_FAT
@@ -49,7 +50,6 @@
 
 #undef CONFIG_MII
 #undef CONFIG_PHY_GIGE
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FACTORYSET
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 12d8141..d56d5b0 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -37,6 +37,11 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 #endif
 
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_3		/* GPIO64 .. 95 is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
 /* USB */
 #define CONFIG_MUSB_UDC			1
 #define CONFIG_USB_OMAP3		1
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 6f41ee7..9af3efd 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -297,7 +297,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 #endif	/* ! __CONFIG_PCM051_H */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 5a55556..fc25966 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -196,7 +196,6 @@
 /* Network */
 #define CONFIG_CMD_MII
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR		1
 #define CONFIG_PHY_RESET	1
 #define CONFIG_PHY_NATSEMI
 
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 7722f7b..6276d43 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -44,7 +44,6 @@
 #undef CONFIG_SPL_NET_VCI_STRING
 #undef CONFIG_SPL_ETH_SUPPORT
 
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_ATHEROS
 
 #define CONFIG_FACTORYSET
diff --git a/include/configs/rut.h b/include/configs/rut.h
index d4519f9..6bddede 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -41,7 +41,6 @@
 #undef CONFIG_SPL_NET_VCI_STRING
 #undef CONFIG_SPL_ETH_SUPPORT
 
-#define CONFIG_PHY_ADDR			1
 #define CONFIG_PHY_NATSEMI
 
 #define CONFIG_FACTORYSET
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
new file mode 100644
index 0000000..91cc7d8
--- /dev/null
+++ b/include/configs/sama5d3_xplained.h
@@ -0,0 +1,203 @@
+/*
+ * Configuration settings for the SAMA5D3 Xplained board.
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ		        1000
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT		/* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		4
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_ATMEL_MCI_8BIT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#if CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
+				"nand read 0x22000000 0x200000 0x600000;" \
+				"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256K(env),256k(evn_redundent),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#endif
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index c34feb5..516be85 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -258,6 +258,8 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 
 #define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
 #ifdef CONFIG_SYS_USE_MMC
 #define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl.lds
 #define CONFIG_SPL_MMC_SUPPORT
@@ -267,6 +269,27 @@
 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#elif CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
+
 #endif
 
 #endif
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index e1a3bbc..76dad4e 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -66,27 +66,63 @@
 #define BOOT_TARGETS_DHCP ""
 #endif
 
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTCMDS_PXE \
+	"bootcmd_pxe=" \
+		BOOTCMD_INIT_USB \
+		"dhcp; " \
+		"if pxe get; then " \
+			"pxe boot; " \
+		"fi\0"
+#define BOOT_TARGETS_PXE "pxe"
+#else
+#define BOOTCMDS_PXE ""
+#define BOOT_TARGETS_PXE ""
+#endif
+
 #define BOOTCMDS_COMMON \
 	"rootpart=1\0" \
 	\
+	"do_script_boot="                                                 \
+		"load ${devtype} ${devnum}:${rootpart} "                  \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
 	"script_boot="                                                    \
-		"if load ${devtype} ${devnum}:${rootpart} "               \
-				"${scriptaddr} ${prefix}${script}; then " \
-			"echo ${script} found! Executing ...;"            \
-			"source ${scriptaddr};"                           \
-		"fi;\0"                                                   \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} ${devnum}:${rootpart} "    \
+					"${prefix}${script}; then "       \
+				"echo Found U-Boot script "               \
+					"${prefix}${script}; "            \
+				"run do_script_boot; "                    \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"do_sysboot_boot="                                                \
+		"sysboot ${devtype} ${devnum}:${rootpart} any "           \
+			"${scriptaddr} ${prefix}extlinux.conf\0"          \
+	\
+	"sysboot_boot="                                                   \
+		"if test -e ${devtype} ${devnum}:${rootpart} "            \
+				"${prefix}extlinux.conf; then "           \
+			"echo Found extlinux config "                     \
+				"${prefix}extlinux.conf; "                \
+			"run do_sysboot_boot; "                           \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
 	\
 	"scan_boot="                                                      \
 		"echo Scanning ${devtype} ${devnum}...; "                 \
 		"for prefix in ${boot_prefixes}; do "                     \
-			"for script in ${boot_scripts}; do "              \
-				"run script_boot; "                       \
-			"done; "                                          \
-		"done;\0"                                                 \
+			"run sysboot_boot; "                              \
+			"run script_boot; "                               \
+		"done\0"                                                  \
 	\
 	"boot_targets=" \
 		BOOT_TARGETS_MMC " " \
 		BOOT_TARGETS_USB " " \
+		BOOT_TARGETS_PXE " " \
 		BOOT_TARGETS_DHCP " " \
 		"\0" \
 	\
@@ -96,7 +132,8 @@
 	\
 	BOOTCMDS_MMC \
 	BOOTCMDS_USB \
-	BOOTCMDS_DHCP
+	BOOTCMDS_DHCP \
+	BOOTCMDS_PXE
 
 #define CONFIG_BOOTCOMMAND \
 	"set usb_need_init; " \
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 9247aef..ae786cf 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -29,7 +29,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
 /* Environment */
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
@@ -69,33 +68,20 @@
 #undef CONFIG_CMD_NET		/* network support */
 
 /* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
 
 /* turn on commonly used storage-related commands */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
 #define CONFIG_PARTITION_UUIDS
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_PART
 
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT		V_PROMPT
 /*
  * Increasing the size of the IO buffer as default nfsargs size is more
@@ -133,8 +119,6 @@
 #define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
 
 /* Defines for SPL */
 #define CONFIG_SPL
@@ -161,4 +145,8 @@
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CRC32_VERIFY
 
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
 #endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index a4e8a5f..555c237 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -26,11 +26,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114			/* in a NVidia Tegra114 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -51,6 +46,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -68,6 +66,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
@@ -83,5 +82,6 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 0a4541b..61e5026 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -18,11 +18,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124			/* is an NVIDIA Tegra124 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -79,5 +74,6 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index b009a31..21bf977 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -24,11 +24,6 @@
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
 
@@ -49,6 +44,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -66,6 +64,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x10000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
 	"kernel_addr_r=0x01000000\0" \
 	"fdt_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0"
@@ -96,6 +95,7 @@
  */
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS	4
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index b5550d7..443c842 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -23,11 +23,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -48,6 +43,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -65,6 +63,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
@@ -80,5 +79,6 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index ba16b1c..b51400c 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -233,7 +233,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			1
 #define CONFIG_PHY_ET1011C
 #define CONFIG_PHY_ET1011C_TX_CLK_FIX
 
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 7e9ca01..50c3203 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -30,6 +30,7 @@
 /* Network defines. */
 #define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
 #define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/cpsw.h b/include/cpsw.h
index 743cb96..a73843d 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -19,7 +19,7 @@
 struct cpsw_slave_data {
 	u32		slave_reg_ofs;
 	u32		sliver_reg_ofs;
-	int		phy_id;
+	int		phy_addr;
 	int		phy_if;
 };
 
diff --git a/include/nand.h b/include/nand.h
index 84116f4..fc735d1 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -21,10 +21,16 @@
  * at the same time, so do it here.  When all drivers are
  * converted, this will go away.
  */
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#else
 #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
 	|| defined(CONFIG_NAND_FSL_IFC)
 #define CONFIG_SYS_NAND_SELF_INIT
 #endif
+#endif
 
 extern void nand_init(void);