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| author | Robin Gong <b38343@freescale.com> | 2014-11-04 19:18:56 +0800 |
|---|---|---|
| committer | Robin Gong <b38343@freescale.com> | 2014-11-11 10:54:29 +0800 |
| commit | 26875f93ac7e84748fa63e5f0dd948d12e663e43 (patch) | |
| tree | fdeedfaec463d69691d2e3e4f9a8fc194b67a238 | |
| parent | 9dfb4a5ee01740eadb751ca5c9edfbec6f5059e3 (diff) | |
| download | u-boot-imx-26875f93ac7e84748fa63e5f0dd948d12e663e43.zip u-boot-imx-26875f93ac7e84748fa63e5f0dd948d12e663e43.tar.gz u-boot-imx-26875f93ac7e84748fa63e5f0dd948d12e663e43.tar.bz2 | |
MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sx
Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable
bit to avoid system reboot during normal kernel boot.
For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready
before mux ready, otherwise also cause reboot. But that dependes on hardware
design, only need on mx6sxsabresd board.
Signed-off-by: Robin Gong <b38343@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 4 | ||||
| -rw-r--r-- | board/freescale/mx6sxsabresd/mx6sxsabresd.c | 15 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index d7c109e..01776a6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -228,6 +228,10 @@ static void imx_set_wdog_powerdown(bool enable) { struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; +#ifdef CONFIG_MX6SX + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + writew(enable, &wdog3->wmcr); +#endif /* Write to the PDE (Power Down Enable) bit */ writew(enable, &wdog1->wmcr); diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 1973bc0..b6a18f5 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -72,6 +72,8 @@ DECLARE_GLOBAL_DATA_PTR; #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm) +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -175,6 +177,10 @@ static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const wdog_b_pad = { + MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + #ifdef CONFIG_FEC_MXC static iomux_v3_cfg_t const fec1_pads[] = { MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -865,6 +871,15 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, ARRAY_SIZE(peri_3v3_pads)); |