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authorAndy Fleming <afleming@freescale.com>2007-10-19 11:24:22 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-10-19 11:24:22 -0500
commitd4d1e9bee7c45ea8c513d3af697c864107f1c4d1 (patch)
tree3cd7eba359e6729454f4fac5b96209eb959ecf72
parent1487adbdcf9594bb2eb686325a6f9540dad1b70a (diff)
parent27d2b1ed216b457a66c17d38ce5ffdf3c2c32d1e (diff)
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Merge branch 'denx'
-rw-r--r--CHANGELOG1419
-rwxr-xr-xMAKEALL4
-rw-r--r--Makefile42
-rw-r--r--board/ads5121/u-boot.lds1
-rw-r--r--board/amcc/katmai/init.S12
-rw-r--r--board/amcc/katmai/katmai.c25
-rw-r--r--board/amcc/luan/luan.c17
-rw-r--r--board/amcc/sequoia/cmd_sequoia.c17
-rw-r--r--board/amcc/sequoia/init.S3
-rw-r--r--board/amcc/sequoia/sequoia.c7
-rw-r--r--board/amcc/taishan/taishan.c4
-rw-r--r--board/amcc/yosemite/yosemite.c7
-rw-r--r--board/amcc/yucca/init.S12
-rw-r--r--board/amcc/yucca/yucca.c25
-rw-r--r--board/at91rm9200dk/led.c2
-rw-r--r--board/atmel/atstk1000/flash.c4
-rw-r--r--board/bf533-ezkit/bf533-ezkit.c3
-rw-r--r--board/bf533-stamp/bf533-stamp.c3
-rw-r--r--board/bf537-stamp/bf537-stamp.c3
-rw-r--r--board/bf561-ezkit/bf561-ezkit.c3
-rw-r--r--board/cm5200/cm5200.c1
-rw-r--r--board/cm5200/cmd_cm5200.c2
-rw-r--r--board/davinci/dv-evm/dv_board.c6
-rw-r--r--board/davinci/schmoogie/dv_board.c6
-rw-r--r--board/davinci/sonata/dv_board.c6
-rw-r--r--board/fads/fads.h1
-rw-r--r--board/freescale/common/pixis.c3
-rw-r--r--board/freescale/common/pq-mds-pib.c26
-rw-r--r--board/freescale/m5235evb/mii.c2
-rw-r--r--board/freescale/m5329evb/mii.c2
-rw-r--r--board/freescale/m54455evb/mii.c2
-rw-r--r--board/freescale/mpc8313erdb/sdram.c3
-rw-r--r--board/icecube/icecube.c7
-rw-r--r--board/jupiter/jupiter.c8
-rw-r--r--board/lpc2292sodimm/lpc2292sodimm.c7
-rw-r--r--board/m5271evb/mii.c2
-rw-r--r--board/m5272c3/mii.c2
-rw-r--r--board/m5282evb/mii.c2
-rw-r--r--board/motionpro/motionpro.c8
-rw-r--r--board/mpc7448hpc2/mpc7448hpc2.c4
-rw-r--r--board/mpc7448hpc2/tsi108_init.c4
-rw-r--r--board/mpl/vcma9/cmd_vcma9.c4
-rw-r--r--board/mpl/vcma9/vcma9.c4
-rw-r--r--board/sbc2410x/sbc2410x.c5
-rw-r--r--board/siemens/SMN42/smn42.c7
-rw-r--r--board/stxssa/stxssa.c11
-rw-r--r--board/stxssa/u-boot.lds1
-rw-r--r--board/tqm5200/tqm5200.c13
-rw-r--r--board/trizepsiv/Makefile51
-rw-r--r--board/trizepsiv/config.mk3
-rw-r--r--board/trizepsiv/conxs.c146
-rw-r--r--board/trizepsiv/eeprom.c85
-rw-r--r--board/trizepsiv/lowlevel_init.S503
-rw-r--r--board/trizepsiv/pxavoltage.S (renamed from include/led.h)30
-rw-r--r--board/trizepsiv/u-boot.lds56
-rw-r--r--common/Makefile3
-rw-r--r--common/cmd_bootm.c67
-rw-r--r--common/cmd_fpga.c2
-rw-r--r--common/cmd_mfsl.c16
-rw-r--r--common/cmd_nand.c6
-rw-r--r--common/cmd_nvedit.c9
-rw-r--r--common/cmd_onenand.c155
-rw-r--r--common/env_onenand.c134
-rw-r--r--common/environment.c13
-rw-r--r--common/serial.c13
-rw-r--r--cpu/arm1136/config.mk1
-rw-r--r--cpu/arm720t/serial.c4
-rw-r--r--cpu/arm920t/start.S128
-rw-r--r--cpu/bf533/serial.c1
-rw-r--r--cpu/bf537/i2c.c3
-rw-r--r--cpu/bf537/serial.c3
-rw-r--r--cpu/bf561/serial.c3
-rw-r--r--cpu/mcf532x/cpu.c4
-rw-r--r--cpu/mcf532x/speed.c4
-rw-r--r--cpu/microblaze/cache.c2
-rw-r--r--cpu/microblaze/start.S6
-rw-r--r--cpu/microblaze/timer.c7
-rw-r--r--cpu/mpc512x/config.mk2
-rw-r--r--cpu/mpc512x/fec.c38
-rw-r--r--cpu/mpc512x/fec.h7
-rw-r--r--cpu/mpc5xxx/cpu.c66
-rw-r--r--cpu/mpc86xx/cpu_init.c3
-rw-r--r--cpu/mpc86xx/spd_sdram.c30
-rw-r--r--cpu/mpc86xx/speed.c2
-rw-r--r--cpu/mpc86xx/traps.c4
-rw-r--r--cpu/ppc4xx/405gp_pci.c17
-rw-r--r--cpu/ppc4xx/440spe_pcie.c162
-rw-r--r--cpu/ppc4xx/440spe_pcie.h16
-rw-r--r--cpu/ppc4xx/4xx_enet.c16
-rw-r--r--cpu/ppc4xx/traps.c6
-rw-r--r--cpu/pxa/mmc.c6
-rw-r--r--cpu/pxa/serial.c351
-rw-r--r--cpu/pxa/usb.c16
-rwxr-xr-xdrivers/Makefile2
-rw-r--r--[-rwxr-xr-x]drivers/at45.c316
-rw-r--r--drivers/bios_emulator/Makefile23
-rw-r--r--drivers/dm9000x.c16
-rw-r--r--drivers/isp116x-hcd.c112
-rw-r--r--drivers/nand/nand_util.c21
-rw-r--r--drivers/onenand/Makefile44
-rw-r--r--drivers/onenand/onenand_base.c1294
-rw-r--r--drivers/onenand/onenand_bbt.c265
-rw-r--r--drivers/pci_auto.c8
-rw-r--r--drivers/qe/qe.c7
-rw-r--r--drivers/serial_xuartlite.c2
-rw-r--r--drivers/sil680.c110
-rw-r--r--drivers/tsec.c2
-rw-r--r--drivers/usb_ohci.c1
-rw-r--r--drivers/usbdcore_mpc8xx.c3
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h18
-rw-r--r--include/asm-avr32/string.h2
-rw-r--r--include/asm-mips/string.h156
-rw-r--r--include/common.h2
-rw-r--r--include/config_cmd_all.h3
-rw-r--r--include/configs/ASH405.h3
-rw-r--r--include/configs/CATcenter.h2
-rw-r--r--include/configs/CMS700.h3
-rw-r--r--include/configs/FADS823.h1
-rw-r--r--include/configs/FADS850SAR.h1
-rw-r--r--include/configs/FPS850L.h60
-rw-r--r--include/configs/FPS860L.h46
-rw-r--r--include/configs/HH405.h3
-rw-r--r--include/configs/HUB405.h3
-rw-r--r--include/configs/ICU862.h1
-rw-r--r--include/configs/IceCube.h2
-rw-r--r--include/configs/M5271EVB.h5
-rw-r--r--include/configs/PLU405.h3
-rw-r--r--include/configs/PPChameleonEVB.h2
-rw-r--r--include/configs/R360MPI.h1
-rw-r--r--include/configs/RRvision.h2
-rw-r--r--include/configs/TQM5200.h43
-rw-r--r--include/configs/TQM823L.h7
-rw-r--r--include/configs/TQM823M.h7
-rw-r--r--include/configs/TQM850L.h7
-rw-r--r--include/configs/TQM850M.h7
-rw-r--r--include/configs/TQM855L.h7
-rw-r--r--include/configs/TQM855M.h7
-rw-r--r--include/configs/TQM85xx.h2
-rw-r--r--include/configs/TQM860L.h7
-rw-r--r--include/configs/TQM860M.h7
-rw-r--r--include/configs/TQM862L.h7
-rw-r--r--include/configs/TQM862M.h7
-rw-r--r--include/configs/TQM866M.h7
-rw-r--r--include/configs/VOH405.h3
-rw-r--r--include/configs/ads5121.h9
-rw-r--r--include/configs/atstk1002.h39
-rw-r--r--include/configs/cmi_mpc5xx.h5
-rw-r--r--include/configs/hymod.h1
-rw-r--r--include/configs/idmr.h2
-rw-r--r--include/configs/jupiter.h2
-rw-r--r--include/configs/katmai.h13
-rw-r--r--include/configs/lwmon5.h16
-rw-r--r--include/configs/ml401.h53
-rw-r--r--include/configs/motionpro.h2
-rw-r--r--include/configs/sequoia.h5
-rw-r--r--include/configs/spc1920.h9
-rw-r--r--include/configs/stxssa.h22
-rw-r--r--include/configs/suzaku.h19
-rw-r--r--include/configs/trab.h2
-rw-r--r--include/configs/trizepsiv.h325
-rw-r--r--include/configs/virtlab2.h2
-rw-r--r--include/configs/xupv2p.h37
-rw-r--r--include/configs/yosemite.h2
-rw-r--r--include/configs/yucca.h13
-rw-r--r--include/image.h1
-rw-r--r--include/libfdt.h2
-rw-r--r--include/linux/mtd/bbm.h127
-rw-r--r--include/linux/mtd/onenand.h143
-rw-r--r--include/linux/mtd/onenand_regs.h181
-rw-r--r--include/onenand_uboot.h39
-rw-r--r--include/serial.h4
-rw-r--r--include/status_led.h21
-rw-r--r--lib_arm/board.c33
-rw-r--r--lib_avr32/board.c12
-rw-r--r--lib_blackfin/board.c7
-rw-r--r--lib_blackfin/post.c10
-rw-r--r--lib_microblaze/time.c8
-rw-r--r--libfdt/fdt_rw.c26
-rw-r--r--nand_spl/board/amcc/bamboo/Makefile6
-rw-r--r--net/bootp.c2
-rw-r--r--net/net.c4
181 files changed, 6693 insertions, 1143 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 2749d69..b038749 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,1299 @@
+commit 68f14f77ca5fe5f9cc025c8cae101671f628309f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Sep 29 13:41:37 2007 +0200
+
+ Fix warning differ in signedness in cpu/pxa/mmc.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit fc19e36f741e8bc727c0a330170b3b5db90399ef
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Oct 13 23:51:14 2007 +0200
+
+ Fix warning differ in signedness in board/mpl/vcma9/vcma9.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit de74b9eeacccaf0a42e5ecc9ae79a88f7a311296
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Oct 13 21:15:39 2007 +0200
+
+ Coding Style cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e1893815b0999410d7a327589611c7b38e95299e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Oct 12 15:49:39 2007 +0200
+
+ GP3 SSA: enable RTC
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8002012041f1ff9f997a5727abe5015f70cd2e46
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Oct 9 13:58:24 2007 +0200
+
+ [ads5121] EEPROM support added.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 7b624ad254b97e5a25dca2304a398b64aeedaffe
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Sat Oct 6 18:55:35 2007 +0200
+
+ AVR32: Initialize bi_flash* in board_init_r
+
+ The ATSTK1000-specific flash driver intializes bi_flashstart,
+ bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI
+ driver, don't.
+
+ Initialize these in board_init_r instead so that things will still be
+ set up correctly when we switch to the CFI driver.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 2b2a587d6d3076387d22ac740f44044bf46e2cb8
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Fri Oct 5 10:40:54 2007 +0200
+
+ tqm5200: Fix CONFIG_CMD_PCI typo in board config file.
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 92869195ef8210758d2176230c0a36897afd50ed
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Fri Oct 5 09:46:06 2007 +0200
+
+ CM5200: Fix missing null-termination in hostname manipulation code
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 9add9884b1fddc34ca186e00a2f868ccd5d02d87
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Tue Oct 2 19:09:01 2007 +0200
+
+ Fix memtest breakage
+
+ CFG_MEMTEST_START uses weird magic involving gd, which fails to
+ compile. Use hardcoded values instead (we actually know how much RAM
+ we have on board.)
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 738815c0cc44aa329097f868dc1efc49ede9c5ba
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 2 11:44:46 2007 +0200
+
+ ppc4xx: Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 87c1833a39e944db66385286fd5e28f9b3fcdd50
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 2 11:44:19 2007 +0200
+
+ ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2db64784061bfc34f4ba70ef1d2fbe7133b55670
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Mon Oct 1 09:51:50 2007 +0200
+
+ Program EPLD to force full duplex mode for PHY.
+
+ EPLD forces modes of PHY operation. By default full duplex is turned off.
+ This fix turns it on.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 86ec86c04326c3913178a7679aa910de071da75d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Sep 27 23:27:47 2007 +0200
+
+ Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3e954beb614b5b190d7f4f4c3b641437a0132e35
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Sep 11 14:12:55 2007 +0200
+
+ ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test)
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Sep 25 15:48:05 2007 -0600
+
+ Fpga: fix incorrect test of CFG_FPGA_XILINX macro
+
+ CFG_FPGA_XILINX is a bit value used to test against the value in
+ CONFIG_FPGA. Testing for a value will always return TRUE. I don't
+ think that is the intention in this code.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 853643d8cf2ca80cb2e25c53ad5dc580abafe166
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:41:30 2007 +0200
+
+ [FIX] change command handling and removing code violation
+
+commit f240356507038e5ce55e8a24cb2607e9eae6d10c
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:36:06 2007 +0200
+
+ [FIX] change sets of commands
+ because changing of command handling brings
+ compilation problems
+
+commit cb1bc63b75a232571eb69aa2c8aa919321655845
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:30:42 2007 +0200
+
+ [FIX] Email reparation & Copyright
+ Both codes are written by myself without any
+ support from CTU
+
+commit 0731cbae6c2feab93b244d83fd6a43f5cc9bf852
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:25:11 2007 +0200
+
+ [PATCH] Change macro name for UartLite
+ because PowerPC 405 can use UartLite as console
+
+commit 1c1100d2fcf46b9d11dcf78d6e5aea75e2e8b716
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:21:19 2007 +0200
+
+ [PATCH] Add support for design without interrupt controller
+ Polling timer
+
+commit 0731933ec8ec45d02ba89b52df673d526873cdde
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:19:48 2007 +0200
+
+ [FIX] resolve problem with cpu without barrel shifter
+
+commit db14d77995ce515b728b178b63f82babe60e3d56
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:18:46 2007 +0200
+
+ [FIX] repair email address
+
+commit 481d4328618804add1f818a6c96296121cd0528e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:17:42 2007 +0200
+
+ [FIX] repair MFSL commands
+
+commit b90c045f035c3cc9b5d2edaed6048dfb74e40763
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:08:37 2007 +0200
+
+ synchronizition with mainline
+
+commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Sep 20 00:04:14 2007 +0200
+
+ v1.3.0-rc2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 135e19bc2773ebca487e9a8371f67e1ba202313a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Sep 18 21:36:35 2007 +0200
+
+ Avoid compiler warning.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8a783a65851bc7421ab69f442261215e21b8891a
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Sep 18 12:24:57 2007 -0600
+
+ Bugfix: remove embedded null (\0) from CFG_BOOTFILE macro in TQM8540_config
+
+ /bin/bash and /bin/dash (which /bin/sh is linked to on ubuntu) handle embedded
+ nulls in a string differently. For example, the following statement:
+ echo "this is a string\0" > afile
+ Will produce the following with /bin/bash:
+ "this is a string\0"
+ But with /bin/dash, will produce:
+ "this is a string
+
+ Bug fixed by moving the embedded null out of the makefile and into the
+ config header. Also renamed the macro to avoid usage colision with the same
+ macro used by other board ports.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit f8d3ca7b6fa322ac57e8e831f07dbeea039a9f35
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Sep 18 17:40:27 2007 +0200
+
+ MCC200: fix build warning
+
+ The MCC200 board config file includes version.h for some customer-
+ specific setting, which causes warnings with "make depend"; build
+ version.h before depend.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit bd86220f58b99d6896198c385fda132f0c980915
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 18 13:07:54 2007 +0100
+
+ Move coloured led API to status_led.h
+ Improve indentation in drivers/at45.c
+
+commit e80e585b00fbbab7ad1bf71619741f2c5b029ab7
+Author: Eirik Aanonsen <eaa@wprmedical.com>
+Date: Tue Sep 18 08:47:20 2007 +0200
+
+ Update atstk1002 bootargs.
+
+ Updates to atstk1002 U-Boot header file:
+ - Changed bootargs:
+ * Set the bootargs for at1002 to point to the SD-card partition instead
+ * ... of the boot flash.
+ * Removing the rootfstype since that argument are not needed.
+
+ Signed-off-by: Eirik Aanonsen <eaa@wprmedical.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit a4f3aab6dfbed6c29367c688bfb8a47eef62c225
+Author: Eirik Aanonsen <eaa@wprmedical.com>
+Date: Wed Sep 12 13:32:37 2007 +0200
+
+ Add some comments to clocks in atstk1002.h
+
+ This patch applies some clarifying comments to how the different
+ clocks are setup according to atstk1002.h Some of the previous
+ comments where stating wrongful information.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 97213f32416ead885deafea86774e912ffd60ad0
+Author: David Saada <David.Saada@ecitele.com>
+Date: Mon Sep 17 17:04:47 2007 +0200
+
+ Description: Add NEC's PCI OHCI module ID to the USB OHCI driver
+
+ Signed-off-by: David Saada <david.saada@ecitele.com>
+
+commit 30363e98fa470fbecea5e8bc0f1443352754f303
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Sep 17 08:20:47 2007 +0200
+
+ Small whitespace cleanup of OneNAND patch
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d7e8ce101a4a45ed6ed45739fc2de5f87b13f7f1
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 17:15:14 2007 +0900
+
+ OneNAND support (take #2)
+
+ [PATCH 3/3] OneNAND support (take #2)
+
+ OneNAND support at U-Boot
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 17aa2800457df0c06b41516f46f126712c196219
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 17:14:34 2007 +0900
+
+ OneNAND support (take #2)
+
+ [PATCH 2/3] OneNAND support (take #2)
+
+ OneNAND support at U-Boot
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 916527f4809a7bcd811f1f1daf34af184e31dd8c
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 17:13:49 2007 +0900
+
+ OneNAND support (take #2)
+
+ [PATCH 1/3] OneNAND support (take #2)
+
+ OneNAND support at U-Boot
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 67c31036acaaaa992fc346cc89db0909a7e733c4
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Sep 16 17:10:04 2007 +0200
+
+ TQM8xx[LM]: Fix broken environment alignment.
+
+ With recent toolchains, the environment sectors were no longer aligned to
+ sector boundaries. The reason was a combination of two bugs:
+
+ 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined
+ for all TQM8xxL and TQM8xxM boards. But "include/common.h", where
+ this gets defined, is not included here (and cannot be included
+ without causing lots of problems).
+
+ Added a new #define CFG_USE_PPCENV for all boards which really
+ want to put the environment is a ".ppcenv" section.
+
+ 2) The linker scripts just include environment.o, silently assuming
+ that the objects in that file are really in the order in which
+ they are coded in the C file, i. e. "environment" first, then
+ "redundand_environment", and "env_size" last. However, current
+ toolchains (GCC-4.x) reorder the objects, causing the environment
+ data not to start on a flash sector boundary:
+
+ Instead of: we got:
+
+ 40008000 T environment 40008000 T env_size
+ 4000c000 T redundand_environment 40008004 T redundand_environment
+ 40010000 T env_size 4000c004 T environment
+
+ Note: this patch fixes just the first part, and cures the alignment
+ problem by making sure that "env_size" gets placed correctly. However,
+ we still have a potential issue because primary and redundant
+ environment sectors are actually swapped, i. e. we have now:
+
+ 40008000 T redundand_environment
+ 4000c000 T environment
+ 40010000 T env_size
+
+ This shall be fixed in the next version.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit eb6da8050797c204c9d010548424186c7ce32fc1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Sep 16 02:39:35 2007 +0200
+
+ TQM8xx/FPS8xx: adjust flash partitions for 2.6 ARCH=powerpc kernels
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cd2d1602c54cc6957bdef3872272a4b264893960
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date: Mon Sep 10 14:54:56 2007 -0400
+
+ Typo fix in tsec.c
+
+ Fixup for the break statement in wrong place.
+
+ [Patch by urwithsughosh@gmail.com]
+ Acked-by: Andy Fleming <afleming@freescale.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5bd7fe9aeb76906371f40b8fd07613f10922e3e7
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Tue Sep 11 17:04:00 2007 +0200
+
+ Fix do_div() usage in nand process output
+
+ Fix usage of do_div() in nand erase|read|write process output.
+
+ The last patch to nand_util.c introduced do_div() instead of libgcc's
+ implementation. But do_div() returns the quotient in its first
+ macro parameter and not as result.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit c750d2e6692a000a82f29de7bf24e3dc21239161
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Sep 12 12:36:53 2007 +0200
+
+ NAND: Add CFG_NAND_QUIET option
+
+ This config option sets the default for the progress information
+ output behavior that can also be configured through the 'quiet'
+ environment variable.
+
+ The legacy NAND code does not print the current progress info
+ on the console. So this option is for backward compatibility for
+ units that are in the field and where setting the quiet variable
+ is not an option. With CFG_NAND_QUIET set to '1' the console
+ progress info is turned off. This can still be overwritten
+ through the environment variable.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit dcb88630290d2bcd803386dd4c2be73142994c4f
+Author: Liew Tsi Chung-r5aahp <Tsi-chung.Liew@freescale.com>
+Date: Thu Sep 13 16:06:05 2007 -0700
+
+ ColdFire: fix build error becasue of bad type of mii_init()
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 314d5b6ce52a4ed19dd295d1364e246c5e605017
+Author: Liew Tsi Chung-r5aahp <Tsi-chung.Liew@freescale.com>
+Date: Thu Sep 13 16:04:05 2007 -0700
+
+ ColdFire: Fix build error caused by pixis.c
+
+ Moved the #include <asm/cache.h> inside the #ifdef CONFIG_FSL_PIXIS.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit e21659e30660a1377c42af135a6114efe39801d9
+Author: Sam Sparks <SSparks@twacs.com>
+Date: Fri Sep 14 11:14:42 2007 -0600
+
+ Update MPC8349ITX*_config to place config.tmp in right place.
+
+ MPC834ITX*_config does not store config.tmp at the correct locatation,
+ causing MPC8349ITXGP to have the wrong TEXT_BASE.
+
+ Signed-off-by: Sam Sparks <SSparks@twacs.com>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 1218abf1b5817a39a82399b4b928b00750575bda
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Sep 15 20:48:41 2007 +0200
+
+ Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 66b3f24d665be678a9dbb125b1e84185400f63b5
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Sep 15 11:55:42 2007 +0200
+
+ Make DECLARE_GLOBAL_DATA_PTR global for DaVinci
+
+ As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not
+ function local.
+
+ Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+ [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805
+
+commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Thu Sep 13 18:21:48 2007 +0200
+
+ cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit e1f601b572db5de9aa81a0b77c68a86994fe24c4
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Thu Sep 13 16:33:59 2007 +0200
+
+ tqm5200: Restore customary env. variable boot commands for powerpc kernels
+
+ - update default definitions of kernel_addr and fdt_addr env. variables
+ - make arch/powerpc booting the default scenario
+ - update MTD partition layout to match the above
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit f34024d4a328e6edd906456da98d2c537155c4f7
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Sep 12 00:48:57 2007 +0200
+
+ Fix memory corruption problem on STX GP3 SSA Board.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d94c79e47011af5e8dd10ed6163c09b4cfc743cc
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 11 15:35:01 2007 +0100
+
+ Final tidy
+
+commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Sep 11 15:42:11 2007 +0200
+
+ [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to
+ scan on second pci bus.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 6c2f4f388e8181655ea8b69343ea00b68aa6e8d0
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Sep 11 12:57:52 2007 +0200
+
+ [ppc4xx] Individual handling of sdram.c for bamboo_nand build
+
+ Bamboo has a file sdram.c which needs special treatment when building in
+ separate directory. It has to be linked to build directory otherwise it is
+ not seen.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit d45963854eff39d575124d859419bb4953ce2c87
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Sep 11 00:37:04 2007 +0200
+
+ [FIX] Microblaze ML401 - repare FLASH handling
+
+commit 38c1ef728d19950414a8ab1ccfc53767848fa346
+Author: Sean MCGOOGAN <sean.mcgoogan@st.com>
+Date: Mon Sep 10 16:55:59 2007 +0100
+
+ Allocate CPU Architecture Code for STMicroelectronics' ST200.
+
+ Signed-off-by: Sean McGoogan <Sean.McGoogan@st.com>
+ ---------------------------------------------------
+
+commit 754bac48156f8958d8f6a53a51eda88ab5758929
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Sep 10 20:42:31 2007 +0200
+
+ Update version to match current state.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7a888d6b3c32a126dbb504ef146bb4c26574ca7b
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Mon Sep 10 17:39:08 2007 +0200
+
+ [MPC512x] Streamline frame handling in the FEC driver
+
+ - convert frame size settings to be derived from a single base
+ - set frame size to the recommended default value
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit e251e00d0db4b36d1d2b7e38fec43a7296b529a2
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 11:34:00 2007 +0900
+
+ Remove compiler warning: target CPU does not support interworking
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 1d9e31e04911a6bb7cc66dd91132c699101c32e2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Sep 9 21:21:33 2007 +0200
+
+ Fix compile error in spc1920 config.
+
+ Signed-off-by: Markus Klotzbücher <mk@denx.de>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a7d7eca791a37f452c9da10fef4b31dd7aa9a622
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Fri Sep 7 09:25:07 2007 -0600
+
+ Bugfix: make bootm+libfdt compile on boards with no flash
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 18:35:37 2007 +0200
+
+ [PPC440SPe] PCIe environment settings for Katmai and Yucca
+
+ - 'pciconfighost' is set by default in order to be able to scan bridges
+ behind the primary host/PCIe
+
+ - 'pciscandelay' env variable is recognized to allow for user-controlled
+ delay before the PCIe bus enumeration; some peripheral devices require a
+ significant delay before they can be scanned (e.g. LSI8408E); without the
+ delay they are not detected
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 7f1913938984ef6c6a46cb53e003719196d9c5de
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 18:20:23 2007 +0200
+
+ [PPC440SPe] Improve PCIe configuration space access
+
+ - correct configuration space mapping
+ - correct bus numbering
+ - better access to config space
+
+ Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
+ first device on the first bus. We now allow to configure up to 16 buses;
+ also, scanning for devices behind the PCIe-PCIe bridge is supported, so
+ peripheral devices farther in hierarchy can be identified.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 15ee4734e4e08003d73d9ead3ca80e2a0672e427
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 17:46:18 2007 +0200
+
+ [PPC440SPe] Convert machine check exceptions handling
+
+ Convert using fixup mechanism to suppressing MCK for the duration of config
+ read/write transaction: while fixups work fine with the case of a precise
+ exception, we identified a major drawback with this approach when there's
+ an imprecise case. In this scenario there is the following race condition:
+ the fixup is (by design) set to catch the instruction following the one
+ actually causing the exception; if an interrupt (e.g. decrementer) happens
+ between those two instructions, the ISR code is executed before the fixup
+ handler the machine check is no longer protected by the fixup handler as it
+ appears as within the ISR code. In consequence the fixup approach is being
+ phased out and replaced with explicit suppressing of MCK during a PCIe
+ config read/write cycle.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit ff7640c9ead8806b5d827f2b29f9cb2632add729
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Sep 7 17:43:36 2007 +0200
+
+ Fix typo in MAKEALL script.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 08e2e5fcd2e06670b62e1680a3934c0e55c72810
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 17:09:21 2007 +0200
+
+ [MPC512x] Proper handling of larger frames in the FEC driver
+
+ When frame larger than local RX buffer is received, it is split and handled
+ by two buffer descriptors. Prior to this patch the FEC driver discarded
+ contents of a buffer descriptor without the 'LAST' bit set, so the first
+ part of the frame was lost in case of larger frames. This fix allows to
+ safely combine the two pieces into the whole frame.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 8d17979d0359492a822a0a409d26e3a3549b4cd4
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Sep 7 17:05:36 2007 +0200
+
+ [MPC512x] Correct fixup relocation
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit a89cbbd27a60e6740772000fd0688ffba1c2576a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Sep 7 01:21:25 2007 +0200
+
+ Update CHANGELOG, minor coding style cleanup.
+
+commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3
+Author: stefano babic <sbabic@denx.de>
+Date: Thu Aug 30 23:01:49 2007 +0200
+
+ PXA270: Added support for TrizepsIV board.
+
+ This patch add support for the Trizeps IV module (520Mhz).
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 80172c6181c912fbb34ea3ba0c22b232b419b47f
+Author: stefano babic <sbabic@denx.de>
+Date: Thu Aug 30 22:57:04 2007 +0200
+
+ PXA270: Add support for multiple serial ports.
+
+ This patch adds support for multiple serial ports to the PXA target.
+ FFUART, BTUART and STUART are supported.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e
+Author: stefano babic <sbabic@denx.de>
+Date: Thu Aug 30 22:48:47 2007 +0200
+
+ PXA270: fix compile issue (invalid lvalue)
+
+ Code is broken for PXA270 due to "invalid lvalue in assignment".
+
+ This patch fix it in pxa-regs.h
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 1d2ca446e1a731df420206d04fe278c27ea6b8e8
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Thu Aug 30 18:19:05 2007 +0800
+
+ Add BUILD_DIR support for bios emulator.
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit b4d8a55145442f136982634862341a3e02002bda
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Fri Aug 31 14:41:51 2007 +0900
+
+ [MIPS] Remove inline asm string functions
+
+ Stop using inline string functions on MIPS as other ARCHs do so,
+ since the optimized inline asm versions are not small.
+
+ This change is triggered by a following MIPS build error:
+ common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init':
+ common/exports.c:32: undefined reference to `strcmp'
+ make: *** [u-boot] Error 1
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Fri Aug 31 14:41:45 2007 +0900
+
+ [MIPS] Update asm string header
+
+ This patches contains several bugfixes and cleanups in the latest upstream:
+
+ - Don't include linux/config.h
+ - Remove buggy inline version of memscan.
+ - Merge with Linux 2.6.11-rc3.
+ - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4.
+ - Goodbye mips64. 31704 lines of code bite the dust.
+ - Replace extern inline with static inline.
+ - Fix return value of strncpy.
+ - Remove a bunch more "$1" clobbers.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Sep 4 17:31:22 2007 +0200
+
+ Fix do_bootm_linux() so that multi-file images with FDT blob boot.
+
+ Fix incorrect blob address calculation in do_bootm_linux() that prevents
+ booting the kernel from a multi-file image (kernel + initrd + blob).
+
+ Also, make minor updates to the U-Boot's output and to the coding style.
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 041a2554ad619e80dce520c1a33210affcb6a3f2
+Author: Gary Jennejohn <gary.jennejohn@freenet.de>
+Date: Fri Aug 31 14:29:04 2007 +0200
+
+ Add support for Sil680 IDE controller.
+
+ o add drivers/sil680.c to support the Sil680 IDE-controller.
+ o drivers/Makefile: add sil680.o.
+
+ Signed-off-by: Gary Jennejohn <garyj@denx.de>
+
+commit e79021223bc339df655e360645a52c457a74b067
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Sep 6 09:47:40 2007 -0600
+
+ bootm/fdt: Only process the fdt if an fdt address was provided
+
+ Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style
+ kernels using the board info structure (instead of passing a device tree)
+ This change allows the old style booting to be used if the fdt argument
+ was not passed to 'bootm'.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Sep 6 09:46:23 2007 -0600
+
+ Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT
+
+ Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200
+
+ Tested on: lite5200b
+
+ Note: the fixup functions have not been moved to a common place. This
+ patch is targeted for immediate merging as in solves a build issue, but
+ the final name/location of the fixups is still subject to debate. I
+ propose to merge this now, and move the fixups in the next merge window
+ to be usable by all targets.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 41bb76e941929f54a73206fb132f7a4c275543a3
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Sep 6 09:46:17 2007 -0600
+
+ libfdt: add convenience function fdt_find_and_setprop()
+
+ Given the path to a node, fdt_find_and_setprop() allows a property value
+ to be set directly.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 80767a6cead9990d9e77e62be947843c2c72f469
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Wed Sep 5 16:04:41 2007 +0100
+
+ Changed API name to coloured_led.h
+ Removed code using deprecated ifdef CONFIG_BOOTBINFUNC
+ Tidied other cpu/arm920t/start.S code
+
+commit 56a9270521baaa00e12639a978302a67f61ef060
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Aug 30 16:18:18 2007 -0500
+
+ Fix ULI RTC support on MPC8544 DS
+
+ The RTC on the M1575 ULI chipset requires a dummy read before
+ we are able to talk to the RTC. We accomplish this by adding a
+ second memory region to the PHB the ULI is on and read from it.
+
+ The second region is added to maintain compatiabilty with Linux's
+ view of the PCI memory map.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f75e89e9b5714db2b0e80074071dfbdd6f59488a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Thu Aug 30 01:58:48 2007 -0500
+
+ ft_board_setup update 85xx/86xx of pci/pcie bus-range property.
+
+ pcie is now differentiated from pci. Add 8641 bus-range updates.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 9f5c3d3720e777a572dcdc8af2008b44c7243885
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 16:18:38 2007 +0100
+
+ Add coloured led interface for ARM boards.
+ Use it in cpu/arm920t/start.S to indicate U-Boot code has been entered.
+
+commit 7462fe0d5a9d40cde083fb1a3cd73911996b5ecb
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 14:49:28 2007 +0100
+
+ Move include/led.h to board/at91rm9200dk
+
+commit 6e4bf9b24e57c15abc6542e685d06380bc64af27
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 14:25:51 2007 +0100
+
+ Ran Lindent on drivers/at45.c
+
+commit 557ab89d294f08dd532f21d19861b40093200a33
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 14:23:50 2007 +0100
+
+ Rename CONFIG_CMD_MUX to CONFIG_CMD_AT91_SPIMUX
+
+commit 81b73dec16fd1227369a191e725e10044a9d56b8
+Author: Gary Jennejohn <garyj@denx.de>
+Date: Fri Aug 31 15:21:46 2007 +0200
+
+ ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
+
+ The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
+ set to non-zero, because it doesn't support MRM (memory-read-
+ multiple) correctly. We now added the possibility to configure
+ this register in the board config file, so that the default value
+ of 8 can be overridden.
+
+ Here the details of this patch:
+
+ o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
+ board-specific settings. As an example the sequoia board requires 0.
+ Idea from Stefan Roese <sr@denx.de>.
+ o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
+ PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
+ o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
+ CFG_PCI_CACHE_LINE_SIZE to 0.
+
+ Signed-off-by: Gary Jennejohn <garyj@denx.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 60174746c668b309378a91488dded898e9553eae
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Aug 31 10:01:51 2007 +0200
+
+ Fix TFTP OACK code for short packets.
+
+ The old code had a loop limit overflow bug which caused a semi-
+ infinite loop for small packets, because in "i<len-8", "i" was signed,
+ but "len" was unsigned, and "len-8" became a huge number for small
+ values of "len".
+
+ This is a workaround which replaces broken commit 8f1bc284.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 696dd1307cd8e73a10e9bb3c51731bfd6f837bee
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date: Thu Aug 30 15:03:05 2007 +0200
+
+ Reduce BOOTDELAY variable to 1 second by default for STK1002
+
+ Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit c88b6e1cbf9a8ae2a34fb602f78a1bf4e6692b6a
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date: Thu Aug 30 15:03:04 2007 +0200
+
+ Remove double quotation marks around MAC address for STK1002
+
+ Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit ff13ac8c7bbebb238e339592de765c546dba1073
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Aug 30 14:42:15 2007 +0200
+
+ Backout commit 8f1bc284 as it causes TFTP to fail.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1900fbf255acba8b94fb442a16408ea85a1d46a6
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Thu Aug 30 02:26:17 2007 -0500
+
+ Revert "Fix MPC8544DS PCIe3 scsi."
+
+ This reverts commit 9468e680.
+ Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 8f1bc28408ded213418d9bc0780c7d8fb8a03774
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Wed Aug 29 18:26:24 2007 -0600
+
+ tftp: don't implicity trust the format of recevied packets
+
+ The TFTP OACK code trusts that the incoming packet is formated as
+ ASCII text and can be processed by string functions. It also has a
+ loop limit overflow bug where if the packet length is less than 8, it
+ ends up looping over *all* of memory to find the 'blksize' string.
+
+ This patch solves the problem by forcing the packet to be null
+ terminated and using strstr() to search for the sub string.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 04625764cc93ce8a61625ac19d7fe2a2ceee8143
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Aug 29 16:31:18 2007 +0200
+
+ ppc4xx: Change lwmon5 default environment to support Linux RTC
+
+ The Linux PCF8563 RTC driver doesn't do autoprobing, so we need
+ to supply the RTC I2C address as bootline parameter. This patch
+ adds support for this rtc probing parameter to the bootargs:
+
+ "rtc-pcf8563.probe=0,0x51"
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2602a5c40ae37ab965a4e240854fdaffb51328a4
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 29 09:06:05 2007 -0500
+
+ sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE
+
+ this had slipped through the cracks, since the sbc board was added
+ after I wrote the original patch to remove all these symbols, and
+ before it was merged.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c5bded3c88e48ae648a75d357dc81a8255fa81f1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Aug 29 14:05:30 2007 +0200
+
+ Add mii_init() prototype
+
+ to get rid of a *lot* of compiler warnings.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Aug 29 13:35:03 2007 +0200
+
+ Disable network support on cmi_mpc5xx board
+
+ ..because it caused compiler errors and there seems to be no
+ board maintainer to take care of this.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 9468e6804b7e25b0f6f52e53f47bce3175400a16
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Aug 20 09:44:00 2007 -0500
+
+ Fix MPC8544DS PCIe3 scsi.
+
+ <ed.swarthout@freescale.com>
+
+ The problem is pciauto_setup_device() getting called from fsl_pci_init.c
+ is allocating memory space it doesn't need.
+
+ Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 4bf4abb8a4e9955556b120a1aafa30c03e74032a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Tue Aug 21 09:38:59 2007 -0500
+
+ 8548cds fixes
+
+ Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the
+ correct consoledev needed for linux boot.
+ Standardize on fdt{file,addr} var to hold dtb file name.
+
+ Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu Aug 23 15:20:54 2007 -0400
+
+ Enable L2 cache for MPC8568MDS board
+
+ The L2 cache size is 512KB for 8568, print out the correct informaiton.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Wed Aug 22 17:54:49 2007 +0800
+
+ Remove the bios emulator binary files from MAI board
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 7608d75f9c87c9eb5b3a43219d0506d3e979a13f
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Tue Aug 21 17:00:17 2007 -0500
+
+ support board vendor-common makefiles
+
+ if a board/$(VENDOR)/common/Makefile exists, build it.
+
+ also add the first such case, board/freescale/common/Makefile, to
+ handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
+ dictated by board configuration.
+
+ thusly get rid of alternate build dir errors such as:
+
+ FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
+
+ by putting the common/ mkdir command in its proper place (the common
+ Makefile). Common bits from existing individual board Makefiles have
+ been removed.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd
+Author: stefano babic <sbabic@denx.de>
+Date: Tue Aug 21 15:52:33 2007 +0200
+
+ Fix: TFTP is not working on little endian systems
+
+ TFTP does not work anymore after multicast tftp
+ patch was applied on little endian systems.
+ This patch fix it.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 5f470948570526e9186f053a3003da7719604e90
+Author: stefano babic <sbabic@denx.de>
+Date: Tue Aug 21 15:50:33 2007 +0200
+
+ Fix MAC address setting in DM9000 driver.
+
+ The logic to check if there is a correct MAC address in the DM9000
+ EEPROM, added in the last patch, is wrong. Now the MAC address is
+ always taken from the environment, even if a suitable MAC is present
+ in the EEPROM.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 4a8527ef086ec7c89f40674ef024ae6f988a614a
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Tue Aug 21 12:40:34 2007 +0200
+
+ MPC5xxx: fix some compiler warnings in USB code
+
+ Fix the following warnings:
+ - usb.c:xx: warning: function declaration isn't a prototype
+ - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer
+ from pointer wihtout a cast
+
+ Signed-off-by: Martin Krause <martin.krase@tqs.de>
+
+commit 16e23c3f5dab6937f5109365416808c7f15c122b
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Mon Aug 20 23:55:33 2007 -0500
+
+ fsl_pci_init - Remove self PCSRBAR allocation
+
+ CPU physical address space was being wasted by allocating a
+ PCSRBAR PCI inbound region to it's memory space.
+
+ As a rule, PCSRBAR should be left alone since it does not affect
+ transactions from self and other masters may have changed it.
+
+ Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
+
+commit 0e700ce03a23bb1921149bc77008ace7103d5289
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Aug 20 13:56:47 2007 +0200
+
+ Fix compiler warning in include/s3c2410.h
+
+ This patch fixes the "type qualifiers ignored on fuction return tpye"
+ warning for include/s3c2410.h
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 9bb8b209ed2058a5756ecbeb544c067e44a42aea
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Mon Aug 20 07:09:05 2007 +0200
+
+ Fix compilation error for omap2420h4_config.
+
+ omap2420h4 switched to cfi, so remove old (already disabled) flash.c
+ and flash_probe() calls in env_flash.c.
+
+ Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+commit 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Fri Aug 10 14:34:14 2007 -0500
+
+ fdt: remove unused OF_FLAT_TREE_MAX_SIZE references
+
+ and make some minor corrections to the FDT part of the README.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Aug 29 01:32:05 2007 +0200
+
+ Minor coding style cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a861558c65f65f1cf1302f3a35e9db7686b9e1a3
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date: Tue Aug 28 17:40:33 2007 +0200
+
+ [UC101] Fix: if no CF in the board, U-Boot resets sometimes.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit f98984cb194bb34dbe1db9429d3b51133af30d07
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date: Tue Aug 28 17:39:14 2007 +0200
+
+ IDE: - make ide_inb () and ide_outb () "weak", so boards can
+ define there own I/O functions.
+ (Needed for the pcs440ep board).
+ - The default I/O Functions are again 8 Bit accesses.
+ - Added CONFIG_CMD_IDE for the pcs440ep Board.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 2c05fd125744981e5f2828d24e66ccc20a77d25d
+Author: Semih Hazar <semih.hazar@indefia.com>
+Date: Mon Aug 20 19:00:01 2007 +0300
+
+ AVR32: Change prototype of memset
+
+ Signed-off-by: Semih Hazar <semih.hazar@indefia.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 9c02defc29b57945b600714cf61ddfd02b02fb14
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date: Sat Aug 25 05:07:16 2007 +0200
+
+ POST: limit memory test area to not touch global data anymore
+
+ As experienced on lwmon5, on some boards the POST memory test can
+ corrupt the global data buffer (bd). This patch fixes this issue
+ by checking and limiting this area.
+
+ Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 75e1a84d483e36be10e206e539b028c4889e1158
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Aug 24 15:41:42 2007 +0200
+
+ ppc4xx: Add RTC POST test to lwmon5 board configuration
+
+ Since this RTC POST test is taking quite a while to complete
+ it's only initiated upon special keypress same as the complete
+ memory POST.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d7bfa620037a6d2210159387571bdf93aa32c162
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Aug 24 15:19:10 2007 +0200
+
+ ppc4xx: Change GPIO signal for watchdog triggering on lwmon5
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c25dd8fc25e9ca3695db996a257d9ba4dab414db
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 23 11:02:37 2007 +0200
+
+ ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board
+
+ This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
+ board. Now the "eeprom" command can be used to read/write from/to this
+ device. Additionally a new command was added "eepromwp" to en-/disable
+ the write-protect of this 2nd EEPROM.
+
+ The 1st EEPROM is not affected by this write-protect command.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c64fb30e4c5976007d56fc1789c7a0666082b536
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Aug 22 08:56:09 2007 +0200
+
+ ppc4xx: Remove unused option CFG_INIT_RAM_OCM
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3ad63878737a5a2b1e60825bf0a7d601d7a695e7
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 21 16:27:57 2007 +0200
+
+ ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)
+
+ This patch adds support for the matrix keyboard on the lwmon5 board.
+ Since the implementation in the dsPCI is kind of compatible with the
+ "old" lwmon board, most of the code is copied from the lwmon
+ board directory.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3e66c078003607a7d1d214c15a5f262bc1b4032f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Aug 19 10:27:34 2007 +0200
+
+ Fix some build errors.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 05675735ef77dc23b5e0eb782bad1ff477b55e86
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Aug 18 22:00:38 2007 +0200
+
+ Update CHANGELOG.
+
commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Thu Aug 16 22:52:39 2007 -0500
@@ -440,6 +1736,18 @@ Date: Fri Jun 22 17:32:28 2007 +0200
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 78cff50edba6b1508eb15c2f53ce966ac891eb9e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Thu Aug 16 10:46:28 2007 +0200
+
+ [FIX] Changes for bios_emulator code for others architecture
+
+commit 6e0e2253f039344f8ebd2787285fdba90e6714e8
+Author: Michal Simek <monstr@monstr.eu>
+Date: Thu Aug 16 10:45:09 2007 +0200
+
+ [FIX] Remove unused include file
+
commit 9de469bd960cc1870bb40d6672ed42726b8b50d7
Author: Stefan Roese <sr@denx.de>
Date: Thu Aug 16 10:18:33 2007 +0200
@@ -535,6 +1843,25 @@ Date: Wed Aug 15 22:30:05 2007 -0500
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+commit 5b4de9309d7a03aa1db2e5391ab696363391f460
+Author: Michal Simek <monstr@monstr.eu>
+Date: Wed Aug 15 21:15:05 2007 +0200
+
+ [FIX] Resolve problem with warnings
+ microblaze toolchain don't support PRAGMA PACK.
+
+commit d1ed28cf36ab6b1d4c479809de7252bf53d2f2d4
+Author: Michal Simek <monstr@monstr.eu>
+Date: Wed Aug 15 21:05:07 2007 +0200
+
+ [FIX] Correction command setting for Microblaze boards
+
+commit 7aa63d8cd30ab20ac2fd1ab86e60471de8b1f1e5
+Author: Michal Simek <monstr@monstr.eu>
+Date: Wed Aug 15 21:03:41 2007 +0200
+
+ [FIX] Correction command definition
+
commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8
Author: Jon Loeliger <jdl@freescale.com>
Date: Wed Aug 15 11:55:35 2007 -0500
@@ -2015,6 +3342,24 @@ Date: Tue Aug 7 16:02:13 2007 +0200
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit 706714d97a0d08d59eda4de2268c39f504688329
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Aug 6 23:41:53 2007 +0200
+
+ [FIX] remove cute code
+
+commit f500d9fdeb576288656dac427052ad2c5ca0ad1a
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Aug 6 23:35:26 2007 +0200
+
+ [FIX] Fix romfs code
+
+commit ab4b956d3143f8f8174089053f5dfabbb04762b0
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Aug 6 23:31:49 2007 +0200
+
+ [FIX] Coding style cleanup - Wolfgang's suggestions
+
commit 6c33c78557ca6f8da68c01ce33e278695197d3f4
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Aug 6 23:21:05 2007 +0200
@@ -2139,6 +3484,32 @@ Date: Thu Aug 2 14:09:49 2007 -0500
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
+commit a274ca4f6d68830e7c916f897561cff8c4101c38
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 22:33:05 2007 +0200
+
+ [FIX] Coding style cleanup
+
+commit af8377d4eb3a0ac5a831830d5ce63fbf65fecb7f
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 16:13:31 2007 +0200
+
+ [FIX] Xilinx Uartlite driver
+ Because PPC405 can use UARTLITE serial interface and
+ Microblaze can use Uart16550 serial interface not only Uartlite.
+
+commit 98889edd50aadf862071eb5664747ad0d568a20e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 15:54:53 2007 +0200
+
+ [FIX] Change configuration for XUPV2P Microblaze board
+
+commit 537091b4eed9302865d03fef3f7212b4fe5cf28f
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 15:53:50 2007 +0200
+
+ [PATCH] Added support for Xilinx Emac community driver
+
commit 86b116b1b1e165ca4840daefed36d2e3b8460173
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Fri Aug 3 12:08:16 2007 +0200
@@ -2439,6 +3810,12 @@ Date: Mon Jul 16 08:53:51 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 0c0a9cda1bde37106520476ed486bd67eb8d30ae
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Jul 16 00:31:07 2007 +0200
+
+ [PATCH] Support for Xilinx EmacLite controller
+
commit 3a6cab844cf74f76639d795e0be8717e02c86af7
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Jul 14 22:51:02 2007 +0200
@@ -2447,12 +3824,42 @@ Date: Sat Jul 14 22:51:02 2007 +0200
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit 5280f352c8da33b1d7fbf448768717d9e16ff9a1
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Jul 14 13:11:28 2007 +0200
+
+ [FIX] support for simply measuring time
+
+commit 91bb4ca665d2e0cf7f60c4b5b370990250ec0c43
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Jul 14 12:41:23 2007 +0200
+
+ [FS] Added support for ROMFS
+
commit 011595307731a7a67a7445d107c279d031e8ab97
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sat Jul 14 01:06:58 2007 +0200
[PCS440EP] - fix compile error, if BUILD_DIR is used
+commit 5a2f1098d81ad58b309e5e558d0492643166a799
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Jul 14 00:18:48 2007 +0200
+
+ [PATCH] Support time without timer
+
+commit a476ca2ac2217ddd05a2bf0c514075814b10a3c0
+Author: Michal Simek <monstr@monstr.eu>
+Date: Fri Jul 13 21:43:55 2007 +0200
+
+ [PATCH] Remove problem with disabled BARREL SHIFTER
+
+commit 55e26ad62107d2f14f757de3ae0b14b9aa7aed94
+Author: Michal Simek <monstr@monstr.eu>
+Date: Fri Jul 13 21:41:44 2007 +0200
+
+ [FIX] correct help for rspr
+
commit fad63407154f46246ce80d53a9c669a44362ac67
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jul 13 09:54:17 2007 +0200
@@ -4637,6 +6044,18 @@ Date: Mon Jun 18 13:50:13 2007 -0500
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+commit 093172f08d6afb3f34d8a2f26ee0ee874261cf27
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Jun 17 19:04:11 2007 +0200
+
+ [fix] email reparation
+
+commit 3666afffe7baf859c6ae0ce2bebbc8ab7e512ddc
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Jun 17 19:03:21 2007 +0200
+
+ [FIX] fix microblaze file permitission
+
commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 15 11:33:41 2007 +0200
diff --git a/MAKEALL b/MAKEALL
index 68bb1ad..20e8137 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -301,10 +301,12 @@ LIST_83xx=" \
MPC8313ERDB_66 \
MPC8323ERDB \
MPC832XEMDS \
+ MPC832XEMDS_ATM \
MPC8349EMDS \
MPC8349ITX \
MPC8349ITXGP \
MPC8360EMDS \
+ MPC8360EMDS_ATM \
sbc8349 \
TQM834x \
"
@@ -341,7 +343,7 @@ LIST_85xx=" \
LIST_86xx=" \
MPC8641HPCN \
- SBC8641D \
+ sbc8641d \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 0477cd3..ce7b07f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -22,9 +22,9 @@
#
VERSION = 1
-PATCHLEVEL = 2
+PATCHLEVEL = 3
SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc3
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
@@ -211,6 +211,7 @@ LIBS += drivers/libdrivers.a
LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/onenand/libonenand.a
LIBS += drivers/net/libnet.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
@@ -319,7 +320,7 @@ updater:
env:
$(MAKE) -C tools/env all || exit 1
-depend dep:
+depend dep: version
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
tags ctags:
@@ -1765,7 +1766,8 @@ MPC8323ERDB_config: unconfig
MPC832XEMDS_config \
MPC832XEMDS_HOST_33_config \
MPC832XEMDS_HOST_66_config \
-MPC832XEMDS_SLAVE_config: unconfig
+MPC832XEMDS_SLAVE_config \
+MPC832XEMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
@@ -1780,11 +1782,18 @@ MPC832XEMDS_SLAVE_config: unconfig
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
- fi ;
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _ATM_,$@)" ] ; then \
+ echo -n "...ATM..." ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
+ fi ;
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
MPC8349EMDS_config: unconfig
@@ -1794,20 +1803,21 @@ MPC8349ITX_config \
MPC8349ITX_LOWBOOT_config \
MPC8349ITXGP_config: unconfig
@mkdir -p $(obj)include
- @mkdir -p $(obj)board/mpc8349itx
+ @mkdir -p $(obj)board/freescale/mpc8349itx
@echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
@if [ "$(findstring GP,$@)" ] ; then \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+ echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
@if [ "$(findstring LOWBOOT,$@)" ] ; then \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+ echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
MPC8360EMDS_HOST_66_config \
-MPC8360EMDS_SLAVE_config: unconfig
+MPC8360EMDS_SLAVE_config \
+MPC8360EMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
@@ -1822,10 +1832,17 @@ MPC8360EMDS_SLAVE_config: unconfig
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _ATM_,$@)" ] ; then \
+ echo -n "...ATM..." ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
@@ -1961,7 +1978,7 @@ TQM8560_config: unconfig
echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
- echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h
+ echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
#########################################################################
@@ -2334,6 +2351,9 @@ scpu_config: unconfig
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
+trizepsiv_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
+
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250
diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds
index 038d849..34ceb0f 100644
--- a/board/ads5121/u-boot.lds
+++ b/board/ads5121/u-boot.lds
@@ -51,7 +51,6 @@ SECTIONS
{
cpu/mpc512x/start.o (.text)
*(.text)
- *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index 5202ae6..e3f3da6 100644
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -67,9 +67,9 @@ tlbtabA:
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -109,9 +109,9 @@ tlbtabB:
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index b804d55..a49066f 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -34,6 +34,8 @@
#undef PCIE_ENDPOINT
/* #define PCIE_ENDPOINT 1 */
+DECLARE_GLOBAL_DATA_PTR;
+
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
@@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
@@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
+ char *env;
+ unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
- bus = 1;
+ bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for katmai card presence */
if (!katmai_pcie_card_present(i))
@@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
hose = &pcie_hose[i];
hose->first_busno = bus;
- hose->last_busno = bus;
- bus++;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
@@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
+
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul (env, NULL, 10);
+ if (delay > 5)
+ printf ("Warning, expect noticable delay before PCIe"
+ "scan due to 'pciscandelay' value!\n");
+ mdelay (delay * 1000);
+ }
+
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
#endif
}
}
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 7b16f8a..0067ce0 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
************************************************************************/
int board_early_init_f(void)
{
- volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
@@ -66,8 +64,6 @@ int board_early_init_f(void)
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
- x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
-
return 0;
}
@@ -79,7 +75,18 @@ int board_early_init_f(void)
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
- x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+ /* set modes of operation */
+ x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+ EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+ /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+ x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+ /* put Ethernet+PHY in reset */
+ x->ethuart &= ~EPLD2_RESET_ETH_N;
+ udelay(10000);
+ /* take Ethernet+PHY out of reset */
+ x->ethuart |= EPLD2_RESET_ETH_N;
return 0;
}
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
index f3803c0..6b9043a 100644
--- a/board/amcc/sequoia/cmd_sequoia.c
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <command.h>
#include <i2c.h>
+#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
@@ -39,7 +40,7 @@
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
- * the only value affected for a 66MHz PCI and simply needs a +0x10.
+ * the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
@@ -56,6 +57,7 @@ static char *config_labels[] = {
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
@@ -97,6 +99,11 @@ static u8 boot_configs[][17] = {
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
+ (NOR_COMPATIBLE),
+ 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
@@ -200,8 +207,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/* check CPLD register +5 for PCI 66MHz flag */
- if (in8(CFG_BCSR_BASE + 5) & 0x01)
- buf[5] += 0x10;
+ if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
+ /*
+ * PLB-to-PCI divisor = 3 for 33MHz sync PCI
+ * instead of 2 for 66MHz systems
+ */
+ buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 45bcd4b..5fe3af9 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -126,6 +126,9 @@ tlbtab:
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ /* TLB-entry PCI IO Space - from sr@denx.de */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index f823117..4e47ab3 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@@ -24,6 +24,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -362,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
- rev = in8(CFG_BCSR_BASE + 0);
- val = in8(CFG_BCSR_BASE + 5) & 0x01;
+ rev = in_8((void *)(CFG_BCSR_BASE + 0));
+ val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index bc976c7..f00397e 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -32,6 +32,8 @@
void show_reset_reg(void);
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int lcd_init(void);
int board_early_init_f (void)
@@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 912f09e..6ec922a 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -1,4 +1,6 @@
/*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,6 +24,7 @@
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -181,8 +184,8 @@ int checkboard(void)
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif
- rev = *(u8 *)(CFG_CPLD + 0);
- val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ rev = in_8((void *)(CFG_BCSR_BASE + 0));
+ val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index c92dcf7..67e8f8f 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -70,9 +70,9 @@ tlbtabA:
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -112,9 +112,9 @@ tlbtabB:
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index d08fcf3..d7cc384 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -34,6 +34,8 @@
#include "yucca.h"
#include "../cpu/ppc4xx/440spe_pcie.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#undef PCIE_ENDPOINT
/* #define PCIE_ENDPOINT 1 */
@@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
@@ -846,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
+ char *env;
+ unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
- bus = 1;
+ bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
@@ -874,8 +876,8 @@ void pcie_setup_hoses(void)
hose = &pcie_hose[i];
hose->first_busno = bus;
- hose->last_busno = bus;
- bus++;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
@@ -895,10 +897,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
+
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul (env, NULL, 10);
+ if (delay > 5)
+ printf ("Warning, expect noticable delay before PCIe"
+ "scan due to 'pciscandelay' value!\n");
+ mdelay (delay * 1000);
+ }
+
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
#endif
}
}
diff --git a/board/at91rm9200dk/led.c b/board/at91rm9200dk/led.c
index 0518918..47a3bfc 100644
--- a/board/at91rm9200dk/led.c
+++ b/board/at91rm9200dk/led.c
@@ -66,7 +66,7 @@ void red_LED_off(void)
}
-void LED_init (void)
+void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;
diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c
index 958f4dc..93d790f 100644
--- a/board/atmel/atstk1000/flash.c
+++ b/board/atmel/atstk1000/flash.c
@@ -55,10 +55,6 @@ unsigned long flash_init(void)
unsigned long addr;
unsigned int i;
- gd->bd->bi_flashstart = CFG_FLASH_BASE;
- gd->bd->bi_flashsize = CFG_FLASH_SIZE;
- gd->bd->bi_flashoffset = _edata - _text;
-
flash_info[0].size = CFG_FLASH_SIZE;
flash_info[0].sector_count = 135;
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
index 1dd4a3f..98ed6f8 100644
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ b/board/bf533-ezkit/bf533-ezkit.c
@@ -30,6 +30,8 @@
#include "psd4256.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF531)
@@ -46,7 +48,6 @@ int checkboard(void)
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index b9dff99..69e425b 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -30,6 +30,8 @@
#include <asm/io.h>
#include "bf533-stamp.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define STATUS_LED_OFF 0
#define STATUS_LED_ON 1
@@ -55,7 +57,6 @@ int checkboard(void)
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
printf("SDRAM attributes:\n");
printf
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
index 919cef6..b3d8bda 100644
--- a/board/bf537-stamp/bf537-stamp.c
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -32,6 +32,8 @@
#include <asm/io.h>
#include "ether_bf537.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define POST_WORD_ADDR 0xFF903FFC
/*
@@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
index 989b019..2ff44a7 100644
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -29,6 +29,8 @@
#include <common.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
printf("CPU: ADSP BF561\n");
@@ -39,7 +41,6 @@ int checkboard(void)
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index b74ac08..e2ab5b8 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -397,6 +397,7 @@ int misc_init_r(void)
"operational\n");
/* set the hostname appropriate to the module we're running on */
+ hostname[0] = 0x00;
compose_hostname(hw_id, hostname);
setenv("hostname", hostname);
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
index 513c365..354f2bf 100644
--- a/board/cm5200/cmd_cm5200.c
+++ b/board/cm5200/cmd_cm5200.c
@@ -27,7 +27,7 @@
#include <i2c.h>
#include <usb.h>
-#ifdef CONFIG_CMD_BSB
+#ifdef CONFIG_CMD_BSP
int do_i2c(char *argv[])
{
diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c
index 604edb5..dce821b 100644
--- a/board/davinci/dv-evm/dv_board.c
+++ b/board/davinci/dv-evm/dv_board.c
@@ -31,6 +31,8 @@
#define MACH_TYPE_DAVINCI_EVM 901
+DECLARE_GLOBAL_DATA_PTR;
+
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
@@ -115,8 +117,6 @@ void dsp_on(void)
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
@@ -202,8 +202,6 @@ int misc_init_r (void)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c
index 9f271a1..0a07523 100644
--- a/board/davinci/schmoogie/dv_board.c
+++ b/board/davinci/schmoogie/dv_board.c
@@ -31,6 +31,8 @@
#define MACH_TYPE_SCHMOOGIE 1255
+DECLARE_GLOBAL_DATA_PTR;
+
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
@@ -115,8 +117,6 @@ void dsp_on(void)
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
@@ -244,8 +244,6 @@ int misc_init_r (void)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c
index 99857c4..cd2dac6 100644
--- a/board/davinci/sonata/dv_board.c
+++ b/board/davinci/sonata/dv_board.c
@@ -31,6 +31,8 @@
#define MACH_TYPE_SONATA 1254
+DECLARE_GLOBAL_DATA_PTR;
+
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
@@ -115,8 +117,6 @@ void dsp_on(void)
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SONATA;
@@ -199,8 +199,6 @@ int misc_init_r (void)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
diff --git a/board/fads/fads.h b/board/fads/fads.h
index a7fe2e9..dea8a0d 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -229,6 +229,7 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CFG_DIRECT_FLASH_TFTP
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index ae4bef1..fd99a93 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -25,10 +25,9 @@
#include <common.h>
#include <command.h>
#include <watchdog.h>
-#include <asm/cache.h>
#ifdef CONFIG_FSL_PIXIS
-
+#include <asm/cache.h>
#include "pixis.h"
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index d79f2eb..e4f96e8 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -79,19 +79,19 @@ int pib_init(void)
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
- val = 0;
- i2c_write(0x26, 0x7, 1, &val, 1);
- val = 0xf7;
- i2c_write(0x26, 0x3, 1, &val, 1);
-
- val = 0;
- i2c_write(0x21, 0x6, 1, &val, 1);
- i2c_write(0x21, 0x7, 1, &val, 1);
-
- val = 0xdf;
- i2c_write(0x21, 0x2, 1, &val, 1);
- val = 0xef;
- i2c_write(0x21, 0x3, 1, &val, 1);
+ val8 = 0;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf7;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x21, 0x6, 1, &val8, 1);
+ i2c_write(0x21, 0x7, 1, &val8, 1);
+
+ val8 = 0xdf;
+ i2c_write(0x21, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x21, 0x3, 1, &val8, 1);
eieio();
diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c
index 58fabdf..1fd4d99 100644
--- a/board/freescale/m5235evb/mii.c
+++ b/board/freescale/m5235evb/mii.c
@@ -204,7 +204,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c
index 31f1510..8f6abf3 100644
--- a/board/freescale/m5329evb/mii.c
+++ b/board/freescale/m5329evb/mii.c
@@ -203,7 +203,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c
index c067183..7a59aa0 100644
--- a/board/freescale/m54455evb/mii.c
+++ b/board/freescale/m54455evb/mii.c
@@ -221,7 +221,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index e6e8410..16ec4bb 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -33,10 +33,11 @@
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CFG_8313ERDB_BROKEN_PMC
static void resume_from_sleep(void)
{
- DECLARE_GLOBAL_DATA_PTR;
u32 magic = *(u32 *)0;
typedef void (*func_t)(void);
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index c027f6f..07ba245 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -28,10 +28,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
@@ -386,7 +383,7 @@ void ide_set_reset (int idereset)
}
#endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index b227487..efdc333 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -28,11 +28,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
+#include <libfdt.h>
#define SDRAM_DDR 0
#if 1
@@ -308,7 +304,7 @@ void ide_set_reset (int idereset)
}
#endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c
index d212c63..9c2d1af 100644
--- a/board/lpc2292sodimm/lpc2292sodimm.c
+++ b/board/lpc2292sodimm/lpc2292sodimm.c
@@ -28,8 +28,7 @@
#include <common.h>
#include <clps7111.h>
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
@@ -37,8 +36,6 @@
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* Activate LED flasher */
IO_LEDFLSH = 0x40;
@@ -53,8 +50,6 @@ int board_init (void)
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c
index f6c63c3..3830ce7 100644
--- a/board/m5271evb/mii.c
+++ b/board/m5271evb/mii.c
@@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c
index fadcbb3..0ecc44a 100644
--- a/board/m5272c3/mii.c
+++ b/board/m5272c3/mii.c
@@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c
index ebd3ed9..d7c6d1f 100644
--- a/board/m5282evb/mii.c
+++ b/board/m5282evb/mii.c
@@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 6eb5fe9..f83998e 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -29,9 +29,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <miiphy.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
#if defined(CONFIG_STATUS_LED)
#include <status_led.h>
@@ -196,12 +194,12 @@ int checkboard(void)
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_STATUS_LED)
diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c
index 63c99de..81846eb 100644
--- a/board/mpc7448hpc2/mpc7448hpc2.c
+++ b/board/mpc7448hpc2/mpc7448hpc2.c
@@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd);
#undef DEBUG
+DECLARE_GLOBAL_DATA_PTR;
+
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
@@ -46,8 +48,6 @@ int display_mem_map (void);
void after_reloc (ulong dest_addr)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*
* Jump to the main U-Boot board init code
*/
diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c
index 8a7efef..30ae17d 100644
--- a/board/mpc7448hpc2/tsi108_init.c
+++ b/board/mpc7448hpc2/tsi108_init.c
@@ -33,6 +33,8 @@
#include <asm/processor.h>
#include <tsi108.h>
+DECLARE_GLOBAL_DATA_PTR;
+
extern void mpicInit (int verbose);
/*
@@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void)
int board_early_init_f (void)
{
- DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
@@ -583,7 +584,6 @@ unsigned long get_l2cr (void)
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
index 44b4112..227c492 100644
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data)
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern void print_vcma9_info(void);
extern int vcma9_cantest(int);
extern int vcma9_nandtest(void);
@@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (strcmp(argv[1], "info") == 0)
{
print_vcma9_info();
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index 45ab654..a4c463a 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -288,7 +288,7 @@ int dram_init(void)
int checkboard(void)
{
- unsigned char s[50];
+ char s[50];
int i;
backup_t *b = (backup_t *) s;
@@ -337,7 +337,7 @@ int overwrite_console(void)
************************************************************************/
void print_vcma9_info(void)
{
- unsigned char s[50];
+ char s[50];
int i;
if ((i = getenv_r("serial#", s, 32)) < 0) {
diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c
index b4865e1..6c894a3 100644
--- a/board/sbc2410x/sbc2410x.c
+++ b/board/sbc2410x/sbc2410x.c
@@ -35,7 +35,7 @@
#include <linux/mtd/nand.h>
#endif
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
#define FCLK_SPEED 1
@@ -74,7 +74,6 @@ static inline void delay (unsigned long loops)
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
@@ -128,8 +127,6 @@ int board_init (void)
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
diff --git a/board/siemens/SMN42/smn42.c b/board/siemens/SMN42/smn42.c
index cbfc76c..52d1d7e 100644
--- a/board/siemens/SMN42/smn42.c
+++ b/board/siemens/SMN42/smn42.c
@@ -31,8 +31,7 @@
#include <common.h>
#include <clps7111.h>
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
@@ -40,8 +39,6 @@
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number MACH_TYPE_ARMADILLO - not official*/
gd->bd->bi_arch_number = 83;
@@ -53,8 +50,6 @@ int board_init (void)
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 5882124..9bacb98 100644
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -378,9 +378,14 @@ static struct pci_config_table pci_stxgp3_config_table[] = {
#endif
-static struct pci_controller hose = {
+static struct pci_controller hose[] = {
#ifndef CONFIG_PCI_PNP
- config_table: pci_stxgp3_config_table,
+ { config_table: pci_stxgp3_config_table,},
+#else
+ {},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
#endif
};
@@ -393,6 +398,6 @@ pci_init_board(void)
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif /* CONFIG_PCI */
}
diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds
index 95ecf66..65e1bcf 100644
--- a/board/stxssa/u-boot.lds
+++ b/board/stxssa/u-boot.lds
@@ -145,6 +145,7 @@ SECTIONS
. = ALIGN(256);
__init_end = .;
+ . = .;
__bss_start = .;
.bss :
{
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
index 51f4aeb..29d6f00 100644
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@@ -31,10 +31,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
@@ -46,6 +43,8 @@
#include "mt48lc16m16a2-75.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
@@ -480,8 +479,6 @@ int silent_boot (void)
int board_early_init_f (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (silent_boot())
gd->flags |= GD_FLG_SILENT;
@@ -780,9 +777,9 @@ int board_get_height (void)
#endif /* CONFIG_VIDEO_SM501 */
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
new file mode 100644
index 0000000..115e17d
--- /dev/null
+++ b/board/trizepsiv/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := conxs.o eeprom.o
+SOBJS := lowlevel_init.o pxavoltage.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk
new file mode 100644
index 0000000..4486f6b
--- /dev/null
+++ b/board/trizepsiv/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE =0xa1f00000
+# 0xa1700000
+#TEXT_BASE = 0
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
new file mode 100644
index 0000000..7c6c855
--- /dev/null
+++ b/board/trizepsiv/conxs.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void usb_board_init(void)
+{
+ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+ UHCHR |= UHCHR_FSBIR;
+
+ while (UHCHR & UHCHR_FSBIR);
+
+ UHCHR &= ~UHCHR_SSE;
+ UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+ /* Clear any OTG Pin Hold */
+ if (PSSR & PSSR_OTGPH)
+ PSSR |= PSSR_OTGPH;
+
+ UHCRHDA &= ~(RH_A_NPS);
+ UHCRHDA |= RH_A_PSM;
+
+ /* Set port power control mask bits, only 3 ports. */
+ UHCRHDB |= (0x7<<17);
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+ CKEN &= ~CKEN10_USBHOST;
+
+ puts("Called USB STOP\n");
+ return;
+}
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of ConXS Board */
+ gd->bd->bi_arch_number = 776;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa000003c;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ char *console=getenv("boot_console");
+
+ if ((strcmp(console,"serial_btuart") == 0) ||
+ (strcmp(console,"serial_stuart") == 0) ||
+ (strcmp(console,"serial_ffuart") == 0)) {
+ setenv("stdout",console);
+ setenv("stdin", console);
+ setenv("stderr",console);
+ } else {
+ setenv("stdout", "serial");
+ setenv("stdin", "serial");
+ setenv("stderr", "serial");
+ }
+#endif
+ return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c
new file mode 100644
index 0000000..3d3bc00
--- /dev/null
+++ b/board/trizepsiv/eeprom.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+static unsigned char srom[128];
+extern u16 read_srom_word(int);
+extern void write_srom_word(int offset, u16 val);
+
+static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+ int i;
+
+ for (i=0; i < 0x40; i++) {
+ if (!(i % 0x10))
+ printf("\n%08lx:", i);
+ printf(" %04x", read_srom_word(i));
+ }
+ printf ("\n");
+ return (0);
+}
+
+static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+ int offset,value;
+
+ if (argc < 4) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ offset=simple_strtoul(argv[2],NULL,16);
+ value=simple_strtoul(argv[3],NULL,16);
+ if (offset > 0x40) {
+ printf("Wrong offset : 0x%x\n",offset);
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+ write_srom_word(offset, value);
+ return (0);
+}
+
+int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (strcmp (argv[1],"read") == 0) {
+ return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
+ } else if (strcmp (argv[1],"write") == 0) {
+ return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
+ } else {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+}
+
+U_BOOT_CMD(
+ dm9000ee,4,1,do_dm9000_eeprom,
+ "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
+ "\ndm9000ee write <word offset> <value> \n"
+ "\tdm9000ee read \n"
+ "\tword:\t\t00-02 : MAC Address\n"
+ "\t\t\t03-07 : DM9000 Configuration\n"
+ "\t\t\t08-63 : User data\n");
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S
new file mode 100644
index 0000000..d886938
--- /dev/null
+++ b/board/trizepsiv/lowlevel_init.S
@@ -0,0 +1,503 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR3
+ ldr r1, =CFG_GPSR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR3
+ ldr r1, =CFG_GPCR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER0
+ ldr r1, =CFG_GRER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER1
+ ldr r1, =CFG_GRER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER2
+ ldr r1, =CFG_GRER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER3
+ ldr r1, =CFG_GRER3_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER0
+ ldr r1, =CFG_GFER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER1
+ ldr r1, =CFG_GFER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER2
+ ldr r1, =CFG_GFER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER3
+ ldr r1, =CFG_GFER3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR3
+ ldr r1, =CFG_GPDR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_L
+ ldr r1, =CFG_GAFR3_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_U
+ ldr r1, =CFG_GAFR3_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+ ldr r2, =CFG_FLYCNFG_VAL
+ str r2, [r1, #FLYCNFG_OFFSET]
+ str r2, [r1, #FLYCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r2, =0xFFF
+ bic r4, r4, r2
+
+ ldr r3, =CFG_MDREFR_VAL
+ and r3, r3, r2
+
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+
+ orr r4, r4, #MDREFR_K0RUN
+ orr r4, r4, #MDREFR_K0DB4
+ orr r4, r4, #MDREFR_K0FREE
+ orr r4, r4, #MDREFR_K0DB2
+ orr r4, r4, #MDREFR_K1DB2
+ bic r4, r4, #MDREFR_K1FREE
+ bic r4, r4, #MDREFR_K2FREE
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ ldr r2, =CFG_SXCNFG_VAL
+ str r2, [r1, #SXCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+ orr r4, r4, #MDREFR_K1RUN
+ bic r4, r4, #MDREFR_K2DB2
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ bic r4, r4, #MDREFR_SLFRSH
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ orr r4, r4, #MDREFR_E1PIN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ nop
+ nop
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ mov r4, r3
+ orr r3, r3, #MDCNFG_DE0
+ str r3, [r1, #MDCNFG_OFFSET]
+ mov r0, r3
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ /* enable APD */
+ ldr r3, [r1, #MDREFR_OFFSET]
+ orr r3, r3, #MDREFR_APD
+ str r3, [r1, #MDREFR_OFFSET]
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+setvoltage:
+
+ mov r10, lr
+ bl initPXAvoltage /* In case the board is rebooting with a */
+ mov lr, r10 /* low voltage raise it up to a good one. */
+
+#if 1
+ b initirqs
+#endif
+
+wakeup:
+ /* Are we waking from sleep? */
+ ldr r0, =RCSR
+ ldr r1, [r0]
+ and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r1, [r0]
+ teq r1, #RCSR_SMR
+
+ bne initirqs
+
+ ldr r0, =PSSR
+ mov r1, #PSSR_PH
+ str r1, [r0]
+
+ /* if so, resume at PSPR */
+ ldr r0, =PSPR
+ ldr r1, [r0]
+ mov pc, r1
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off on-chip peripheral clocks (except for memory) */
+ /* for re-configuration. */
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN
+ str r2, [r1]
+
+ /* ... and write the core clock config register */
+ ldr r2, =CFG_CCCR
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* Turn on turbo mode */
+ mrc p14, 0, r2, c6, c0, 0
+ orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
+ mcr p14, 0, r2, c6, c0, 0
+
+ /* Re-write MDREFR */
+ ldr r1, =MEMC_BASE
+ ldr r2, [r1, #MDREFR_OFFSET]
+ str r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#else
+#error "RTC not defined"
+#endif
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+ /* FIXME */
+
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
diff --git a/include/led.h b/board/trizepsiv/pxavoltage.S
index 57c2b4a..9659c2b 100644
--- a/include/led.h
+++ b/board/trizepsiv/pxavoltage.S
@@ -1,7 +1,6 @@
/*
- * (C) Copyright 2006
- * Atmel Nordic AB <www.atmel.com>
- * Ulf Samuelsson <ulf@atmel.com>
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,24 +21,9 @@
* MA 02111-1307 USA
*/
-#ifndef __LED_H
-#define __LED_H
+#include <asm/arch/pxa-regs.h>
-#ifndef __ASSEMBLY__
-extern void LED_init (void);
-extern void red_LED_on(void);
-extern void red_LED_off(void);
-extern void green_LED_on(void);
-extern void green_LED_off(void);
-extern void yellow_LED_on(void);
-extern void yellow_LED_off(void);
-#else
- .extern LED_init
- .extern red_LED_on
- .extern red_LED_off
- .extern yellow_LED_on
- .extern yellow_LED_off
- .extern green_LED_on
- .extern green_LED_off
-#endif
-#endif
+ .global initPXAvoltage
+
+initPXAvoltage:
+ mov pc, lr
diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds
new file mode 100644
index 0000000..f010239
--- /dev/null
+++ b/board/trizepsiv/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/common/Makefile b/common/Makefile
index ef7d097..fde5ad9 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -37,13 +37,14 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
+ cmd_onenand.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
cmd_universe.o cmd_usb.o cmd_vfd.o \
command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
- env_nvram.o env_nowhere.o \
+ env_onenand.o env_nvram.o env_nowhere.o \
exports.o \
fdt_support.o flash.o fpga.o ft_build.o \
hush.o kgdb.o lcd.o lists.o lynxkdi.o \
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index bcb927f..6ebedfb 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -817,27 +817,34 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
int i;
/* skip kernel length, initrd length, and terminator */
- of_data = (ulong)(&len_ptr[3]);
+ of_flat_tree = (char *)(&len_ptr[3]);
/* skip any additional image length fields */
for (i=2; len_ptr[i]; ++i)
- of_data += 4;
+ of_flat_tree += 4;
/* add kernel length, and align */
- of_data += ntohl(len_ptr[0]);
+ of_flat_tree += ntohl(len_ptr[0]);
if (tail) {
- of_data += 4 - tail;
+ of_flat_tree += 4 - tail;
}
/* add initrd length, and align */
tail = ntohl(len_ptr[1]) % 4;
- of_data += ntohl(len_ptr[1]);
+ of_flat_tree += ntohl(len_ptr[1]);
if (tail) {
- of_data += 4 - tail;
+ of_flat_tree += 4 - tail;
}
+#ifndef CFG_NO_FLASH
+ /* move the blob if it is in flash (set of_data to !null) */
+ if (addr2info ((ulong)of_flat_tree) != NULL)
+ of_data = (ulong)of_flat_tree;
+#endif
+
+
#if defined(CONFIG_OF_FLAT_TREE)
- if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+ if (*((ulong *)(of_flat_tree)) != OF_DT_HEADER) {
#else
- if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
+ if (fdt_check_header (of_flat_tree) != 0) {
#endif
puts ("ERROR: image is not a fdt - "
"must RESET the board to recover.\n");
@@ -845,9 +852,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
}
#if defined(CONFIG_OF_FLAT_TREE)
- if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
+ if (((struct boot_param_header *)of_flat_tree)->totalsize !=
+ ntohl (len_ptr[2])) {
#else
- if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
+ if (be32_to_cpu (fdt_totalsize (of_flat_tree)) !=
+ ntohl(len_ptr[2])) {
#endif
puts ("ERROR: fdt size != image size - "
"must RESET the board to recover.\n");
@@ -957,34 +966,37 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
+ puts ("OK\n");
}
/*
* Add the chosen node if it doesn't exist, add the env and bd_t
* if the user wants it (the logic is in the subroutines).
*/
- if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
- puts ("ERROR: /chosen node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (of_flat_tree) {
+ if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
+ puts ("ERROR: /chosen node create failed - "
+ "must RESET the board to recover.\n");
+ do_reset (cmdtp, flag, argc, argv);
+ }
#ifdef CONFIG_OF_HAS_UBOOT_ENV
- if (fdt_env(of_flat_tree) < 0) {
- puts ("ERROR: /u-boot-env node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (fdt_env(of_flat_tree) < 0) {
+ puts ("ERROR: /u-boot-env node create failed - "
+ "must RESET the board to recover.\n");
+ do_reset (cmdtp, flag, argc, argv);
+ }
#endif
#ifdef CONFIG_OF_HAS_BD_T
- if (fdt_bd_t(of_flat_tree) < 0) {
- puts ("ERROR: /bd_t node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (fdt_bd_t(of_flat_tree) < 0) {
+ puts ("ERROR: /bd_t node create failed - "
+ "must RESET the board to recover.\n");
+ do_reset (cmdtp, flag, argc, argv);
+ }
#endif
#ifdef CONFIG_OF_BOARD_SETUP
- /* Call the board-specific fixup routine */
- ft_board_setup(of_flat_tree, gd->bd);
+ /* Call the board-specific fixup routine */
+ ft_board_setup(of_flat_tree, gd->bd);
#endif
+ }
#endif /* CONFIG_OF_LIBFDT */
#if defined(CONFIG_OF_FLAT_TREE)
#ifdef CFG_BOOTMAPSZ
@@ -1011,6 +1023,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
printf (" Loading Device Tree to %08lx, end %08lx ... ",
of_start, of_start + of_len - 1);
memmove ((void *)of_start, (void *)of_data, of_len);
+ puts ("OK\n");
}
/*
* Create the /chosen node and modify the blob with board specific
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 3fc4fca..cce23ad 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -60,6 +60,7 @@ static int fpga_get_op (char *opstr);
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
+#if (CONFIG_FPGA & CFG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
@@ -72,7 +73,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
dataptr = (unsigned char *)fpgadata;
-#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 8d4c1a3..9d1d875 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -355,19 +355,18 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
unsigned int reg = 0;
unsigned int val = 0;
- reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
- val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
- if (argc < 1) {
+ if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
+ reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+ val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
switch (reg) {
case 0x1:
if (argc > 2) {
MTS (val, rmsr);
NOP;
MFS (val, rmsr);
-
} else {
MFS (val, rmsr);
}
@@ -382,6 +381,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts ("ESR");
break;
default:
+ puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08lx\n", val);
@@ -408,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
" 3 - blocking control write\n");
U_BOOT_CMD (rspr, 3, 1, do_rspr,
- "rmsr - read/write special purpose register\n",
+ "rspr - read/write special purpose register\n",
"- reg_num [write value] read/write special purpose register\n"
- " 0 - MSR - Machine status register\n"
- " 1 - EAR - Exception address register\n"
- " 2 - ESR - Exception status register\n");
+ " 1 - MSR - Machine status register\n"
+ " 3 - EAR - Exception address register\n"
+ " 5 - ESR - Exception status register\n");
#endif
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 254a775..1fdd7a6 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -161,7 +161,11 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong addr, off, size;
char *cmd, *s;
nand_info_t *nand;
+#ifdef CFG_NAND_QUIET
+ int quiet = CFG_NAND_QUIET;
+#else
int quiet = 0;
+#endif
const char *quiet_str = getenv("quiet");
/* at least two arguments please */
@@ -452,7 +456,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand,
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2] - addr off|partition size\n"
- "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n"
+ "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 1db0fc3..6770408 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -57,8 +57,9 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CFG_ENV_IS_IN_FLASH) && \
!defined(CFG_ENV_IS_IN_DATAFLASH) && \
!defined(CFG_ENV_IS_IN_NAND) && \
+ !defined(CFG_ENV_IS_IN_ONENAND) && \
!defined(CFG_ENV_IS_NOWHERE)
-# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
+# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
#endif
#define XMK_STR(x) #x
@@ -553,7 +554,8 @@ int getenv_r (char *name, char *buf, unsigned len)
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
- || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
extern char * env_name_spec;
@@ -608,7 +610,8 @@ U_BOOT_CMD(
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
- || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
U_BOOT_CMD(
saveenv, 1, 0, do_saveenv,
"saveenv - save environment variables to persistent storage\n",
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
new file mode 100644
index 0000000..dcda099
--- /dev/null
+++ b/common/cmd_onenand.c
@@ -0,0 +1,155 @@
+/*
+ * U-Boot command for OneNAND support
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int ret = 0;
+
+ switch (argc) {
+ case 0:
+ case 1:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+
+ case 2:
+ if (strncmp(argv[1], "open", 4) == 0) {
+ onenand_init();
+ return 0;
+ }
+ onenand_print_device_info(onenand_chip.device_id, 1);
+ return 0;
+
+ default:
+ /* At least 4 args */
+ if (strncmp(argv[1], "erase", 5) == 0) {
+ struct erase_info instr;
+ ulong start, end;
+ ulong block;
+
+ start = simple_strtoul(argv[2], NULL, 10);
+ end = simple_strtoul(argv[3], NULL, 10);
+ start -= (unsigned long)onenand_chip.base;
+ end -= (unsigned long)onenand_chip.base;
+
+ if (!end || end < 0)
+ end = start;
+
+ printf("Erase block from %d to %d\n", start, end);
+
+ for (block = start; block <= end; block++) {
+ instr.addr = block << onenand_chip.erase_shift;
+ instr.len = 1 << onenand_chip.erase_shift;
+ ret = onenand_erase(&onenand_mtd, &instr);
+ if (ret) {
+ printf("erase failed %d\n", block);
+ break;
+ }
+ }
+
+ return 0;
+ }
+
+ if (strncmp(argv[1], "read", 4) == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong ofs = simple_strtoul(argv[3], NULL, 16);
+ size_t len = simple_strtoul(argv[4], NULL, 16);
+ size_t retlen = 0;
+ int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
+
+ ofs -= (unsigned long)onenand_chip.base;
+
+ if (oob)
+ onenand_read_oob(&onenand_mtd, ofs, len,
+ &retlen, (u_char *) addr);
+ else
+ onenand_read(&onenand_mtd, ofs, len, &retlen,
+ (u_char *) addr);
+ printf("Done\n");
+
+ return 0;
+ }
+
+ if (strncmp(argv[1], "write", 5) == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong ofs = simple_strtoul(argv[3], NULL, 16);
+ size_t len = simple_strtoul(argv[4], NULL, 16);
+ size_t retlen = 0;
+
+ ofs -= (unsigned long)onenand_chip.base;
+
+ onenand_write(&onenand_mtd, ofs, len, &retlen,
+ (u_char *) addr);
+ printf("Done\n");
+
+ return 0;
+ }
+
+ if (strncmp(argv[1], "block", 5) == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong block = simple_strtoul(argv[3], NULL, 10);
+ ulong page = simple_strtoul(argv[4], NULL, 10);
+ size_t len = simple_strtol(argv[5], NULL, 10);
+ size_t retlen = 0;
+ ulong ofs;
+ int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1;
+
+ ofs = block << onenand_chip.erase_shift;
+ if (page)
+ ofs += page << onenand_chip.page_shift;
+
+ if (!len) {
+ if (oob)
+ len = 64;
+ else
+ len = 512;
+ }
+
+ if (oob)
+ onenand_read_oob(&onenand_mtd, ofs, len,
+ &retlen, (u_char *) addr);
+ else
+ onenand_read(&onenand_mtd, ofs, len, &retlen,
+ (u_char *) addr);
+ return 0;
+ }
+
+ break;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ onenand, 6, 1, do_onenand,
+ "onenand - OneNAND sub-system\n",
+ "info - show available OneNAND devices\n"
+ "onenand read[.oob] addr ofs len - read data at ofs with len to addr\n"
+ "onenand write addr ofs len - write data at ofs with len from addr\n"
+ "onenand erase saddr eaddr - erase block start addr to end addr\n"
+ "onenand block[.oob] addr block [page] [len] - "
+ "read data with (block [, page]) to addr"
+);
+
+#endif /* CONFIG_CMD_ONENAND */
diff --git a/common/env_onenand.c b/common/env_onenand.c
new file mode 100644
index 0000000..66107f9
--- /dev/null
+++ b/common/env_onenand.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_IN_ONENAND) /* Environment is in OneNAND */
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+/* References to names in env_common.c */
+extern uchar default_environment[];
+
+#define ONENAND_ENV_SIZE(mtd) (mtd.oobblock - ENV_HEADER_SIZE)
+
+char *env_name_spec = "OneNAND";
+
+#ifdef ENV_IS_EMBEDDED
+extern uchar environment[];
+env_t *env_ptr = (env_t *) (&environment[0]);
+#else /* ! ENV_IS_EMBEDDED */
+static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
+env_t *env_ptr = (env_t *) onenand_env;
+#endif /* ENV_IS_EMBEDDED */
+
+uchar env_get_char_spec(int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return (*((uchar *) (gd->env_addr + index)));
+}
+
+void env_relocate_spec(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned long env_addr;
+ int use_default = 0;
+ int retlen;
+
+ env_addr = CFG_ENV_ADDR;
+ env_addr -= (unsigned long)onenand_chip.base;
+
+ /* Check OneNAND exist */
+ if (onenand_mtd.oobblock)
+ /* Ignore read fail */
+ onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock,
+ &retlen, (u_char *) env_ptr);
+ else
+ onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE;
+
+ if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
+ env_ptr->crc)
+ use_default = 1;
+
+ if (use_default) {
+ memcpy(env_ptr->data, default_environment,
+ ONENAND_ENV_SIZE(onenand_mtd));
+ env_ptr->crc =
+ crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
+ }
+
+ gd->env_addr = (ulong) & env_ptr->data;
+ gd->env_valid = 1;
+}
+
+int saveenv(void)
+{
+ unsigned long env_addr = CFG_ENV_ADDR;
+ struct erase_info instr;
+ int retlen;
+
+ instr.len = CFG_ENV_SIZE;
+ instr.addr = env_addr;
+ instr.addr -= (unsigned long)onenand_chip.base;
+ if (onenand_erase(&onenand_mtd, &instr)) {
+ printf("OneNAND: erase failed at 0x%08x\n", env_addr);
+ return 1;
+ }
+
+ /* update crc */
+ env_ptr->crc =
+ crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE);
+
+ env_addr -= (unsigned long)onenand_chip.base;
+ if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
+ (u_char *) env_ptr)) {
+ printf("OneNAND: write failed at 0x%08x\n", instr.addr);
+ return 2;
+ }
+
+ return 0;
+}
+
+int env_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* use default */
+ gd->env_addr = (ulong) & default_environment[0];
+ gd->env_valid = 1;
+
+ return 0;
+}
+
+#endif /* CFG_ENV_IS_IN_ONENAND */
diff --git a/common/environment.c b/common/environment.c
index 1d425a7..24257f7 100644
--- a/common/environment.c
+++ b/common/environment.c
@@ -51,18 +51,7 @@
* a seperate section. Note that ENV_CRC is only defined when building
* U-Boot itself.
*/
-#if (defined(CONFIG_CMI) || \
- defined(CONFIG_FADS) || \
- defined(CONFIG_HYMOD) || \
- defined(CONFIG_ICU862) || \
- defined(CONFIG_R360MPI) || \
- defined(CONFIG_TQM8xxL) || \
- defined(CONFIG_RRVISION) || \
- defined(CONFIG_TRAB) || \
- defined(CONFIG_PPCHAMELEONEVB) || \
- defined(CONFIG_M5271EVB) || \
- defined(CONFIG_IDMR) || \
- defined(CONFIG_NAND_U_BOOT)) && \
+#if (defined(CFG_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))
diff --git a/common/serial.c b/common/serial.c
index 13e9f30..dee1cc0 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
-#ifndef CONFIG_LWMON
+#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
struct serial_device *default_serial_console (void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
@@ -65,7 +65,7 @@ struct serial_device *default_serial_console (void)
}
#endif
-static int serial_register (struct serial_device *dev)
+int serial_register (struct serial_device *dev)
{
dev->init += gd->reloc_off;
dev->setbrg += gd->reloc_off;
@@ -110,6 +110,15 @@ void serial_initialize (void)
serial_register(&eserial4_device);
#endif
#endif /* CFG_NS16550_SERIAL */
+#if defined (CONFIG_FFUART)
+ serial_register(&serial_ffuart_device);
+#endif
+#if defined (CONFIG_BTUART)
+ serial_register(&serial_btuart_device);
+#endif
+#if defined (CONFIG_STUART)
+ serial_register(&serial_stuart_device);
+#endif
serial_assign (default_serial_console ()->name);
}
diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk
index e39e774..6ab0dd3 100644
--- a/cpu/arm1136/config.mk
+++ b/cpu/arm1136/config.mk
@@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv5
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 15c54af..1b0e147 100644
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -125,12 +125,12 @@ serial_puts (const char *s)
#elif defined(CONFIG_LPC2292)
+DECLARE_GLOBAL_DATA_PTR;
+
#include <asm/arch/hardware.h>
void serial_setbrg (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned short divisor = 0;
switch (gd->baudrate) {
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index b9c364b..aefcdd1 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -27,9 +27,7 @@
#include <config.h>
#include <version.h>
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-#include <led.h>
-#endif
+#include <status_led.h>
/*
*************************************************************************
@@ -41,7 +39,7 @@
.globl _start
-_start: b reset
+_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -64,7 +62,7 @@ _fiq: .word fiq
/*
*************************************************************************
*
- * Startup Code (reset vector)
+ * Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
@@ -106,10 +104,10 @@ FIQ_STACK_START:
/*
- * the actual reset code
+ * the actual start code
*/
-reset:
+start_code:
/*
* set the cpu to SVC32 mode
*/
@@ -118,58 +116,12 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
-#if CONFIG_AT91RM9200
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
- bl LED_init
+ bl coloured_LED_init
bl red_LED_on
-#endif
-#ifdef CONFIG_BOOTBINFUNC
-/* code based on entry.S from ATMEL */
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
- /* Get the CKGR Base Address */
- ldr r1, =AT91C_BASE_CKGR
-
-/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
-/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
- ldr r0, =0x0000FF01
- str r0, [r1, #CKGR_MOR]
- /* Add loop to compensate Main Oscillator startup time */
- ldr r0, =0x00000010
-LoopOsc:
- subs r0, r0, #1
- bhi LoopOsc
- /* scratch stack */
- ldr r1, =0x00204000
- /* Insure word alignment */
- bic r1, r1, #3
- /* Init stack SYS */
- mov sp, r1
- /*
- * This does a lot more than just set up the memory, which
- * is why it's called lowlevelinit
- */
- bl lowlevelinit /* in memsetup.S */
- bl icache_enable;
- /* ------------------------------------
- * Read/modify/write CP15 control register
- * -------------------------------------
- * read cp15 control register (cp15 r1) in r0
- * ------------------------------------
- */
- mrc p15, 0, r0, c1, c0, 0
- /* Reset bit :Little Endian end fast bus mode */
- ldr r3, =0xC0000080
- /* Set bit :Asynchronous clock mode, Not Fast Bus */
- ldr r4, =0xC0000000
- bic r0, r0, r3
- orr r0, r0, r4
- /* write r0 in cp15 control register (cp15 r1) */
- mcr p15, 0, r0, c1, c0, 0
-#endif /* CONFIG_BOOTBINFUNC */
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
/*
- * relocate exeception table
+ * relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
@@ -181,19 +133,20 @@ copyex:
bne copyex
#endif
-/* turn off the watchdog */
-#if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
-# define CLKDIVN 0x14800014 /* clock divisor register */
-#elif defined(CONFIG_S3C2410)
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
-# define INTSUBMSK 0x4A00001C
-# define CLKDIVN 0x4C000014 /* clock divisor register */
-#endif
-
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+ /* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define CLKDIVN 0x14800014 /* clock divisor register */
+#else
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTSUBMSK 0x4A00001C
+# define CLKDIVN 0x4C000014 /* clock divisor register */
+# endif
+
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
@@ -226,25 +179,7 @@ copyex:
#endif
#ifdef CONFIG_AT91RM9200
-#ifdef CONFIG_BOOTBINFUNC
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_BOOTBINFUNC */
-#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@@ -284,27 +219,6 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
ble clbss_l
-#if 0
- /* try doing this stuff after the relocation */
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =INTMR
- str r1, [r0]
-
- /* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #3
- str r1, [r0]
- /* END stuff after relocation */
-#endif
-
ldr pc, _start_armboot
_start_armboot: .word start_armboot
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
index 6cab5da..8ac6e3f 100644
--- a/cpu/bf533/serial.c
+++ b/cpu/bf533/serial.c
@@ -76,7 +76,6 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
- DECLARE_GLOBAL_DATA_PTR;
calc_baud();
diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c
index 3b0d026..0daba63 100644
--- a/cpu/bf537/i2c.c
+++ b/cpu/bf537/i2c.c
@@ -22,6 +22,8 @@
#include <i2c.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ (\
"%0 = w[%1] (z);\n\t"\
@@ -68,7 +70,6 @@
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
- DECLARE_GLOBAL_DATA_PTR; \
if (gd->have_console) \
printf(fmt ,##args); \
} while (0)
diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c
index e04d08a..f7a2483 100644
--- a/cpu/bf537/serial.c
+++ b/cpu/bf537/serial.c
@@ -52,6 +52,8 @@
#include <asm/io.h>
#include "serial.h"
+DECLARE_GLOBAL_DATA_PTR;
+
unsigned long pll_div_fact;
void calc_baud(void)
@@ -74,7 +76,6 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
- DECLARE_GLOBAL_DATA_PTR;
calc_baud();
diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c
index 7f5c695..bc5a4f5 100644
--- a/cpu/bf561/serial.c
+++ b/cpu/bf561/serial.c
@@ -52,6 +52,8 @@
#include "serial.h"
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
unsigned long pll_div_fact;
void calc_baud(void)
@@ -74,7 +76,6 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
- DECLARE_GLOBAL_DATA_PTR;
calc_baud();
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index 520f5d6..2f62e95 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -31,6 +31,8 @@
#include <asm/immap.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
@@ -48,8 +50,6 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int checkcpu(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c
index cf72609..001b9f4 100644
--- a/cpu/mcf532x/speed.c
+++ b/cpu/mcf532x/speed.c
@@ -30,6 +30,8 @@
#include <asm/immap.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* PLL min/max specifications */
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
@@ -208,8 +210,6 @@ int clock_pll(int fsys, int flags)
*/
int get_clocks(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
return (0);
diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
index 6ce0b55..4b7866f 100644
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2007 Michal Simek
*
- * Michal SIMEK <moonstr@monstr.eu>
+ * Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index 3c027ff..8740284 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -33,15 +33,13 @@ _start:
addi r1, r0, CFG_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
- addi r6, r0, 0xb000 /* hex b000 opcode imm */
- bslli r6, r6, 16 /* shift */
+ addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
swi r6, r0, 0x0 /* reset address */
swi r6, r0, 0x8 /* user vector exception */
swi r6, r0, 0x10 /* interrupt */
swi r6, r0, 0x20 /* hardware exception */
- addi r6, r0, 0xb808 /* hew b808 opcode brai*/
- bslli r6, r6, 16
+ addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
swi r6, r0, 0x4 /* reset address */
swi r6, r0, 0xC /* user vector exception */
swi r6, r0, 0x14 /* interrupt */
diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c
index ab1cb12..b350453 100644
--- a/cpu/microblaze/timer.c
+++ b/cpu/microblaze/timer.c
@@ -33,10 +33,17 @@ void reset_timer (void)
timestamp = 0;
}
+#ifdef CFG_TIMER_0
ulong get_timer (ulong base)
{
return (timestamp - base);
}
+#else
+ulong get_timer (ulong base)
+{
+ return (timestamp++ - base);
+}
+#endif
void set_timer (ulong t)
{
diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk
index 8a07c5a..3259d53 100644
--- a/cpu/mpc512x/config.mk
+++ b/cpu/mpc512x/config.mk
@@ -19,7 +19,7 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e
diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c
index 3c142a9..675b7a2 100644
--- a/cpu/mpc512x/fec.c
+++ b/cpu/mpc512x/fec.c
@@ -32,6 +32,9 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re
int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
+static uchar rx_buff[FEC_BUFFER_SIZE];
+static int rx_buff_idx = 0;
+
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
@@ -234,8 +237,8 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
/* Set Opcode/Pause Duration Register */
fec->eth->op_pause = 0x00010020;
- /* Frame length=1518; MII mode */
- fec->eth->r_cntrl = 0x05ee000c;
+ /* Frame length=1522; MII mode */
+ fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
/* Half-duplex, heartbeat disabled */
fec->eth->x_cntrl = 0x00000000;
@@ -245,7 +248,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
/* Setup recv fifo start and buff size */
fec->eth->r_fstart = 0x500;
- fec->eth->r_buff_size = 0x5e0;
+ fec->eth->r_buff_size = FEC_BUFFER_SIZE;
/* Setup BD base addresses */
fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
@@ -520,8 +523,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
unsigned long ievent;
- int frame_length, len = 0;
- uchar buff[FEC_MAX_PKT_SIZE];
+ int frame_length = 0;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
@@ -555,31 +557,37 @@ static int mpc512x_fec_recv (struct eth_device *dev)
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
- if ((pRbd->status & FEC_RBD_LAST) &&
- !(pRbd->status & FEC_RBD_ERR) &&
+ if (!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
/*
* Get buffer size
*/
- frame_length = pRbd->dataLength - 4;
-
+ if (pRbd->status & FEC_RBD_LAST)
+ frame_length = pRbd->dataLength - 4;
+ else
+ frame_length = pRbd->dataLength;
#if (DEBUG & 0x20)
{
int i;
- printf ("recv data hdr:");
+ printf ("recv data length 0x%08x data hdr: ",
+ pRbd->dataLength);
for (i = 0; i < 14; i++)
printf ("%x ", *((uint8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
-
/*
* Fill the buffer and pass it to upper layers
*/
- memcpy (buff, (void*)pRbd->dataPointer, frame_length);
- NetReceive ((uchar*)buff, frame_length);
- len = frame_length;
+ memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
+ frame_length - rx_buff_idx);
+ rx_buff_idx = frame_length;
+
+ if (pRbd->status & FEC_RBD_LAST) {
+ NetReceive ((uchar*)rx_buff, frame_length);
+ rx_buff_idx = 0;
+ }
}
/*
@@ -590,7 +598,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
/* Try to fill Buffer Descriptors */
fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
- return len;
+ return frame_length;
}
/********************************************************************/
diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h
index d2d877a..9c38502 100644
--- a/cpu/mpc512x/fec.h
+++ b/cpu/mpc512x/fec.h
@@ -164,10 +164,13 @@ typedef enum {
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
-#define FEC_MAX_PKT_SIZE 1536
+#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
+
+/* Buffer size must be evenly divisible by 16 */
+#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
typedef struct {
- uint8 frame[FEC_MAX_PKT_SIZE];
+ uint8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;
typedef struct {
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 1eac2bb..7f16b92 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -29,10 +29,12 @@
#include <watchdog.h>
#include <command.h>
#include <mpc5xxx.h>
+#include <asm/io.h>
#include <asm/processor.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -111,29 +113,43 @@ unsigned long get_tbclk (void)
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_cpu_setup(void *blob, bd_t *bd)
+#ifdef CONFIG_OF_LIBFDT
+static void do_fixup(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create)
{
- u32 *p;
- int len;
-
- /* Core XLB bus frequency */
- p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_busfreq);
-
- /* SOC peripherals use the IPB bus frequency */
- p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_ipbfreq);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
- if (p != NULL)
- memcpy(p, bd->bi_enetaddr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len);
- if (p != NULL)
- memcpy(p, bd->bi_enetaddr, 6);
+#if defined(DEBUG)
+ int i;
+ debug("Updating property '%s/%s' = ", node, prop);
+ for (i = 0; i < len; i++)
+ debug(" %.2x", *(u8*)(val+i));
+ debug("\n");
+#endif
+ int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create);
+ if (rc)
+ printf("Unable to update property %s:%s, err=%s\n",
+ node, prop, fdt_strerror(rc));
+}
+
+static void do_fixup_u32(void *fdt, const char *node, const char *prop,
+ u32 val, int create)
+{
+ val = cpu_to_fdt32(val);
+ do_fixup(fdt, node, prop, &val, sizeof(val), create);
+}
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+ int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
+ char * cpu_path = "/cpus/" OF_CPU;
+ char * eth_path = "/" OF_SOC "/ethernet@3000";
+
+ do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
+ do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
+ do_fixup_u32(blob, "/" OF_SOC, "system-frequency",
+ bd->bi_busfreq*div, 1);
+ do_fixup(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
+ do_fixup(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
}
#endif
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index c8e4666..4f8956e 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -29,6 +29,8 @@
#include <common.h>
#include <mpc86xx.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Breathe some life into the CPU...
*
@@ -38,7 +40,6 @@
void cpu_init_f(void)
{
- DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index f37ab43..059097f 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -948,19 +948,25 @@ unsigned int enable_ddr(unsigned int ddr_num)
* Read both dimm slots and decide whether
* or not to enable this controller.
*/
- memset((void *)&spd1,0,sizeof(spd1));
- memset((void *)&spd2,0,sizeof(spd2));
+ memset((void *)&spd1, 0, sizeof(spd1));
+ memset((void *)&spd2, 0, sizeof(spd2));
if (ddr_num == 1) {
CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
0, 1, (uchar *) &spd1, sizeof(spd1));
+#if defined(SPD_EEPROM_ADDRESS2)
CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
} else {
+#if defined(SPD_EEPROM_ADDRESS3)
CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
0, 1, (uchar *) &spd1, sizeof(spd1));
+#endif
+#if defined(SPD_EEPROM_ADDRESS4)
CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
}
/*
@@ -1105,21 +1111,25 @@ spd_sdram(void)
{
int memsize_ddr1_dimm1 = 0;
int memsize_ddr1_dimm2 = 0;
+ int memsize_ddr1 = 0;
+ unsigned int law_size_ddr1;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
int memsize_ddr2_dimm1 = 0;
int memsize_ddr2_dimm2 = 0;
- int memsize_total = 0;
- int memsize_ddr1 = 0;
int memsize_ddr2 = 0;
+ unsigned int law_size_ddr2;
+#endif
+
unsigned int ddr1_enabled = 0;
unsigned int ddr2_enabled = 0;
- unsigned int law_size_ddr1;
- unsigned int law_size_ddr2;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ int memsize_total = 0;
#ifdef CONFIG_DDR_INTERLEAVE
unsigned int law_size_interleaved;
- volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
@@ -1194,9 +1204,11 @@ spd_sdram(void)
(unsigned int)memsize_total * 1024*1024);
memsize_total += memsize_ddr1_dimm1;
+#if defined(SPD_EEPROM_ADDRESS2)
memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1, 2,
(unsigned int)memsize_total * 1024*1024);
+#endif
memsize_total += memsize_ddr1_dimm2;
/*
diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
index 312ca12..23161ca 100644
--- a/cpu/mpc86xx/speed.c
+++ b/cpu/mpc86xx/speed.c
@@ -29,6 +29,7 @@
#include <mpc86xx.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(sys_info_t *sysInfo)
{
@@ -96,7 +97,6 @@ void get_sys_info(sys_info_t *sysInfo)
int get_clocks(void)
{
- DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
get_sys_info(&sys_info);
diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c
index c84bfbf..04c2e13 100644
--- a/cpu/mpc86xx/traps.c
+++ b/cpu/mpc86xx/traps.c
@@ -34,6 +34,8 @@
#include <command.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@@ -50,8 +52,6 @@ extern unsigned long search_exception_table(unsigned long);
void
print_backtrace(unsigned long *sp)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int cnt = 0;
unsigned long i;
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 2837929..282e7a1 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -443,7 +443,7 @@ void pci_init_board(void)
static struct pci_controller ppc440_hose = {0};
-void pci_440_init (struct pci_controller *hose)
+int pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
@@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose)
if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
- return;
+ return -1;
}
#elif defined(CONFIG_440GP)
unsigned long strap;
@@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose)
if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
- return;
+ return -1;
}
#endif
#endif /* CONFIG_DISABLE_PISE_TEST */
@@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose)
* PCI controller init
*--------------------------------------------------------------------------*/
hose->first_busno = 0;
- hose->last_busno = 0xff;
+ hose->last_busno = 0;
/* PCI I/O space */
pci_set_region(hose->regions + reg_num++,
@@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose)
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
- return;
+ return -1;
}
pci_register_hose( hose );
@@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose)
#endif
hose->last_busno = pci_hose_scan(hose);
}
+ return hose->last_busno;
}
void pci_init_board(void)
{
- pci_440_init (&ppc440_hose);
+ int busno;
+
+ busno = pci_440_init (&ppc440_hose);
#if defined(CONFIG_440SPE)
- pcie_setup_hoses();
+ pcie_setup_hoses(busno + 1);
#endif
}
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index bf68cc1..3eac0ae 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -40,73 +40,126 @@ enum {
LNKW_X8 = 0x8
};
-static inline int pcie_in_8(const volatile unsigned char __iomem *addr)
+static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
{
- int ret;
-
- PCIE_IN(lbzx, ret, addr);
+ u8 *base = (u8*)hose->cfg_data;
+
+ /* use local configuration space for the first bus */
+ if (PCI_BUS(devfn) == 0) {
+ if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
+ base = (u8*)CFG_PCIE0_XCFGBASE;
+ if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
+ base = (u8*)CFG_PCIE1_XCFGBASE;
+ if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
+ base = (u8*)CFG_PCIE2_XCFGBASE;
+ }
- return ret;
+ return base;
}
-static inline int pcie_in_le16(const volatile unsigned short __iomem *addr)
+static void pcie_dmer_disable(void)
{
- int ret;
-
- PCIE_IN(lhbrx, ret, addr)
-
- return ret;
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
}
-static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr)
+static void pcie_dmer_enable(void)
{
- unsigned ret;
-
- PCIE_IN(lwbrx, ret, addr);
-
- return ret;
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
}
-
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
+ u8 *address;
*val = 0;
+
+ /*
+ * Bus numbers are relative to hose->first_busno
+ */
+ devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
+ /*
+ * NOTICE: configuration space ranges are currenlty mapped only for
+ * the first 16 buses, so such limit must be imposed. In case more
+ * buses are required the TLB settings in board/amcc/<board>/init.S
+ * need to be altered accordingly (one bus takes 1 MB of memory space).
+ */
+ if (PCI_BUS(devfn) >= 16)
+ return 0;
+
/*
- * 440SPE implements only one function per port
+ * Only single device/single function is supported for the primary and
+ * secondary buses of the 440SPe host bridge.
*/
- if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+ if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+ ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
- devfn = PCI_BDF(0,0,0);
+ address = pcie_get_base(hose, devfn);
offset += devfn << 4;
+ /*
+ * Reading from configuration space of non-existing device can
+ * generate transaction errors. For the read duration we suppress
+ * assertion of machine check exceptions to avoid those.
+ */
+ pcie_dmer_disable ();
+
switch (len) {
case 1:
- *val = pcie_in_8(hose->cfg_data + offset);
+ *val = in_8(hose->cfg_data + offset);
break;
case 2:
- *val = pcie_in_le16((u16 *)(hose->cfg_data + offset));
+ *val = in_le16((u16 *)(hose->cfg_data + offset));
break;
default:
- *val = pcie_in_le32((u32*)(hose->cfg_data + offset));
+ *val = in_le32((u32*)(hose->cfg_data + offset));
break;
}
+
+ pcie_dmer_enable ();
+
return 0;
}
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 val) {
+ u8 *address;
+
+ /*
+ * Bus numbers are relative to hose->first_busno
+ */
+ devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
/*
- * 440SPE implements only one function per port
+ * Same constraints as in pcie_read_config().
*/
- if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+ if (PCI_BUS(devfn) >= 16)
+ return 0;
+
+ if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+ ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
- devfn = PCI_BDF(0,0,0);
+ address = pcie_get_base(hose, devfn);
offset += devfn << 4;
+ /*
+ * Suppress MCK exceptions, similar to pcie_read_config()
+ */
+ pcie_dmer_disable ();
+
switch (len) {
case 1:
out_8(hose->cfg_data + offset, val);
@@ -118,6 +171,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
out_le32((u32 *)(hose->cfg_data + offset), val);
break;
}
+
+ pcie_dmer_enable ();
+
return 0;
}
@@ -126,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u
u32 v;
int rv;
- rv = pcie_read_config(hose, dev, offset, 1, &v);
+ rv = pcie_read_config(hose, dev, offset, 1, &v);
*val = (u8)v;
return rv;
}
@@ -783,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
volatile void *rmbase = NULL;
pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
switch (port) {
case 0:
@@ -811,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
/*
* Set bus numbers on our root port
*/
- if (ppc440spe_revB()) {
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
- } else {
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
- }
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+ out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
/*
* Set up outbound translation to hose->mem_space from PLB
@@ -875,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
printf("PCIE:%d successfully set as rootpoint\n",port);
+
+ /* Set Device and Vendor Id */
+ switch (port) {
+ case 0:
+ out_le16(mbase + 0x200, 0xaaa0);
+ out_le16(mbase + 0x202, 0xbed0);
+ break;
+ case 1:
+ out_le16(mbase + 0x200, 0xaaa1);
+ out_le16(mbase + 0x202, 0xbed1);
+ break;
+ case 2:
+ out_le16(mbase + 0x200, 0xaaa2);
+ out_le16(mbase + 0x202, 0xbed2);
+ break;
+ default:
+ out_le16(mbase + 0x200, 0xaaa3);
+ out_le16(mbase + 0x202, 0xbed3);
+ }
+
+ /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
+ out_le32(mbase + 0x208, 0x06040001);
+
}
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
@@ -952,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
attempts = 10;
diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h
index eb7cecf..38745eb 100644
--- a/cpu/ppc4xx/440spe_pcie.h
+++ b/cpu/ppc4xx/440spe_pcie.h
@@ -38,6 +38,7 @@
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
+#define DCRN_PEGPL_CFG(base) (base + 0x16)
/*
* System DCRs (SDRs)
@@ -161,20 +162,7 @@
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
-#define PCIE_IN(opcode, ret, addr) \
- __asm__ __volatile__( \
- "sync\n" \
- #opcode " %0,0,%1\n" \
- "1: twi 0,%0,0\n" \
- "isync\n" \
- "b 3f\n" \
- "2: li %0,-1\n" \
- "3:\n" \
- ".section __ex_table,\"a\"\n" \
- ".balign 4\n" \
- ".long 1b,2b\n" \
- ".previous\n" \
- : "=r" (ret) : "r" (addr), "m" (*addr));
+#define GPL_DMER_MASK_DISA 0x02000000
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index cc8e734..71a9e37 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -138,7 +138,8 @@
#define BI_PHYMODE_MII 7
#endif
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
@@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
int ethgroup = -1;
#endif
#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long mfr;
#endif
@@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -920,8 +924,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set speed */
if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index f5365cb..38b6f89 100644
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs)
int uncorr_ecc = 0;
#endif
- /* Probing PCI(E) using config cycles may cause this exception
- * when a device is not present. To gracefully recover in such
- * scenarios config read/write routines need to be instrumented in
- * order to return via fixup handler. For examples refer to
- * pcie_in_8(), pcie_in_le16() and pcie_in_le32()
- */
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
val = mfspr(MCSR);
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index 0fbaa16..d76e0cd 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -438,11 +438,11 @@ mmc_init(int verbose)
/* FIXME fill in the correct size (is set to 32MByte) */
mmc_dev.blksz = 512;
mmc_dev.lba = 0x10000;
- sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
+ sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
cid->id[0], cid->id[1], cid->id[2],
cid->sn[0], cid->sn[1], cid->sn[2]);
- sprintf(mmc_dev.product,"%s",cid->name);
- sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
+ sprintf((char*)mmc_dev.product,"%s",cid->name);
+ sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
mmc_dev.removable = 0;
mmc_dev.block_read = mmc_bread;
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
index cb3a478..51e7f65 100644
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@@ -30,11 +30,28 @@
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+#define FFUART 0
+#define BTUART 1
+#define STUART 2
+
+#ifndef CONFIG_SERIAL_MULTI
+#if defined (CONFIG_FFUART)
+#define UART_INDEX FFUART
+#elif defined (CONFIG_BTUART)
+#define UART_INDEX BTUART
+#elif defined (CONFIG_STUART)
+#define UART_INDEX STUART
+#else
+#error "Bad: you didn't configure serial ..."
+#endif
+#endif
+
+void pxa_setbrg_dev (unsigned int uart_index)
{
unsigned int quot = 0;
@@ -53,63 +70,68 @@ void serial_setbrg (void)
else
hang ();
-#ifdef CONFIG_FFUART
+ switch (uart_index) {
+ case FFUART:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_22_FFUART;
+ CKENA |= CKENA_22_FFUART;
#else
- CKEN |= CKEN6_FFUART;
+ CKEN |= CKEN6_FFUART;
#endif /* CONFIG_CPU_MONAHANS */
- FFIER = 0; /* Disable for now */
- FFFCR = 0; /* No fifos enabled */
+ FFIER = 0; /* Disable for now */
+ FFFCR = 0; /* No fifos enabled */
- /* set baud rate */
- FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
- FFDLL = quot & 0xff;
- FFDLH = quot >> 8;
- FFLCR = LCR_WLS0 | LCR_WLS1;
+ /* set baud rate */
+ FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
+ FFDLL = quot & 0xff;
+ FFDLH = quot >> 8;
+ FFLCR = LCR_WLS0 | LCR_WLS1;
- FFIER = IER_UUE; /* Enable FFUART */
+ FFIER = IER_UUE; /* Enable FFUART */
+ break;
-#elif defined(CONFIG_BTUART)
+ case BTUART:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_21_BTUART;
+ CKENA |= CKENA_21_BTUART;
#else
- CKEN |= CKEN7_BTUART;
+ CKEN |= CKEN7_BTUART;
#endif /* CONFIG_CPU_MONAHANS */
- BTIER = 0;
- BTFCR = 0;
+ BTIER = 0;
+ BTFCR = 0;
- /* set baud rate */
- BTLCR = LCR_DLAB;
- BTDLL = quot & 0xff;
- BTDLH = quot >> 8;
- BTLCR = LCR_WLS0 | LCR_WLS1;
+ /* set baud rate */
+ BTLCR = LCR_DLAB;
+ BTDLL = quot & 0xff;
+ BTDLH = quot >> 8;
+ BTLCR = LCR_WLS0 | LCR_WLS1;
- BTIER = IER_UUE; /* Enable BFUART */
+ BTIER = IER_UUE; /* Enable BFUART */
-#elif defined(CONFIG_STUART)
+ break;
+
+ case STUART:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_23_STUART;
+ CKENA |= CKENA_23_STUART;
#else
- CKEN |= CKEN5_STUART;
+ CKEN |= CKEN5_STUART;
#endif /* CONFIG_CPU_MONAHANS */
- STIER = 0;
- STFCR = 0;
+ STIER = 0;
+ STFCR = 0;
- /* set baud rate */
- STLCR = LCR_DLAB;
- STDLL = quot & 0xff;
- STDLH = quot >> 8;
- STLCR = LCR_WLS0 | LCR_WLS1;
+ /* set baud rate */
+ STLCR = LCR_DLAB;
+ STDLL = quot & 0xff;
+ STDLH = quot >> 8;
+ STLCR = LCR_WLS0 | LCR_WLS1;
- STIER = IER_UUE; /* Enable STUART */
+ STIER = IER_UUE; /* Enable STUART */
+ break;
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
+ default:
+ hang();
+ }
}
@@ -118,9 +140,9 @@ void serial_setbrg (void)
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+int pxa_init_dev (unsigned int uart_index)
{
- serial_setbrg ();
+ pxa_setbrg_dev (uart_index);
return (0);
}
@@ -129,26 +151,32 @@ int serial_init (void)
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
-{
-#ifdef CONFIG_FFUART
- /* wait for room in the tx FIFO on FFUART */
- while ((FFLSR & LSR_TEMT) == 0)
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- FFTHR = c;
-#elif defined(CONFIG_BTUART)
- while ((BTLSR & LSR_TEMT ) == 0 )
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- BTTHR = c;
-#elif defined(CONFIG_STUART)
- while ((STLSR & LSR_TEMT ) == 0 )
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- STTHR = c;
-#endif
+void pxa_putc_dev (unsigned int uart_index,const char c)
+{
+ switch (uart_index) {
+ case FFUART:
+ /* wait for room in the tx FIFO on FFUART */
+ while ((FFLSR & LSR_TEMT) == 0)
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ FFTHR = c;
+ break;
+
+ case BTUART:
+ while ((BTLSR & LSR_TEMT ) == 0 )
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ BTTHR = c;
+ break;
+
+ case STUART:
+ while ((STLSR & LSR_TEMT ) == 0 )
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ STTHR = c;
+ break;
+ }
/* If \n, also do \r */
if (c == '\n')
- serial_putc ('\r');
+ pxa_putc_dev (uart_index,'\r');
}
/*
@@ -156,15 +184,17 @@ void serial_putc (const char c)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
-{
-#ifdef CONFIG_FFUART
- return FFLSR & LSR_DR;
-#elif defined(CONFIG_BTUART)
- return BTLSR & LSR_DR;
-#elif defined(CONFIG_STUART)
- return STLSR & LSR_DR;
-#endif
+int pxa_tstc_dev (unsigned int uart_index)
+{
+ switch (uart_index) {
+ case FFUART:
+ return FFLSR & LSR_DR;
+ case BTUART:
+ return BTLSR & LSR_DR;
+ case STUART:
+ return STLSR & LSR_DR;
+ }
+ return -1;
}
/*
@@ -172,27 +202,184 @@ int serial_tstc (void)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
-{
-#ifdef CONFIG_FFUART
- while (!(FFLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) FFRBR & 0xff;
-#elif defined(CONFIG_BTUART)
- while (!(BTLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) BTRBR & 0xff;
-#elif defined(CONFIG_STUART)
- while (!(STLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) STRBR & 0xff;
-#endif
+int pxa_getc_dev (unsigned int uart_index)
+{
+ switch (uart_index) {
+ case FFUART:
+ while (!(FFLSR & LSR_DR))
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ return (char) FFRBR & 0xff;
+
+ case BTUART:
+ while (!(BTLSR & LSR_DR))
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ return (char) BTRBR & 0xff;
+ case STUART:
+ while (!(STLSR & LSR_DR))
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ return (char) STRBR & 0xff;
+ }
+ return -1;
}
void
-serial_puts (const char *s)
+pxa_puts_dev (unsigned int uart_index,const char *s)
{
while (*s) {
- serial_putc (*s++);
+ pxa_putc_dev (uart_index,*s++);
}
}
+
+#if defined (CONFIG_FFUART)
+static int ffuart_init(void)
+{
+ return pxa_init_dev(FFUART);
+}
+
+static void ffuart_setbrg(void)
+{
+ return pxa_setbrg_dev(FFUART);
+}
+
+static void ffuart_putc(const char c)
+{
+ return pxa_putc_dev(FFUART,c);
+}
+
+static void ffuart_puts(const char *s)
+{
+ return pxa_puts_dev(FFUART,s);
+}
+
+static int ffuart_getc(void)
+{
+ return pxa_getc_dev(FFUART);
+}
+
+static int ffuart_tstc(void)
+{
+ return pxa_tstc_dev(FFUART);
+}
+
+struct serial_device serial_ffuart_device =
+{
+ "serial_ffuart",
+ "PXA",
+ ffuart_init,
+ ffuart_setbrg,
+ ffuart_getc,
+ ffuart_tstc,
+ ffuart_putc,
+ ffuart_puts,
+};
+#endif
+
+#if defined (CONFIG_BTUART)
+static int btuart_init(void)
+{
+ return pxa_init_dev(BTUART);
+}
+
+static void btuart_setbrg(void)
+{
+ return pxa_setbrg_dev(BTUART);
+}
+
+static void btuart_putc(const char c)
+{
+ return pxa_putc_dev(BTUART,c);
+}
+
+static void btuart_puts(const char *s)
+{
+ return pxa_puts_dev(BTUART,s);
+}
+
+static int btuart_getc(void)
+{
+ return pxa_getc_dev(BTUART);
+}
+
+static int btuart_tstc(void)
+{
+ return pxa_tstc_dev(BTUART);
+}
+
+struct serial_device serial_btuart_device =
+{
+ "serial_btuart",
+ "PXA",
+ btuart_init,
+ btuart_setbrg,
+ btuart_getc,
+ btuart_tstc,
+ btuart_putc,
+ btuart_puts,
+};
+#endif
+
+#if defined (CONFIG_STUART)
+static int stuart_init(void)
+{
+ return pxa_init_dev(STUART);
+}
+
+static void stuart_setbrg(void)
+{
+ return pxa_setbrg_dev(STUART);
+}
+
+static void stuart_putc(const char c)
+{
+ return pxa_putc_dev(STUART,c);
+}
+
+static void stuart_puts(const char *s)
+{
+ return pxa_puts_dev(STUART,s);
+}
+
+static int stuart_getc(void)
+{
+ return pxa_getc_dev(STUART);
+}
+
+static int stuart_tstc(void)
+{
+ return pxa_tstc_dev(STUART);
+}
+
+struct serial_device serial_stuart_device =
+{
+ "serial_stuart",
+ "PXA",
+ stuart_init,
+ stuart_setbrg,
+ stuart_getc,
+ stuart_tstc,
+ stuart_putc,
+ stuart_puts,
+};
+#endif
+
+
+#ifndef CONFIG_SERIAL_MULTI
+inline int serial_init(void) {
+ return (pxa_init_dev(UART_INDEX));
+}
+void serial_setbrg(void) {
+ pxa_setbrg_dev(UART_INDEX);
+}
+int serial_getc(void) {
+ return(pxa_getc_dev(UART_INDEX));
+}
+int serial_tstc(void) {
+ return(pxa_tstc_dev(UART_INDEX));
+}
+void serial_putc(const char c) {
+ pxa_putc_dev(UART_INDEX,c);
+}
+void serial_puts(const char *s) {
+ pxa_puts_dev(UART_INDEX,s);
+}
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c
index 65f457f..3c11d4d 100644
--- a/cpu/pxa/usb.c
+++ b/cpu/pxa/usb.c
@@ -67,6 +67,22 @@ int usb_cpu_init()
int usb_cpu_stop()
{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+ UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+ UHCHR |= UHCHR_SSEP2;
+#endif
+ UHCHR |= UHCHR_SSEP1;
+ UHCHR |= UHCHR_SSE;
+
return 0;
}
diff --git a/drivers/Makefile b/drivers/Makefile
index 3ee6312..6bf05cc 100755
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -43,7 +43,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \
sed13806.o sed156x.o \
serial.o serial_max3100.o \
serial_pl010.o serial_pl011.o serial_xuartlite.o \
- sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
+ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o systemace.o ahci.o \
ti_pci1410a.o tigon3.o tsec.o \
tsi108_eth.o tsi108_i2c.o tsi108_pci.o \
diff --git a/drivers/at45.c b/drivers/at45.c
index 507ff36..dac987a 100755..100644
--- a/drivers/at45.c
+++ b/drivers/at45.c
@@ -27,33 +27,31 @@
/*
* spi.c API
*/
-extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc);
-extern void AT91F_SpiEnable(int cs);
+extern unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc);
+extern void AT91F_SpiEnable(int cs);
#define AT91C_TIMEOUT_WRDY 200000
-
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashSendCommand */
/* \brief Generic function to send a command to the dataflash */
/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
- AT91PS_DataFlash pDataFlash,
- unsigned char OpCode,
- unsigned int CmdSize,
- unsigned int DataflashAddress)
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress)
{
unsigned int adr;
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ if ((pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* process the address to obtain page address and byte address */
adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) <<
- pDataFlash->pDevice->page_offset) + (DataflashAddress %
- (pDataFlash->pDevice->pages_size));
+ pDataFlash->pDevice->page_offset) +
+ (DataflashAddress % (pDataFlash->pDevice->pages_size));
- /* fill the command buffer */
+ /* fill the command buffer */
pDataFlash->pDataFlashDesc->command[0] = OpCode;
if (pDataFlash->pDevice->pages_number >= 16384) {
pDataFlash->pDataFlashDesc->command[1] =
@@ -78,16 +76,16 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
pDataFlash->pDataFlashDesc->command[7] = 0;
/* Initialize the SpiData structure for the spi write fuction */
- pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
- pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
- pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
- pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
/* send the command and read the data */
- return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); }
-
+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashGetStatus */
@@ -98,50 +96,49 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
AT91S_DataFlashStatus status;
/* if a transfert is in progress ==> return 0 */
- if( (pDesc->state) != IDLE)
+ if ((pDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* first send the read status command (D7H) */
pDesc->command[0] = DB_STATUS;
pDesc->command[1] = 0;
- pDesc->DataFlash_state = GET_STATUS;
- pDesc->tx_data_size = 0; /* Transmit the command */
- /* and receive response */
- pDesc->tx_cmd_pt = pDesc->command;
- pDesc->rx_cmd_pt = pDesc->command;
- pDesc->rx_cmd_size = 2;
- pDesc->tx_cmd_size = 2;
- status = AT91F_SpiWrite (pDesc);
+ pDesc->DataFlash_state = GET_STATUS;
+ pDesc->tx_data_size = 0; /* Transmit the command */
+ /* and receive response */
+ pDesc->tx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_size = 2;
+ pDesc->tx_cmd_size = 2;
+ status = AT91F_SpiWrite(pDesc);
- pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+ pDesc->DataFlash_state = *((unsigned char *)(pDesc->rx_cmd_pt) + 1);
return status;
}
-
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashWaitReady */
/* \brief wait for dataflash ready (bit7 of the status register == 1) */
/*----------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
-pDataFlashDesc, unsigned int timeout)
+ pDataFlashDesc,
+ unsigned int timeout)
{
pDataFlashDesc->DataFlash_state = IDLE;
do {
AT91F_DataFlashGetStatus(pDataFlashDesc);
timeout--;
- } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
- (timeout > 0) );
+ } while (((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
+ (timeout > 0));
- if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+ if ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
return DATAFLASH_ERROR;
return DATAFLASH_OK;
}
-
/*--------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashContinuousRead */
/* Object : Continuous stream Read */
@@ -151,17 +148,17 @@ pDataFlashDesc, unsigned int timeout)
/* : <sizeToRead> = data buffer size */
/* Return value : State of the dataflash */
/*--------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
- int src,
- unsigned char *dataBuffer,
- int sizeToRead )
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead)
{
AT91S_DataFlashStatus status;
/* Test the size to read in the device */
- if ( (src + sizeToRead) >
- (pDataFlash->pDevice->pages_size *
- (pDataFlash->pDevice->pages_number)))
+ if ((src + sizeToRead) >
+ (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
@@ -169,13 +166,12 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
- status = AT91F_DataFlashSendCommand
- (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+ status = AT91F_DataFlashSendCommand(
+ pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
/* Send the command to the dataflash */
- return(status);
+ return (status);
}
-
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashPagePgmBuf */
/* Object : Main memory page program thru buffer 1 or buffer 2 */
@@ -185,11 +181,10 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
/* : <SizeToWrite> = data buffer size */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int SizeToWrite)
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite)
{
int cmdsize;
pDataFlash->pDataFlashDesc->tx_data_pt = src;
@@ -201,9 +196,9 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
/* Send the command to the dataflash */
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1,
-cmdsize, dest)); }
-
+ return (AT91F_DataFlashSendCommand(
+ pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_MainMemoryToBufferTransfert */
@@ -214,26 +209,29 @@ cmdsize, dest)); }
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int page)
+ AT91PS_DataFlash
+ pDataFlash,
+ unsigned char
+ BufferCommand,
+ unsigned int page)
{
int cmdsize;
/* Test if the buffer command is legal */
- if ((BufferCommand != DB_PAGE_2_BUF1_TRF)
- && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF) &&
+ (BufferCommand != DB_PAGE_2_BUF2_TRF)) {
return DATAFLASH_BAD_COMMAND;
+ }
/* no data to transmit or receive */
pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
-page*pDataFlash->pDevice->pages_size));
+ return (AT91F_DataFlashSendCommand(
+ pDataFlash, BufferCommand, cmdsize,
+ page * pDataFlash->pDevice->pages_size));
}
-
/*-------------------------------------------------------------------------- */
/* Function Name : AT91F_DataFlashWriteBuffer */
/* Object : Write data to the internal sram buffer 1 or 2 */
@@ -244,58 +242,61 @@ page*pDataFlash->pDevice->pages_size));
/* : <SizeToWrite> = data buffer size */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned char *dataBuffer,
- unsigned int bufferAddress,
- int SizeToWrite )
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite)
{
int cmdsize;
/* Test if the buffer command is legal */
- if ((BufferCommand != DB_BUF1_WRITE)
- && (BufferCommand != DB_BUF2_WRITE))
+ if ((BufferCommand != DB_BUF1_WRITE) &&
+ (BufferCommand != DB_BUF2_WRITE)) {
return DATAFLASH_BAD_COMMAND;
+ }
/* buffer address must be lower than page size */
if (bufferAddress > pDataFlash->pDevice->pages_size)
return DATAFLASH_BAD_ADDRESS;
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ if ((pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* Send first Write Command */
pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
pDataFlash->pDataFlashDesc->command[1] = 0;
if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[2] = 0;
- pDataFlash->pDataFlashDesc->command[3] =
+ pDataFlash->pDataFlashDesc->command[2] = 0;
+ pDataFlash->pDataFlashDesc->command[3] =
(unsigned char)(((unsigned int)(bufferAddress &
- pDataFlash->pDevice->byte_mask)) >> 8);
- pDataFlash->pDataFlashDesc->command[4] =
- (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ pDataFlash->pDevice->
+ byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
cmdsize = 5;
} else {
- pDataFlash->pDataFlashDesc->command[2] =
+ pDataFlash->pDataFlashDesc->command[2] =
(unsigned char)(((unsigned int)(bufferAddress &
- pDataFlash->pDevice->byte_mask)) >> 8);
- pDataFlash->pDataFlashDesc->command[3] =
- (unsigned char)((unsigned int)bufferAddress & 0x00FF);
- pDataFlash->pDataFlashDesc->command[4] = 0;
+ pDataFlash->pDevice->
+ byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ pDataFlash->pDataFlashDesc->command[4] = 0;
cmdsize = 4;
}
- pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize;
- pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize;
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
}
@@ -309,22 +310,22 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_PageErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int page)
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page)
{
int cmdsize;
/* Test if the buffer command is legal */
/* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize,
-page*pDataFlash->pDevice->pages_size));
+ return (AT91F_DataFlashSendCommand(pDataFlash,
+ DB_PAGE_ERASE, cmdsize,
+ page * pDataFlash->pDevice->pages_size));
}
-
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_BlockErase */
/* Object : Erase a Block */
@@ -334,18 +335,19 @@ page*pDataFlash->pDevice->pages_size));
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_BlockErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int block)
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block)
{
int cmdsize;
/* Test if the buffer command is legal */
/* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize,
-block*8*pDataFlash->pDevice->pages_size));
+ return (AT91F_DataFlashSendCommand(pDataFlash, DB_BLOCK_ERASE, cmdsize,
+ block * 8 *
+ pDataFlash->pDevice->pages_size));
}
/*---------------------------------------------------------------------------*/
@@ -356,17 +358,16 @@ block*8*pDataFlash->pDevice->pages_size));
/* : <dest> = main memory address */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int dest )
+AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest)
{
int cmdsize;
/* Test if the buffer command is correct */
if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
- (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM))
return DATAFLASH_BAD_COMMAND;
/* no data to transmit or receive */
@@ -376,9 +377,9 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain (
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
/* Send the command to the dataflash */
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
- dest)); }
-
+ return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand,
+ cmdsize, dest));
+}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_PartialPageWrite */
@@ -387,11 +388,10 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain (
/* : <AdrInpage> = adr to begin the fading */
/* : <length> = Number of bytes to erase */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int size)
+AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size)
{
unsigned int page;
unsigned int AdrInPage;
@@ -400,10 +400,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
AdrInPage = dest % (pDataFlash->pDevice->pages_size);
/* Read the contents of the page in the Sram Buffer */
- AT91F_MainMemoryToBufferTransfert(pDataFlash,
- DB_PAGE_2_BUF1_TRF, page);
+ AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
/*Update the SRAM buffer */
AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
AdrInPage, size);
@@ -416,12 +415,13 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91F_PageErase(pDataFlash, page);
/* Rewrite the modified Sram Buffer in the main memory */
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
}
/* Rewrite the modified Sram Buffer in the main memory */
- return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
- (page*pDataFlash->pDevice->pages_size)));
+ return (AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
+ (page *
+ pDataFlash->pDevice->pages_size)));
}
/*---------------------------------------------------------------------------*/
@@ -431,11 +431,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
/* : <dest> = dataflash adress */
/* : <size> = data buffer size */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size )
+AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest, int size)
{
unsigned int length;
unsigned int page;
@@ -443,26 +441,24 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91F_SpiEnable(pDataFlash->pDevice->cs);
- if ( (dest + size) > (pDataFlash->pDevice->pages_size *
- (pDataFlash->pDevice->pages_number)))
+ if ((dest + size) > (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
/* If destination does not fit a page start address */
- if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 )
- {
- length = pDataFlash->pDevice->pages_size -
- (dest %
- ((unsigned int)
- (pDataFlash->pDevice->pages_size)));
+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) {
+ length =
+ pDataFlash->pDevice->pages_size -
+ (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
if (size < length)
length = size;
- if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+ if (!AT91F_PartialPageWrite(pDataFlash, src, dest, length))
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
/* Update size, source and destination pointers */
size -= length;
@@ -470,78 +466,77 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(
src += length;
}
- while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+ while ((size - pDataFlash->pDevice->pages_size) >= 0) {
/* program dataflash page */
page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
status = AT91F_DataFlashWriteBuffer(pDataFlash,
- DB_BUF1_WRITE, src, 0,
- pDataFlash->pDevice->pages_size);
+ DB_BUF1_WRITE, src, 0,
+ pDataFlash->pDevice->
+ pages_size);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
status = AT91F_PageErase(pDataFlash, page);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
if (!status)
return DATAFLASH_ERROR;
- status = AT91F_WriteBufferToMain (pDataFlash,
- DB_BUF1_PAGE_PGM, dest);
- if(!status)
+ status = AT91F_WriteBufferToMain(pDataFlash,
+ DB_BUF1_PAGE_PGM, dest);
+ if (!status)
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
/* Update size, source and destination pointers */
size -= pDataFlash->pDevice->pages_size;
dest += pDataFlash->pDevice->pages_size;
- src += pDataFlash->pDevice->pages_size;
+ src += pDataFlash->pDevice->pages_size;
}
/* If still some bytes to read */
- if ( size > 0 ) {
+ if (size > 0) {
/* program dataflash page */
- if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+ if (!AT91F_PartialPageWrite(pDataFlash, src, dest, size))
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
}
return DATAFLASH_OK;
}
-
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashRead */
/* Object : Read a block in dataflash */
/* Input Parameters : */
/* Return value : */
/*---------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
- AT91PS_DataFlash pDataFlash,
- unsigned long addr,
- unsigned long size,
- char *buffer)
+int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash,
+ unsigned long addr, unsigned long size, char *buffer)
{
unsigned long SizeToRead;
AT91F_SpiEnable(pDataFlash->pDevice->cs);
- if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
return -1;
while (size) {
- SizeToRead = (size < 0x8000)? size:0x8000;
+ SizeToRead = (size < 0x8000) ? size : 0x8000;
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ AT91C_TIMEOUT_WRDY) !=
+ DATAFLASH_OK)
return -1;
- if (AT91F_DataFlashContinuousRead (pDataFlash, addr,
- (uchar *) buffer, SizeToRead) != DATAFLASH_OK)
+ if (AT91F_DataFlashContinuousRead(pDataFlash, addr,
+ (uchar *) buffer,
+ SizeToRead) != DATAFLASH_OK)
return -1;
size -= SizeToRead;
@@ -558,9 +553,10 @@ int AT91F_DataFlashRead(
/* Input Parameters : */
/* Return value : Dataflash status register */
/*---------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) {
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
AT91F_SpiEnable(cs);
AT91F_DataFlashGetStatus(pDesc);
- return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+ return ((pDesc->command[1] == 0xFF) ? 0 : pDesc->command[1] & 0x3C);
}
#endif
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index 586e83b..90c64da 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libatibiosemu.a
-X86DIR = ./x86emu
+X86DIR = x86emu
-OBJS = atibios.o biosemu.o besys.o bios.o \
+$(shell mkdir -p $(obj)$(X86DIR))
+
+COBJS = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/decode.o \
$(X86DIR)/ops2.o \
$(X86DIR)/ops.o \
@@ -12,19 +14,24 @@ OBJS = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/sys.o \
$(X86DIR)/debug.o
-CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
-D__PPC__ -D__BIG_ENDIAN__
+CFLAGS += $(EXTRA_CFLAGS)
+HOST_CFLAGS += $(EXTRA_CFLAGS)
+
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c
index e0d531b..6131b5c 100644
--- a/drivers/dm9000x.c
+++ b/drivers/dm9000x.c
@@ -99,7 +99,7 @@ void eth_halt(void);
static int dm9000_probe(void);
static u16 phy_read(int);
static void phy_write(int, u16);
-static u16 read_srom_word(int);
+u16 read_srom_word(int);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);
@@ -537,7 +537,7 @@ eth_rx(void)
/*
Read a word data from SROM
*/
-static u16
+u16
read_srom_word(int offset)
{
DM9000_iow(DM9000_EPAR, offset);
@@ -547,6 +547,18 @@ read_srom_word(int offset)
return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
}
+void
+write_srom_word(int offset, u16 val)
+{
+ DM9000_iow(DM9000_EPAR, offset);
+ DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
+ DM9000_iow(DM9000_EPDRL, (val & 0xff));
+ DM9000_iow(DM9000_EPCR, 0x12);
+ udelay(8000);
+ DM9000_iow(DM9000_EPCR, 0);
+}
+
+
/*
Read a byte from I/O port
*/
diff --git a/drivers/isp116x-hcd.c b/drivers/isp116x-hcd.c
index 8e2bc7a..b21af10 100644
--- a/drivers/isp116x-hcd.c
+++ b/drivers/isp116x-hcd.c
@@ -113,9 +113,9 @@ static const char hcd_name[] = "isp116x-hcd";
struct isp116x isp116x_dev;
struct isp116x_platform_data isp116x_board;
-int got_rhsc = 0; /* root hub status change */
+static int got_rhsc; /* root hub status change */
struct usb_device *devgone; /* device which was disconnected */
-int rh_devnum = 0; /* address of Root Hub endpoint */
+static int rh_devnum; /* address of Root Hub endpoint */
/* ------------------------------------------------------------------------- */
@@ -522,11 +522,13 @@ static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
done += PTD_GET_LEN(&ptd[i]);
cc = PTD_GET_CC(&ptd[i]);
- if (cc == TD_DATAUNDERRUN) { /* underrun is no error... */
- DBG("allowed data underrun");
- cc = TD_CC_NOERROR;
- }
- if (cc != TD_CC_NOERROR && ret == TD_CC_NOERROR)
+
+ /* Data underrun means basically that we had more buffer space than
+ * the function had data. It is perfectly normal but upper levels have
+ * to know how much we actually transferred.
+ */
+ if (cc == TD_NOTACCESSED ||
+ (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
ret = cc;
}
@@ -592,11 +594,19 @@ static int isp116x_interrupt(struct isp116x *isp116x)
return ret;
}
-#define PTD_NUM 64 /* it should be enougth... */
-struct ptd ptd[PTD_NUM];
+/* With one PTD we can transfer almost 1K in one go;
+ * HC does the splitting into endpoint digestible transactions
+ */
+struct ptd ptd[1];
+
static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
{
- return min(PTD_NUM * usb_maxpacket(dev, pipe), PTD_NUM * 16);
+ unsigned mpck = usb_maxpacket(dev, pipe);
+
+ /* One PTD can transfer 1023 bytes but try to always
+ * transfer multiples of endpoint buffer size
+ */
+ return 1023 / mpck * mpck;
}
/* Do an USB transfer
@@ -610,13 +620,21 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
int max = usb_maxpacket(dev, pipe);
int dir_out = usb_pipeout(pipe);
int speed_low = usb_pipeslow(pipe);
- int i, done, stat, timeout, cc;
- int retries = 10;
+ int i, done = 0, stat, timeout, cc;
+
+ /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
+ int retries = 500;
DBG("------------------------------------------------");
dump_msg(dev, pipe, buffer, len, "SUBMIT");
DBG("------------------------------------------------");
+ if (len >= 1024) {
+ ERR("Too big job");
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
if (isp116x->disabled) {
ERR("EPIPE");
dev->status = USB_ST_CRC_ERR;
@@ -653,29 +671,15 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
/* Prepare the PTD data */
- done = 0;
- i = 0;
- do {
- ptd[i].count = PTD_CC_MSK | PTD_ACTIVE_MSK |
- PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
- ptd[i].mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum);
- ptd[i].len = PTD_LEN(max > len - done ? len - done : max) |
- PTD_DIR(dir);
- ptd[i].faddr = PTD_FA(usb_pipedevice(pipe));
-
- usb_dotoggle(dev, epnum, dir_out);
- done += PTD_GET_LEN(&ptd[i]);
- i++;
- if (i >= PTD_NUM) {
- ERR("****** Cannot pack buffer! ******");
- dev->status = USB_ST_BUF_ERR;
- return -1;
- }
- } while (done < len);
- ptd[i - 1].mps |= PTD_LAST_MSK;
+ ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+ PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+ ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
+ ptd->len = PTD_LEN(len) | PTD_DIR(dir);
+ ptd->faddr = PTD_FA(usb_pipedevice(pipe));
+retry_same:
/* Pack data into FIFO ram */
- pack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
+ pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
#ifdef EXTRA_DELAY
wait_ms(EXTRA_DELAY);
#endif
@@ -738,17 +742,42 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
}
/* Unpack data from FIFO ram */
- cc = unpack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
+ cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+ i = PTD_GET_COUNT(ptd);
+ done += i;
+ buffer += i;
+ len -= i;
- /* Mmm... sometime we get 0x0f as cc which is a non sense!
- * Just retry the transfer...
+ /* There was some kind of real problem; Prepare the PTD again
+ * and retry from the failed transaction on
*/
- if (cc == 0x0f && retries-- > 0) {
- usb_dotoggle(dev, epnum, dir_out);
- goto retry;
+ if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
+ if (retries >= 100) {
+ retries -= 100;
+ /* The chip will have toggled the toggle bit for the failed
+ * transaction too. We have to toggle it back.
+ */
+ usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
+ goto retry;
+ }
+ }
+ /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
+ * the transactions from the first on for the whole frame. It may be busy and we retry
+ * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
+ * PTD didn't make it because the function was busy or the frame ended before the PTD
+ * finished. We prepare the rest of the data and try again.
+ */
+ else if (cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || (cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
+ if (retries) {
+ --retries;
+ if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) goto retry_same;
+ usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+ goto retry;
+ }
}
- if (cc != TD_CC_NOERROR) {
+ if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
DBG("****** completition code error %x ******", cc);
switch (cc) {
case TD_CC_BITSTUFFING:
@@ -766,6 +795,7 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
}
return -cc;
}
+ else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
@@ -1369,6 +1399,8 @@ int usb_lowlevel_init(void)
DBG("");
+ got_rhsc = rh_devnum = 0;
+
/* Init device registers addr */
isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;
diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c
index cf05043..4fd4e16 100644
--- a/drivers/nand/nand_util.c
+++ b/drivers/nand/nand_util.c
@@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
if (!opts->quiet) {
unsigned long long n =(unsigned long long)
- (erase.addr+meminfo->erasesize-opts->offset)
- * 100;
- int percent = (int)do_div(n, erase_length);
+ (erase.addr + meminfo->erasesize - opts->offset)
+ * 100;
+ int percent;
+
+ do_div(n, erase_length);
+ percent = (int)n;
/* output progress message only at whole percent
* steps to reduce the number of messages printed
@@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
if (!opts->quiet) {
unsigned long long n = (unsigned long long)
(opts->length-imglen) * 100;
- int percent = (int)do_div(n, opts->length);
+ int percent;
+
+ do_div(n, opts->length);
+ percent = (int)n;
+
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
@@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
if (!opts->quiet) {
unsigned long long n = (unsigned long long)
(opts->length-imglen) * 100;
- int percent = (int)do_div(n ,opts->length);
+ int percent;
+
+ do_div(n, opts->length);
+ percent = (int)n;
+
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
diff --git a/drivers/onenand/Makefile b/drivers/onenand/Makefile
new file mode 100644
index 0000000..2049413
--- /dev/null
+++ b/drivers/onenand/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2005-2007 Samsung Electronics.
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libonenand.a
+
+COBJS := onenand_base.o onenand_bbt.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/onenand/onenand_base.c b/drivers/onenand/onenand_base.c
new file mode 100644
index 0000000..7983a4a
--- /dev/null
+++ b/drivers/onenand/onenand_base.c
@@ -0,0 +1,1294 @@
+/*
+ * linux/drivers/mtd/onenand/onenand_base.c
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+
+static const unsigned char ffchars[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
+};
+
+/**
+ * onenand_readw - [OneNAND Interface] Read OneNAND register
+ * @param addr address to read
+ *
+ * Read OneNAND register
+ */
+static unsigned short onenand_readw(void __iomem * addr)
+{
+ return readw(addr);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Write OneNAND register with value
+ * @param value value to write
+ * @param addr address to write
+ *
+ * Write OneNAND register with value
+ */
+static void onenand_writew(unsigned short value, void __iomem * addr)
+{
+ writew(value, addr);
+}
+
+/**
+ * onenand_block_address - [DEFAULT] Get block address
+ * @param device the device id
+ * @param block the block
+ * @return translated block address if DDP, otherwise same
+ *
+ * Setup Start Address 1 Register (F100h)
+ */
+static int onenand_block_address(int device, int block)
+{
+ if (device & ONENAND_DEVICE_IS_DDP) {
+ /* Device Flash Core select, NAND Flash Block Address */
+ int dfs = 0, density, mask;
+
+ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+ mask = (1 << (density + 6));
+
+ if (block & mask)
+ dfs = 1;
+
+ return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1));
+ }
+
+ return block;
+}
+
+/**
+ * onenand_bufferram_address - [DEFAULT] Get bufferram address
+ * @param device the device id
+ * @param block the block
+ * @return set DBS value if DDP, otherwise 0
+ *
+ * Setup Start Address 2 Register (F101h) for DDP
+ */
+static int onenand_bufferram_address(int device, int block)
+{
+ if (device & ONENAND_DEVICE_IS_DDP) {
+ /* Device BufferRAM Select */
+ int dbs = 0, density, mask;
+
+ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+ mask = (1 << (density + 6));
+
+ if (block & mask)
+ dbs = 1;
+
+ return (dbs << ONENAND_DDP_SHIFT);
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_page_address - [DEFAULT] Get page address
+ * @param page the page address
+ * @param sector the sector address
+ * @return combined page and sector address
+ *
+ * Setup Start Address 8 Register (F107h)
+ */
+static int onenand_page_address(int page, int sector)
+{
+ /* Flash Page Address, Flash Sector Address */
+ int fpa, fsa;
+
+ fpa = page & ONENAND_FPA_MASK;
+ fsa = sector & ONENAND_FSA_MASK;
+
+ return ((fpa << ONENAND_FPA_SHIFT) | fsa);
+}
+
+/**
+ * onenand_buffer_address - [DEFAULT] Get buffer address
+ * @param dataram1 DataRAM index
+ * @param sectors the sector address
+ * @param count the number of sectors
+ * @return the start buffer value
+ *
+ * Setup Start Buffer Register (F200h)
+ */
+static int onenand_buffer_address(int dataram1, int sectors, int count)
+{
+ int bsa, bsc;
+
+ /* BufferRAM Sector Address */
+ bsa = sectors & ONENAND_BSA_MASK;
+
+ if (dataram1)
+ bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
+ else
+ bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
+
+ /* BufferRAM Sector Count */
+ bsc = count & ONENAND_BSC_MASK;
+
+ return ((bsa << ONENAND_BSA_SHIFT) | bsc);
+}
+
+/**
+ * onenand_command - [DEFAULT] Send command to OneNAND device
+ * @param mtd MTD device structure
+ * @param cmd the command to be sent
+ * @param addr offset to read from or write to
+ * @param len number of bytes to read or write
+ *
+ * Send command to OneNAND device. This function is used for middle/large page
+ * devices (1KB/2KB Bytes per page)
+ */
+static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
+ size_t len)
+{
+ struct onenand_chip *this = mtd->priv;
+ int value, readcmd = 0;
+ int block, page;
+ /* Now we use page size operation */
+ int sectors = 4, count = 4;
+
+ /* Address translation */
+ switch (cmd) {
+ case ONENAND_CMD_UNLOCK:
+ case ONENAND_CMD_LOCK:
+ case ONENAND_CMD_LOCK_TIGHT:
+ block = -1;
+ page = -1;
+ break;
+
+ case ONENAND_CMD_ERASE:
+ case ONENAND_CMD_BUFFERRAM:
+ block = (int)(addr >> this->erase_shift);
+ page = -1;
+ break;
+
+ default:
+ block = (int)(addr >> this->erase_shift);
+ page = (int)(addr >> this->page_shift);
+ page &= this->page_mask;
+ break;
+ }
+
+ /* NOTE: The setting order of the registers is very important! */
+ if (cmd == ONENAND_CMD_BUFFERRAM) {
+ /* Select DataRAM for DDP */
+ value = onenand_bufferram_address(this->device_id, block);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS2);
+
+ /* Switch to the next data buffer */
+ ONENAND_SET_NEXT_BUFFERRAM(this);
+
+ return 0;
+ }
+
+ if (block != -1) {
+ /* Write 'DFS, FBA' of Flash */
+ value = onenand_block_address(this->device_id, block);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS1);
+ }
+
+ if (page != -1) {
+ int dataram;
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ case ONENAND_CMD_READOOB:
+ dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+ readcmd = 1;
+ break;
+
+ default:
+ dataram = ONENAND_CURRENT_BUFFERRAM(this);
+ break;
+ }
+
+ /* Write 'FPA, FSA' of Flash */
+ value = onenand_page_address(page, sectors);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS8);
+
+ /* Write 'BSA, BSC' of DataRAM */
+ value = onenand_buffer_address(dataram, sectors, count);
+ this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
+
+ if (readcmd) {
+ /* Select DataRAM for DDP */
+ value =
+ onenand_bufferram_address(this->device_id, block);
+ this->write_word(value,
+ this->base +
+ ONENAND_REG_START_ADDRESS2);
+ }
+ }
+
+ /* Interrupt clear */
+ this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
+ /* Write command */
+ this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
+
+ return 0;
+}
+
+/**
+ * onenand_wait - [DEFAULT] wait until the command is done
+ * @param mtd MTD device structure
+ * @param state state to select the max. timeout value
+ *
+ * Wait for command done. This applies to all OneNAND command
+ * Read can take up to 30us, erase up to 2ms and program up to 350us
+ * according to general OneNAND specs
+ */
+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int flags = ONENAND_INT_MASTER;
+ unsigned int interrupt = 0;
+ unsigned int ctrl, ecc;
+
+ while (1) {
+ interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
+ if (interrupt & flags)
+ break;
+ }
+
+ ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
+
+ if (ctrl & ONENAND_CTRL_ERROR) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_wait: controller error = 0x%04x\n", ctrl);
+ return -EAGAIN;
+ }
+
+ if (ctrl & ONENAND_CTRL_LOCK) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_wait: it's locked error = 0x%04x\n", ctrl);
+ return -EIO;
+ }
+
+ if (interrupt & ONENAND_INT_READ) {
+ ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
+ if (ecc & ONENAND_ECC_2BIT_ALL) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_wait: ECC error = 0x%04x\n", ecc);
+ return -EBADMSG;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @return offset given area
+ *
+ * Return BufferRAM offset given area
+ */
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ if (ONENAND_CURRENT_BUFFERRAM(this)) {
+ if (area == ONENAND_DATARAM)
+ return mtd->oobblock;
+ if (area == ONENAND_SPARERAM)
+ return mtd->oobsize;
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @param buffer the databuffer to put/get data
+ * @param offset offset to read from or write to
+ * @param count number of bytes to read/write
+ *
+ * Read the BufferRAM area
+ */
+static int onenand_read_bufferram(struct mtd_info *mtd, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ memcpy(buffer, bufferram + offset, count);
+
+ return 0;
+}
+
+/**
+ * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @param buffer the databuffer to put/get data
+ * @param offset offset to read from or write to
+ * @param count number of bytes to read/write
+ *
+ * Read the BufferRAM area with Sync. Burst Mode
+ */
+static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
+
+ memcpy(buffer, bufferram + offset, count);
+
+ this->mmcontrol(mtd, 0);
+
+ return 0;
+}
+
+/**
+ * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @param buffer the databuffer to put/get data
+ * @param offset offset to read from or write to
+ * @param count number of bytes to read/write
+ *
+ * Write the BufferRAM area
+ */
+static int onenand_write_bufferram(struct mtd_info *mtd, int area,
+ const unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ memcpy(bufferram + offset, buffer, count);
+
+ return 0;
+}
+
+/**
+ * onenand_check_bufferram - [GENERIC] Check BufferRAM information
+ * @param mtd MTD data structure
+ * @param addr address to check
+ * @return 1 if there are valid data, otherwise 0
+ *
+ * Check bufferram if there is data we required
+ */
+static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
+{
+ struct onenand_chip *this = mtd->priv;
+ int block, page;
+ int i;
+
+ block = (int)(addr >> this->erase_shift);
+ page = (int)(addr >> this->page_shift);
+ page &= this->page_mask;
+
+ i = ONENAND_CURRENT_BUFFERRAM(this);
+
+ /* Is there valid data? */
+ if (this->bufferram[i].block == block &&
+ this->bufferram[i].page == page && this->bufferram[i].valid)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * onenand_update_bufferram - [GENERIC] Update BufferRAM information
+ * @param mtd MTD data structure
+ * @param addr address to update
+ * @param valid valid flag
+ *
+ * Update BufferRAM information
+ */
+static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
+ int valid)
+{
+ struct onenand_chip *this = mtd->priv;
+ int block, page;
+ int i;
+
+ block = (int)(addr >> this->erase_shift);
+ page = (int)(addr >> this->page_shift);
+ page &= this->page_mask;
+
+ /* Invalidate BufferRAM */
+ for (i = 0; i < MAX_BUFFERRAM; i++) {
+ if (this->bufferram[i].block == block &&
+ this->bufferram[i].page == page)
+ this->bufferram[i].valid = 0;
+ }
+
+ /* Update BufferRAM */
+ i = ONENAND_CURRENT_BUFFERRAM(this);
+ this->bufferram[i].block = block;
+ this->bufferram[i].page = page;
+ this->bufferram[i].valid = valid;
+
+ return 0;
+}
+
+/**
+ * onenand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd MTD device structure
+ * @param new_state the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+static void onenand_get_device(struct mtd_info *mtd, int new_state)
+{
+ /* Do nothing */
+}
+
+/**
+ * onenand_release_device - [GENERIC] release chip
+ * @param mtd MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+static void onenand_release_device(struct mtd_info *mtd)
+{
+ /* Do nothing */
+}
+
+/**
+ * onenand_read_ecc - [MTD Interface] Read data with ECC
+ * @param mtd MTD device structure
+ * @param from offset to read from
+ * @param len number of bytes to read
+ * @param retlen pointer to variable to store the number of read bytes
+ * @param buf the databuffer to put data
+ * @param oob_buf filesystem supplied oob data buffer
+ * @param oobsel oob selection structure
+ *
+ * OneNAND read with ECC
+ */
+static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf,
+ u_char * oob_buf, struct nand_oobinfo *oobsel)
+{
+ struct onenand_chip *this = mtd->priv;
+ int read = 0, column;
+ int thislen;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n",
+ (unsigned int)from, (int)len);
+
+ /* Do not allow reads past end of device */
+ if ((from + len) > mtd->size) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_ecc: Attempt read beyond end of device\n");
+ *retlen = 0;
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_READING);
+
+ while (read < len) {
+ thislen = min_t(int, mtd->oobblock, len - read);
+
+ column = from & (mtd->oobblock - 1);
+ if (column + thislen > mtd->oobblock)
+ thislen = mtd->oobblock - column;
+
+ if (!onenand_check_bufferram(mtd, from)) {
+ this->command(mtd, ONENAND_CMD_READ, from,
+ mtd->oobblock);
+ ret = this->wait(mtd, FL_READING);
+ /* First copy data and check return value for ECC handling */
+ onenand_update_bufferram(mtd, from, 1);
+ }
+
+ this->read_bufferram(mtd, ONENAND_DATARAM, buf, column,
+ thislen);
+
+ read += thislen;
+ if (read == len)
+ break;
+
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_ecc: read failed = %d\n", ret);
+ break;
+ }
+
+ from += thislen;
+ buf += thislen;
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ /*
+ * Return success, if no ECC failures, else -EBADMSG
+ * fs driver will take care of that, because
+ * retlen == desired len and result == -EBADMSG
+ */
+ *retlen = read;
+ return ret;
+}
+
+/**
+ * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
+ * @param mtd MTD device structure
+ * @param from offset to read from
+ * @param len number of bytes to read
+ * @param retlen pointer to variable to store the number of read bytes
+ * @param buf the databuffer to put data
+ *
+ * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
+*/
+int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf)
+{
+ return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
+ * @param mtd MTD device structure
+ * @param from offset to read from
+ * @param len number of bytes to read
+ * @param retlen pointer to variable to store the number of read bytes
+ * @param buf the databuffer to put data
+ *
+ * OneNAND read out-of-band data from the spare area
+ */
+int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf)
+{
+ struct onenand_chip *this = mtd->priv;
+ int read = 0, thislen, column;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n",
+ (unsigned int)from, (int)len);
+
+ /* Initialize return length value */
+ *retlen = 0;
+
+ /* Do not allow reads past end of device */
+ if (unlikely((from + len) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_oob: Attempt read beyond end of device\n");
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_READING);
+
+ column = from & (mtd->oobsize - 1);
+
+ while (read < len) {
+ thislen = mtd->oobsize - column;
+ thislen = min_t(int, thislen, len);
+
+ this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+
+ onenand_update_bufferram(mtd, from, 0);
+
+ ret = this->wait(mtd, FL_READING);
+ /* First copy data and check return value for ECC handling */
+
+ this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column,
+ thislen);
+
+ read += thislen;
+ if (read == len)
+ break;
+
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_oob: read failed = %d\n", ret);
+ break;
+ }
+
+ buf += thislen;
+ /* Read more? */
+ if (read < len) {
+ /* Page size */
+ from += mtd->oobblock;
+ column = 0;
+ }
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ *retlen = read;
+ return ret;
+}
+
+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd MTD device structure
+ * @param buf the databuffer to verify
+ * @param block block address
+ * @param page page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char * buf,
+ loff_t addr, int block, int page)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *dataram0, *dataram1;
+ int ret = 0;
+
+ this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock);
+
+ ret = this->wait(mtd, FL_READING);
+ if (ret)
+ return ret;
+
+ onenand_update_bufferram(mtd, addr, 1);
+
+ /* Check, if the two dataram areas are same */
+ dataram0 = this->base + ONENAND_DATARAM;
+ dataram1 = dataram0 + mtd->oobblock;
+
+ if (memcmp(dataram0, dataram1, mtd->oobblock))
+ return -EBADMSG;
+
+ return 0;
+}
+#else
+#define onenand_verify_page(...) (0)
+#endif
+
+#define NOTALIGNED(x) ((x & (mtd->oobblock - 1)) != 0)
+
+/**
+ * onenand_write_ecc - [MTD Interface] OneNAND write with ECC
+ * @param mtd MTD device structure
+ * @param to offset to write to
+ * @param len number of bytes to write
+ * @param retlen pointer to variable to store the number of written bytes
+ * @param buf the data to write
+ * @param eccbuf filesystem supplied oob data buffer
+ * @param oobsel oob selection structure
+ *
+ * OneNAND write with ECC
+ */
+static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t * retlen, const u_char * buf,
+ u_char * eccbuf, struct nand_oobinfo *oobsel)
+{
+ struct onenand_chip *this = mtd->priv;
+ int written = 0;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n",
+ (unsigned int)to, (int)len);
+
+ /* Initialize retlen, in case of early exit */
+ *retlen = 0;
+
+ /* Do not allow writes past end of device */
+ if (unlikely((to + len) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: Attempt write to past end of device\n");
+ return -EINVAL;
+ }
+
+ /* Reject writes, which are not page aligned */
+ if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: Attempt to write not page aligned data\n");
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_WRITING);
+
+ /* Loop until all data write */
+ while (written < len) {
+ int thislen = min_t(int, mtd->oobblock, len - written);
+
+ this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+ this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen);
+ this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0,
+ mtd->oobsize);
+
+ this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+ onenand_update_bufferram(mtd, to, 1);
+
+ ret = this->wait(mtd, FL_WRITING);
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: write filaed %d\n", ret);
+ break;
+ }
+
+ written += thislen;
+
+ /* Only check verify write turn on */
+ ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: verify failed %d\n", ret);
+ break;
+ }
+
+ if (written == len)
+ break;
+
+ to += thislen;
+ buf += thislen;
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ *retlen = written;
+
+ return ret;
+}
+
+/**
+ * onenand_write - [MTD Interface] compability function for onenand_write_ecc
+ * @param mtd MTD device structure
+ * @param to offset to write to
+ * @param len number of bytes to write
+ * @param retlen pointer to variable to store the number of written bytes
+ * @param buf the data to write
+ *
+ * This function simply calls onenand_write_ecc
+ * with oob buffer and oobsel = NULL
+ */
+int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t * retlen, const u_char * buf)
+{
+ return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
+ * @param mtd MTD device structure
+ * @param to offset to write to
+ * @param len number of bytes to write
+ * @param retlen pointer to variable to store the number of written bytes
+ * @param buf the data to write
+ *
+ * OneNAND write out-of-band
+ */
+int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t * retlen, const u_char * buf)
+{
+ struct onenand_chip *this = mtd->priv;
+ int column, status;
+ int written = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n",
+ (unsigned int)to, (int)len);
+
+ /* Initialize retlen, in case of early exit */
+ *retlen = 0;
+
+ /* Do not allow writes past end of device */
+ if (unlikely((to + len) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_oob: Attempt write to past end of device\n");
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_WRITING);
+
+ /* Loop until all data write */
+ while (written < len) {
+ int thislen = min_t(int, mtd->oobsize, len - written);
+
+ column = to & (mtd->oobsize - 1);
+
+ this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
+
+ this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0,
+ mtd->oobsize);
+ this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column,
+ thislen);
+
+ this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+
+ onenand_update_bufferram(mtd, to, 0);
+
+ status = this->wait(mtd, FL_WRITING);
+ if (status)
+ break;
+
+ written += thislen;
+ if (written == len)
+ break;
+
+ to += thislen;
+ buf += thislen;
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ *retlen = written;
+
+ return 0;
+}
+
+/**
+ * onenand_erase - [MTD Interface] erase block(s)
+ * @param mtd MTD device structure
+ * @param instr erase instruction
+ *
+ * Erase one ore more blocks
+ */
+int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int block_size;
+ loff_t addr;
+ int len;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n",
+ (unsigned int)instr->addr, (unsigned int)instr->len);
+
+ block_size = (1 << this->erase_shift);
+
+ /* Start address must align on block boundary */
+ if (unlikely(instr->addr & (block_size - 1))) {
+ DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n");
+ return -EINVAL;
+ }
+
+ /* Length must align on block boundary */
+ if (unlikely(instr->len & (block_size - 1))) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Length not block aligned\n");
+ return -EINVAL;
+ }
+
+ /* Do not allow erase past end of device */
+ if (unlikely((instr->len + instr->addr) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Erase past end of device\n");
+ return -EINVAL;
+ }
+
+ instr->fail_addr = 0xffffffff;
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_ERASING);
+
+ /* Loop throught the pages */
+ len = instr->len;
+ addr = instr->addr;
+
+ instr->state = MTD_ERASING;
+
+ while (len) {
+
+ /* TODO Check badblock */
+
+ this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
+
+ ret = this->wait(mtd, FL_ERASING);
+ /* Check, if it is write protected */
+ if (ret) {
+ if (ret == -EPERM)
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Device is write protected!!!\n");
+ else
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Failed erase, block %d\n",
+ (unsigned)(addr >> this->erase_shift));
+ instr->state = MTD_ERASE_FAILED;
+ instr->fail_addr = addr;
+ goto erase_exit;
+ }
+
+ len -= block_size;
+ addr += block_size;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+
+ erase_exit:
+
+ ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+ /* Do call back function */
+ if (!ret)
+ mtd_erase_callback(instr);
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ return ret;
+}
+
+/**
+ * onenand_sync - [MTD Interface] sync
+ * @param mtd MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+void onenand_sync(struct mtd_info *mtd)
+{
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_SYNCING);
+
+ /* Release it and go back */
+ onenand_release_device(mtd);
+}
+
+/**
+ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @param mtd MTD device structure
+ * @param ofs offset relative to mtd start
+ */
+int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+ /*
+ * TODO
+ * 1. Bad block table (BBT)
+ * -> using NAND BBT to support JFFS2
+ * 2. Bad block management (BBM)
+ * -> bad block replace scheme
+ *
+ * Currently we do nothing
+ */
+ return 0;
+}
+
+/**
+ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @param mtd MTD device structure
+ * @param ofs offset relative to mtd start
+ */
+int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ /* see above */
+ return 0;
+}
+
+/**
+ * onenand_unlock - [MTD Interface] Unlock block(s)
+ * @param mtd MTD device structure
+ * @param ofs offset relative to mtd start
+ * @param len number of bytes to unlock
+ *
+ * Unlock one or more blocks
+ */
+int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+ struct onenand_chip *this = mtd->priv;
+ int start, end, block, value, status;
+
+ start = ofs >> this->erase_shift;
+ end = len >> this->erase_shift;
+
+ /* Continuous lock scheme */
+ if (this->options & ONENAND_CONT_LOCK) {
+ /* Set start block address */
+ this->write_word(start,
+ this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+ /* Set end block address */
+ this->write_word(end - 1,
+ this->base + ONENAND_REG_END_BLOCK_ADDRESS);
+ /* Write unlock command */
+ this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+ /* There's no return value */
+ this->wait(mtd, FL_UNLOCKING);
+
+ /* Sanity check */
+ while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+ & ONENAND_CTRL_ONGO)
+ continue;
+
+ /* Check lock status */
+ status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+ if (!(status & ONENAND_WP_US))
+ printk(KERN_ERR "wp status = 0x%x\n", status);
+
+ return 0;
+ }
+
+ /* Block lock scheme */
+ for (block = start; block < end; block++) {
+ /* Set start block address */
+ this->write_word(block,
+ this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+ /* Write unlock command */
+ this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+ /* There's no return value */
+ this->wait(mtd, FL_UNLOCKING);
+
+ /* Sanity check */
+ while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+ & ONENAND_CTRL_ONGO)
+ continue;
+
+ /* Set block address for read block status */
+ value = onenand_block_address(this->device_id, block);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS1);
+
+ /* Check lock status */
+ status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+ if (!(status & ONENAND_WP_US))
+ printk(KERN_ERR "block = %d, wp status = 0x%x\n",
+ block, status);
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_print_device_info - Print device ID
+ * @param device device ID
+ *
+ * Print device ID
+ */
+void onenand_print_device_info(int device, int verbose)
+{
+ int vcc, demuxed, ddp, density;
+
+ if (!verbose)
+ return;
+
+ vcc = device & ONENAND_DEVICE_VCC_MASK;
+ demuxed = device & ONENAND_DEVICE_IS_DEMUX;
+ ddp = device & ONENAND_DEVICE_IS_DDP;
+ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+ printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
+ demuxed ? "" : "Muxed ",
+ ddp ? "(DDP)" : "",
+ (16 << density), vcc ? "2.65/3.3" : "1.8", device);
+}
+
+static const struct onenand_manufacturers onenand_manuf_ids[] = {
+ {ONENAND_MFR_SAMSUNG, "Samsung"},
+ {ONENAND_MFR_UNKNOWN, "Unknown"}
+};
+
+/**
+ * onenand_check_maf - Check manufacturer ID
+ * @param manuf manufacturer ID
+ *
+ * Check manufacturer ID
+ */
+static int onenand_check_maf(int manuf)
+{
+ int i;
+
+ for (i = 0; onenand_manuf_ids[i].id; i++) {
+ if (manuf == onenand_manuf_ids[i].id)
+ break;
+ }
+
+#ifdef ONENAND_DEBUG
+ printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n",
+ onenand_manuf_ids[i].name, manuf);
+#endif
+
+ return (i != ONENAND_MFR_UNKNOWN);
+}
+
+/**
+ * onenand_probe - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd MTD device structure
+ *
+ * OneNAND detection method:
+ * Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ int bram_maf_id, bram_dev_id, maf_id, dev_id;
+ int version_id;
+ int density;
+
+ /* Send the command for reading device ID from BootRAM */
+ this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
+
+ /* Read manufacturer and device IDs from BootRAM */
+ bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
+ bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
+
+ /* Check manufacturer ID */
+ if (onenand_check_maf(bram_maf_id))
+ return -ENXIO;
+
+ /* Reset OneNAND to read default register values */
+ this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
+
+ {
+ int i;
+ for (i = 0; i < 10000; i++) ;
+ }
+
+ /* Read manufacturer and device IDs from Register */
+ maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
+ dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
+
+ /* Check OneNAND device */
+ if (maf_id != bram_maf_id || dev_id != bram_dev_id)
+ return -ENXIO;
+
+ /* Flash device information */
+ onenand_print_device_info(dev_id, 0);
+ this->device_id = dev_id;
+
+ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+ this->chipsize = (16 << density) << 20;
+
+ /* OneNAND page size & block size */
+ /* The data buffer size is equal to page size */
+ mtd->oobblock =
+ this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+ mtd->oobsize = mtd->oobblock >> 5;
+ /* Pagers per block is always 64 in OneNAND */
+ mtd->erasesize = mtd->oobblock << 6;
+
+ this->erase_shift = ffs(mtd->erasesize) - 1;
+ this->page_shift = ffs(mtd->oobblock) - 1;
+ this->ppb_shift = (this->erase_shift - this->page_shift);
+ this->page_mask = (mtd->erasesize / mtd->oobblock) - 1;
+
+ /* REVIST: Multichip handling */
+
+ mtd->size = this->chipsize;
+
+ /* Version ID */
+ version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
+#ifdef ONENAND_DEBUG
+ printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id);
+#endif
+
+ /* Lock scheme */
+ if (density <= ONENAND_DEVICE_DENSITY_512Mb &&
+ !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) {
+ printk(KERN_INFO "Lock scheme is Continues Lock\n");
+ this->options |= ONENAND_CONT_LOCK;
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
+ * @param mtd MTD device structure
+ * @param maxchips Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values.
+ */
+int onenand_scan(struct mtd_info *mtd, int maxchips)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ if (!this->read_word)
+ this->read_word = onenand_readw;
+ if (!this->write_word)
+ this->write_word = onenand_writew;
+
+ if (!this->command)
+ this->command = onenand_command;
+ if (!this->wait)
+ this->wait = onenand_wait;
+
+ if (!this->read_bufferram)
+ this->read_bufferram = onenand_read_bufferram;
+ if (!this->write_bufferram)
+ this->write_bufferram = onenand_write_bufferram;
+
+ if (onenand_probe(mtd))
+ return -ENXIO;
+
+ /* Set Sync. Burst Read after probing */
+ if (this->mmcontrol) {
+ printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
+ this->read_bufferram = onenand_sync_read_bufferram;
+ }
+
+ onenand_unlock(mtd, 0, mtd->size);
+
+ return onenand_default_bbt(mtd);
+}
+
+/**
+ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
+ * @param mtd MTD device structure
+ */
+void onenand_release(struct mtd_info *mtd)
+{
+}
+
+/*
+ * OneNAND initialization at U-Boot
+ */
+struct mtd_info onenand_mtd;
+struct onenand_chip onenand_chip;
+
+void onenand_init(void)
+{
+ memset(&onenand_mtd, 0, sizeof(struct mtd_info));
+ memset(&onenand_chip, 0, sizeof(struct onenand_chip));
+
+ onenand_chip.base = (void *)CFG_ONENAND_BASE;
+ onenand_mtd.priv = &onenand_chip;
+
+ onenand_scan(&onenand_mtd, 1);
+
+ puts("OneNAND: ");
+ print_size(onenand_mtd.size, "\n");
+}
+
+#endif /* CONFIG_CMD_ONENAND */
diff --git a/drivers/onenand/onenand_bbt.c b/drivers/onenand/onenand_bbt.c
new file mode 100644
index 0000000..5a610ee
--- /dev/null
+++ b/drivers/onenand/onenand_bbt.c
@@ -0,0 +1,265 @@
+/*
+ * linux/drivers/mtd/onenand/onenand_bbt.c
+ *
+ * Bad Block Table support for the OneNAND driver
+ *
+ * Copyright(c) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * TODO:
+ * Split BBT core and chip specific BBT.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <malloc.h>
+
+#include <asm/errno.h>
+
+/**
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @param buf the buffer to search
+ * @param len the length of buffer to search
+ * @param paglen the pagelength
+ * @param td search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers. Same as check_pattern, but
+ * no optional empty check and the pattern is expected to start
+ * at offset 0.
+ */
+static int check_short_pattern(uint8_t * buf, int len, int paglen,
+ struct nand_bbt_descr *td)
+{
+ int i;
+ uint8_t *p = buf;
+
+ /* Compare the pattern */
+ for (i = 0; i < td->len; i++) {
+ if (p[i] != td->pattern[i])
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * create_bbt - [GENERIC] Create a bad block table by scanning the device
+ * @param mtd MTD device structure
+ * @param buf temporary buffer
+ * @param bd descriptor for the good/bad block search pattern
+ * @param chip create the table for a specific chip, -1 read all chips.
+ * Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Create a bad block table by scanning the device
+ * for the given good/bad block identify pattern
+ */
+static int create_bbt(struct mtd_info *mtd, uint8_t * buf,
+ struct nand_bbt_descr *bd, int chip)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm = this->bbm;
+ int i, j, numblocks, len, scanlen;
+ int startblock;
+ loff_t from;
+ size_t readlen, ooblen;
+
+ printk(KERN_INFO "Scanning device for bad blocks\n");
+
+ len = 1;
+
+ /* We need only read few bytes from the OOB area */
+ scanlen = ooblen = 0;
+ readlen = bd->len;
+
+ /* chip == -1 case only */
+ /* Note that numblocks is 2 * (real numblocks) here;
+ * see i += 2 below as it makses shifting and masking less painful
+ */
+ numblocks = mtd->size >> (bbm->bbt_erase_shift - 1);
+ startblock = 0;
+ from = 0;
+
+ for (i = startblock; i < numblocks;) {
+ int ret;
+
+ for (j = 0; j < len; j++) {
+ size_t retlen;
+
+ /* No need to read pages fully,
+ * just read required OOB bytes */
+ ret = onenand_read_oob(mtd,
+ from + j * mtd->oobblock +
+ bd->offs, readlen, &retlen,
+ &buf[0]);
+
+ if (ret && ret != -EAGAIN) {
+ printk("ret = %d\n", ret);
+ return ret;
+ }
+
+ if (check_short_pattern
+ (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
+ bbm->bbt[i >> 3] |= 0x03 << (i & 0x6);
+ printk(KERN_WARNING
+ "Bad eraseblock %d at 0x%08x\n", i >> 1,
+ (unsigned int)from);
+ break;
+ }
+ }
+ i += 2;
+ from += (1 << bbm->bbt_erase_shift);
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_memory_bbt - [GENERIC] create a memory based bad block table
+ * @param mtd MTD device structure
+ * @param bd descriptor for the good/bad block search pattern
+ *
+ * The function creates a memory based bbt by scanning the device
+ * for manufacturer / software marked good / bad blocks
+ */
+static inline int onenand_memory_bbt(struct mtd_info *mtd,
+ struct nand_bbt_descr *bd)
+{
+ unsigned char data_buf[MAX_ONENAND_PAGESIZE];
+
+ bd->options &= ~NAND_BBT_SCANEMPTY;
+ return create_bbt(mtd, data_buf, bd, -1);
+}
+
+/**
+ * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad
+ * @param mtd MTD device structure
+ * @param offs offset in the device
+ * @param allowbbt allow access to bad block table region
+ */
+static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm = this->bbm;
+ int block;
+ uint8_t res;
+
+ /* Get block number * 2 */
+ block = (int)(offs >> (bbm->bbt_erase_shift - 1));
+ res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03;
+
+ DEBUG(MTD_DEBUG_LEVEL2,
+ "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+ (unsigned int)offs, block >> 1, res);
+
+ switch ((int)res) {
+ case 0x00:
+ return 0;
+ case 0x01:
+ return 1;
+ case 0x02:
+ return allowbbt ? 0 : 1;
+ }
+
+ return 1;
+}
+
+/**
+ * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s)
+ * @param mtd MTD device structure
+ * @param bd descriptor for the good/bad block search pattern
+ *
+ * The function checks, if a bad block table(s) is/are already
+ * available. If not it scans the device for manufacturer
+ * marked good / bad blocks and writes the bad block table(s) to
+ * the selected place.
+ *
+ * The bad block table memory is allocated here. It must be freed
+ * by calling the onenand_free_bbt function.
+ *
+ */
+int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm = this->bbm;
+ int len, ret = 0;
+
+ len = mtd->size >> (this->erase_shift + 2);
+ /* Allocate memory (2bit per block) */
+ bbm->bbt = malloc(len);
+ if (!bbm->bbt) {
+ printk(KERN_ERR "onenand_scan_bbt: Out of memory\n");
+ return -ENOMEM;
+ }
+ /* Clear the memory bad block table */
+ memset(bbm->bbt, 0x00, len);
+
+ /* Set the bad block position */
+ bbm->badblockpos = ONENAND_BADBLOCK_POS;
+
+ /* Set erase shift */
+ bbm->bbt_erase_shift = this->erase_shift;
+
+ if (!bbm->isbad_bbt)
+ bbm->isbad_bbt = onenand_isbad_bbt;
+
+ /* Scan the device to build a memory based bad block table */
+ if ((ret = onenand_memory_bbt(mtd, bd))) {
+ printk(KERN_ERR
+ "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n");
+ free(bbm->bbt);
+ bbm->bbt = NULL;
+ }
+
+ return ret;
+}
+
+/*
+ * Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks.
+ */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr largepage_memorybased = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern,
+};
+
+/**
+ * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device
+ * @param mtd MTD device structure
+ *
+ * This function selects the default bad block table
+ * support for the device and calls the onenand_scan_bbt function
+ */
+int onenand_default_bbt(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm;
+
+ this->bbm = malloc(sizeof(struct bbm_info));
+ if (!this->bbm)
+ return -ENOMEM;
+
+ bbm = this->bbm;
+
+ memset(bbm, 0, sizeof(struct bbm_info));
+
+ /* 1KB page has same configuration as 2KB page */
+ if (!bbm->badblock_pattern)
+ bbm->badblock_pattern = &largepage_memorybased;
+
+ return onenand_scan_bbt(mtd, bbm->badblock_pattern);
+}
+
+#endif /* CFG_CMD_ONENAND */
diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 2378553..acfda83 100644
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -28,6 +28,11 @@
#define PCIAUTO_IDE_MODE_MASK 0x05
+/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_PCI_CACHE_LINE_SIZE
+#define CFG_PCI_CACHE_LINE_SIZE 8
+#endif
+
/*
*
*/
@@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose,
}
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
+ CFG_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 0f5232a..7559e92 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -30,6 +30,8 @@
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
+DECLARE_GLOBAL_DATA_PTR;
+
void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
{
u32 cecr;
@@ -51,8 +53,6 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
uint qe_muram_alloc(uint size, uint align)
{
- DECLARE_GLOBAL_DATA_PTR;
-
uint retloc;
uint align_mask, off;
uint savebase;
@@ -158,8 +158,6 @@ void qe_put_snum(u8 snum)
void qe_init(uint qe_base)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* Init the QE IMMR base */
qe_immr = (qe_map_t *)qe_base;
@@ -204,7 +202,6 @@ void qe_assign_page(uint snum, uint para_ram_base)
int qe_set_brg(uint brg, uint rate)
{
- DECLARE_GLOBAL_DATA_PTR;
volatile uint *bp;
u32 divisor;
int div16 = 0;
diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c
index ed59abe..d678ab6 100644
--- a/drivers/serial_xuartlite.c
+++ b/drivers/serial_xuartlite.c
@@ -24,7 +24,7 @@
#include <config.h>
-#ifdef CONFIG_MICROBLAZE
+#ifdef CONFIG_XILINX_UARTLITE
#include <asm/serial_xuartlite.h>
diff --git a/drivers/sil680.c b/drivers/sil680.c
new file mode 100644
index 0000000..a6143df
--- /dev/null
+++ b/drivers/sil680.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2007
+ * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* sil680.c - ide support functions for the Sil0680A controller */
+
+/*
+ * The following parameters must be defined in the configuration file
+ * of the target board:
+ *
+ * #define CFG_IDE_SIL680
+ *
+ * #define CONFIG_PCI_PNP
+ * NOTE it may also be necessary to define this if the default of 8 is
+ * incorrect for the target board (e.g. the sequoia board requires 0).
+ * #define CFG_PCI_CACHE_LINE_SIZE 0
+ *
+ * #define CONFIG_CMD_IDE
+ * #undef CONFIG_IDE_8xx_DIRECT
+ * #undef CONFIG_IDE_LED
+ * #undef CONFIG_IDE_RESET
+ * #define CONFIG_IDE_PREINIT
+ * #define CFG_IDE_MAXBUS 2 - modify to suit
+ * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit
+ * #define CFG_ATA_BASE_ADDR 0
+ * #define CFG_ATA_IDE0_OFFSET 0
+ * #define CFG_ATA_IDE1_OFFSET 0
+ * #define CFG_ATA_DATA_OFFSET 0
+ * #define CFG_ATA_REG_OFFSET 0
+ * #define CFG_ATA_ALT_OFFSET 0x0004
+ *
+ * The mapping for PCI IO-space.
+ * NOTE this is the value for the sequoia board. Modify to suit.
+ * #define CFG_PCI0_IO_SPACE 0xE8000000
+ */
+
+#include <common.h>
+#if defined(CFG_IDE_SIL680)
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+
+int ide_preinit (void)
+{
+ int status;
+ pci_dev_t devbusfn;
+ int l;
+
+ status = 1;
+ for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+ ide_bus_offset[l] = -ATA_STATUS;
+ }
+ devbusfn = pci_find_device (0x1095, 0x0680, 0);
+ if (devbusfn != -1) {
+ status = 0;
+
+ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+ (u32 *) &ide_bus_offset[0]);
+ ide_bus_offset[0] &= 0xfffffff8;
+ ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
+ (u32 *) &ide_bus_offset[1]);
+ ide_bus_offset[1] &= 0xfffffff8;
+ ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+ /* init various things - taken from the Linux driver */
+ /* set PIO mode */
+ pci_write_config_byte(devbusfn, 0x80, 0x00);
+ pci_write_config_byte(devbusfn, 0x84, 0x00);
+ /* IDE0 */
+ pci_write_config_byte(devbusfn, 0xA1, 0x02);
+ pci_write_config_word(devbusfn, 0xA2, 0x328A);
+ pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
+ pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
+ pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
+ /* IDE1 */
+ pci_write_config_byte(devbusfn, 0xB1, 0x02);
+ pci_write_config_word(devbusfn, 0xB2, 0x328A);
+ pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
+ pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
+ pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
+ }
+ return (status);
+}
+
+void ide_set_reset (int flag) {
+ return;
+}
+
+#endif /* CFG_IDE_SIL680 */
diff --git a/drivers/tsec.c b/drivers/tsec.c
index 6bca4dc..4ff3339 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -1262,10 +1262,10 @@ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
case MIIM_LXT971_SR2_100HDX:
priv->speed = 100;
priv->duplexity = 0;
+ break;
default:
priv->speed = 100;
priv->duplexity = 1;
- break;
}
} else {
priv->speed = 0;
diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c
index 14984a5..7ddcab6 100644
--- a/drivers/usb_ohci.c
+++ b/drivers/usb_ohci.c
@@ -93,6 +93,7 @@
#ifdef CONFIG_PCI_OHCI
static struct pci_device_id ohci_pci_ids[] = {
{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
+ {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
/* Please add supported PCI OHCI controller ids here */
{0, 0}
};
diff --git a/drivers/usbdcore_mpc8xx.c b/drivers/usbdcore_mpc8xx.c
index e87284b..d4c4096 100644
--- a/drivers/usbdcore_mpc8xx.c
+++ b/drivers/usbdcore_mpc8xx.c
@@ -64,6 +64,8 @@
#include "usbdcore_mpc8xx.h"
#include "usbdcore_ep0.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define ERR(fmt, args...)\
serial_printf("ERROR : [%s] %s:%d: "fmt,\
__FILE__,__FUNCTION__,__LINE__, ##args)
@@ -1216,7 +1218,6 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr,
#elif defined(CFG_USB_BRGCLK)
/* This has been tested with brgclk == 50MHz */
- DECLARE_GLOBAL_DATA_PTR;
int divisor = 0;
if (gd->cpu_clk < 48000000L) {
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e8cb299..9b4da3a 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ;
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
-#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
-#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
-#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
-#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
-#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
-#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
-#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
- ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \
+ ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h
index 8b05d1a..58582a3 100644
--- a/include/asm-avr32/string.h
+++ b/include/asm-avr32/string.h
@@ -23,6 +23,6 @@
#define __ASM_AVR32_STRING_H
#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t n);
+extern void *memset(void *s, int c, __kernel_size_t n);
#endif /* __ASM_AVR32_STRING_H */
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
index 463a111..c42ad82 100644
--- a/include/asm-mips/string.h
+++ b/include/asm-mips/string.h
@@ -1,126 +1,31 @@
-/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
*/
-#ifndef __ASM_MIPS_STRING_H
-#define __ASM_MIPS_STRING_H
-
-#include <linux/config.h>
-
-#define __HAVE_ARCH_STRCPY
-extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
-{
- char *__xdest = __dest;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "addiu\t%1,1\n\t"
- "sb\t$1,(%0)\n\t"
- "bnez\t$1,1b\n\t"
- "addiu\t%0,1\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__dest), "=r" (__src)
- : "0" (__dest), "1" (__src)
- : "$1","memory");
-
- return __xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
-{
- char *__xdest = __dest;
-
- if (__n == 0)
- return __xdest;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "subu\t%2,1\n\t"
- "sb\t$1,(%0)\n\t"
- "beqz\t$1,2f\n\t"
- "addiu\t%0,1\n\t"
- "bnez\t%2,1b\n\t"
- "addiu\t%1,1\n"
- "2:\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__dest), "=r" (__src), "=r" (__n)
- : "0" (__dest), "1" (__src), "2" (__n)
- : "$1","memory");
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
- return __dest;
-}
-
-#define __HAVE_ARCH_STRCMP
-extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
-{
- int __res;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "lbu\t%2,(%0)\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "addiu\t%0,1\n\t"
- "bne\t$1,%2,2f\n\t"
- "addiu\t%1,1\n\t"
- "bnez\t%2,1b\n\t"
- "lbu\t%2,(%0)\n\t"
-#if defined(CONFIG_CPU_R3000)
- "nop\n\t"
-#endif
- "move\t%2,$1\n"
- "2:\tsubu\t%2,$1\n"
- "3:\t.set\tat\n\t"
- ".set\treorder"
- : "=r" (__cs), "=r" (__ct), "=r" (__res)
- : "0" (__cs), "1" (__ct)
- : "$1");
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
- return __res;
-}
+#undef __HAVE_ARCH_STRCPY
+extern char *strcpy(char *__dest, __const__ char *__src);
-#define __HAVE_ARCH_STRNCMP
-extern __inline__ int
-strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
-{
- int __res;
+#undef __HAVE_ARCH_STRNCPY
+extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t%3,(%0)\n\t"
- "beqz\t%2,2f\n\t"
- "lbu\t$1,(%1)\n\t"
- "subu\t%2,1\n\t"
- "bne\t$1,%3,3f\n\t"
- "addiu\t%0,1\n\t"
- "bnez\t%3,1b\n\t"
- "addiu\t%1,1\n"
- "2:\n\t"
-#if defined(CONFIG_CPU_R3000)
- "nop\n\t"
-#endif
- "move\t%3,$1\n"
- "3:\tsubu\t%3,$1\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
- : "0" (__cs), "1" (__ct), "2" (__count)
- : "$1");
+#undef __HAVE_ARCH_STRCMP
+extern int strcmp(__const__ char *__cs, __const__ char *__ct);
- return __res;
-}
+#undef __HAVE_ARCH_STRNCMP
+extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
@@ -131,27 +36,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-/* Don't build bcopy at all ... */
-#define __HAVE_ARCH_BCOPY
-
-#define __HAVE_ARCH_MEMSCAN
-extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
-{
- char *__end = (char *)__addr + __size;
-
- __asm__(".set\tpush\n\t"
- ".set\tnoat\n\t"
- ".set\treorder\n\t"
- "1:\tbeq\t%0,%1,2f\n\t"
- "addiu\t%0,1\n\t"
- "lb\t$1,-1(%0)\n\t"
- "bne\t$1,%4,1b\n"
- "2:\t.set\tpop"
- : "=r" (__addr), "=r" (__end)
- : "0" (__addr), "1" (__end), "r" (__c)
- : "$1");
-
- return __addr;
-}
-
-#endif /* __ASM_MIPS_STRING_H */
+#endif /* _ASM_STRING_H */
diff --git a/include/common.h b/include/common.h
index 9a5a0ab..aca281b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -275,7 +275,7 @@ void pciinfo (int, int);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
- void pcie_setup_hoses(void);
+ void pcie_setup_hoses(int busno);
#endif
#endif
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index 3d91e99..d7ef65d 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -59,6 +59,7 @@
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_ONENAND /* OneNAND support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_PCMCIA /* PCMCIA support */
#define CONFIG_CMD_PING /* ping support */
@@ -76,6 +77,6 @@
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_VFD /* VFD support (TRAB) */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */
+#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */
#endif /* _CONFIG_CMD_ALL_H */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 0718c85..9adbba9 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -158,7 +158,8 @@
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 62a2eaa..0321650 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -399,6 +399,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 1fd2b53..21cd9c1 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -165,7 +165,8 @@
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index a562b2f..f810af2 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -206,6 +206,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index c8ce259..a09c0e0 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -156,6 +156,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index 322158c..3b0ddb4 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -39,28 +39,44 @@
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 19200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* BOOTP options
*/
@@ -80,24 +96,32 @@
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index f8698b5..6fec075 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -40,18 +40,37 @@
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
@@ -79,11 +98,11 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
+
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
@@ -95,7 +114,14 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index ea8e61a..8967b3f 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -217,7 +217,8 @@
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index ed669c5..1ff7108 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -157,7 +157,8 @@
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index 27a5bc3..da54cef 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -234,6 +234,7 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index bdd92ba..4c16d22 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -178,7 +178,7 @@
#endif /* CONFIG_MPC5200 */
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5200@0"
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 0f97050..798ec0c 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -54,13 +54,12 @@
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
-#define CFG_ENV_SECT_SIZE 0x2000
-#define CFG_ENV_IS_IN_FLASH 1
#else
#define CFG_ENV_ADDR 0xffe04000
+#endif
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
-#endif
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*
* BOOTP options
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 4acbcd5..652210c 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -177,7 +177,8 @@
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index dd1decd..8a74c4f 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -429,6 +429,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#endif /* ENVIRONMENT_IN_EEPROM */
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index 516ec64..a98b4af 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -233,6 +233,7 @@
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 1e6e8c0..32e2285 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -235,6 +235,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index c08173b..d553404 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -188,7 +188,7 @@
#endif
#ifdef CONFIG_PCI
-#define CONFIG_CMD_CMD_PCI
+#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
@@ -238,13 +238,13 @@
"protect on FC000000 +${filesize}\0"
#endif
-#ifndef CONFIG_CAM5200
+#if defined(CONFIG_TQM5200)
#define CUSTOM_ENV_SETTINGS \
+ "hostname=tqm5200\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "bootfile_fdt=/tftpboot/tqm5200/uImage_fdt\0" \
"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
-#else
+#elif defined(CONFIG_CAM5200)
#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
@@ -252,11 +252,13 @@
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttyS0\0" \
- "kernel_addr=200000\0" \
- "fdt_addr=400000\0" \
- "hostname=tqm5200\0" \
"netdev=eth0\0" \
+ "console=ttyPSC0\0" \
+ "fdt_addr=FC0A0000\0" \
+ "kernel_addr=FC0C0000\0" \
+ "ramdisk_addr=FC300000\0" \
+ "kernel_addr_r=200000\0" \
+ "fdt_addr_r=400000\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -266,16 +268,20 @@
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
- "flash_self=run ramargs addip addcons;" \
+ "flash_self_old=sete console ttyS0; run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addcons;" \
+ "flash_self=run ramargs addip addcons;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr} ${bootfile};" \
- "run nfsargs addip addcons;bootm\0" \
- "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt};" \
- "tftp ${fdt_addr} ${fdt_file};setenv console ttyPSC0;" \
- "run nfsargs addip addcons;" \
+ "flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
+ "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "tftp ${fdt_addr_r} ${fdt_file}; " \
+ "run nfsargs addip addcons; " \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
ENV_UPDT \
@@ -408,11 +414,12 @@
# endif /* CFG_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
- "1408k(kernel)," \
+ "128k(dtb)," \
+ "2304k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"8m(misc)," \
- "16m(big-fs)"
+ "15m(big-fs)"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
@@ -701,7 +708,7 @@
* Open firmware flat tree support
*-----------------------------------------------------------------------
*/
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5200@0"
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 2bdcf2c..7a38010 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -205,6 +206,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 58bc5d3..e8b6a80 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -202,6 +203,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 74b16c7..beeca63 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -66,8 +66,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -192,6 +193,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index e3936c3..d5609c1 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -64,8 +64,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -191,6 +192,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index ae22b77..e35b5b2 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -196,6 +197,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 5d54f87..cd5212e 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -231,6 +232,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 2f23c50..6dbd392 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -449,7 +449,7 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
+ "bootfile="CFG_BOOTFILE_PATH"\0" \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 40c0940..d5838db 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -199,6 +200,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 481e3d0..684b86f 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -198,6 +199,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index bb3b1cc..f09d3d1 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -72,8 +72,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -200,6 +201,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index d687d08..039aa3a 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -72,8 +72,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -201,6 +202,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index ff00c13..0d77891 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -81,8 +81,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -241,6 +242,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 3880ec7..14848ab 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -163,7 +163,8 @@
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 22eac1b..bb1efdf 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -235,6 +235,14 @@
#endif
/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
+
+/*
* Ethernet configuration
*/
#define CONFIG_MPC512x_FEC 1
@@ -275,6 +283,7 @@
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index e1d8f74..1809fc5 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -39,8 +39,10 @@
#define CFG_HZ 1000
/*
- * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
- * frequency and the peripherals to run at 1/4 the PLL frequency.
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
*/
#define CONFIG_PLL 1
#define CFG_POWER_MANAGER 1
@@ -48,9 +50,25 @@
#define CFG_PLL0_DIV 1
#define CFG_PLL0_MUL 7
#define CFG_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
#define CFG_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
#define CFG_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
#define CFG_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
#define CFG_CLKDIV_PBB 1
/*
@@ -78,7 +96,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
- "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
+ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
#define CONFIG_BOOTCOMMAND \
"fsload; bootm $(fileaddr)"
@@ -87,7 +105,7 @@
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
-#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTDELAY 1
#define CONFIG_AUTOBOOT 1
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
@@ -103,8 +121,8 @@
* generated and assigned to the environment variables "ethaddr" and
* "eth1addr".
*/
-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
+#define CONFIG_ETHADDR 6a:87:71:14:cd:cb
+#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
@@ -182,13 +200,8 @@
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START \
- ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
-#define CFG_MEMTEST_END \
- ({ \
- DECLARE_GLOBAL_DATA_PTR; \
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
- })
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index 85c2b96..a869364 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -171,8 +171,9 @@
#define CFG_ENV_IS_IN_FLASH 1
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
-#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 2f64ec2..2547afb 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -406,6 +406,7 @@
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 404e88a..3821ebc 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -125,6 +125,8 @@
#define CFG_ENV_IS_IN_FLASH
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 4070ab9..b7100e9 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -145,7 +145,7 @@
#if 0
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5200@0"
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index b6d0f51..7908e5a 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -66,11 +66,11 @@
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -201,6 +201,7 @@
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -322,7 +323,7 @@
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index be48324..00c34d5 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -200,12 +200,13 @@
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
+ "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
+ "flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/lwmon5/uImage\0" \
"kernel_addr=FC000000\0" \
@@ -338,7 +339,12 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#if 0
+/*
+ * ToDo: Watchdog is not test fully, so exclude it for now
+ */
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+#endif
/*
* For booting Linux, the board info and command line data
@@ -472,7 +478,7 @@
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 7eeae70..b320438 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -1,7 +1,7 @@
/*
- * (C) Copyright 2007 Czech Technical University.
+ * (C) Copyright 2007 Michal Simek
*
- * Michal SIMEK <monstr@seznam.cz>
+ * Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -32,6 +32,7 @@
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
+#define CONFIG_XILINX_UARTLITE
#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
@@ -58,6 +59,7 @@
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
/* FSL */
#define CFG_FSL_2
@@ -86,7 +88,7 @@
* 0x11FB_F000 CFG_MONITOR_BASE
* MONITOR_CODE 256kB Env
* 0x13FF_F000 CFG_GBL_DATA_OFFSET
- * GLOBAL_DATA 4kB bd, gd
+ * GLOBAL_DATA 4kB bd, gd
* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/
@@ -99,7 +101,7 @@
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
/* start of global data */
-#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
/* monitor code */
#define SIZE 0x40000
@@ -145,6 +147,16 @@
#define CFG_FLASH_PROTECTION /* hardware flash protection */
#endif /* !FLASH */
+/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
+ #define CONFIG_SYSTEMACE
+ /* #define DEBUG_SYSTEMACE */
+ #define SYSTEMACE_CONFIG_FPGA
+ #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+ #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+ #define CONFIG_DOS_PARTITION
+#endif
+
/*
* BOOTP options
*/
@@ -153,28 +165,21 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_AUTOSCRIPT
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MFSL
-#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
+
+#if defined(CONFIG_SYSTEMACE)
+ #define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_FAT
+#endif
#if defined(FLASH)
#define CONFIG_CMD_ECHO
@@ -186,6 +191,8 @@
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#endif
+#else
+ #undef CONFIG_CMD_FLASH
#endif
#if defined(CONFIG_CMD_JFFS2)
@@ -210,24 +217,16 @@
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
+#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
-#define CONFIG_SERVERIP 192.168.0.5
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.5
+#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
/* architecture dependent code */
#define CFG_USR_EXCEP /* user exception */
#define CFG_HZ 1000
-/* system ace */
-#define CONFIG_SYSTEMACE
-/* #define DEBUG_SYSTEMACE */
-#define SYSTEMACE_CONFIG_FPGA
-#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 82827c6..9a21632 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -417,7 +417,7 @@ extern void __led_set(led_id_t id, int state);
#define CFG_RESET_ADDRESS 0xfff00100
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5200@0"
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 824a812..600f98c 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -400,7 +400,8 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
@@ -449,6 +450,8 @@
#define CFG_EBC_PB2AP 0x24814580
#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
+#define CFG_BCSR5_PCI66EN 0x80
+
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index b4ab9ad..2efc8f1 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -31,14 +31,9 @@
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MII
-/* #define MII_DEBUG */
-/* #define CONFIG_FEC_ENET */
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
-/* #define CONFIG_FEC2_PHY_NORXERR */
-/* #define CFG_DISCOVER_PHY */
-/* #define CONFIG_PHY_ADDR 0x1 */
#define CONFIG_FEC2_PHY 1
#define CONFIG_BAUDRATE 19200
@@ -100,14 +95,12 @@
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
-#undef CONFIG_CMD_NET
-
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index f32ff67..c6e7953 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -189,20 +189,21 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
+/*
+ * I2C
+ */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#if 0
-#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
-#else
-/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
-#endif
#define CFG_I2C_OFFSET 0x3000
+/* I2C RTC */
+#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
/* I2C EEPROM. AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
@@ -230,7 +231,7 @@
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
-
+#define CONFIG_MPC85XX_PCI2 1
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
@@ -341,8 +342,13 @@
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
index 08ac9cb..020ed02 100644
--- a/include/configs/suzaku.h
+++ b/include/configs/suzaku.h
@@ -48,6 +48,7 @@
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024))
+#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 115200 }
@@ -55,21 +56,16 @@
#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_MISC
#define CFG_UART1_BASE (0xFFFF2000)
#define CONFIG_SERIAL_BASE CFG_UART1_BASE
@@ -108,4 +104,7 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define XILINX_CLOCK_FREQ 50000000
+#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
+
#endif /* __CONFIG_H */
diff --git a/include/configs/trab.h b/include/configs/trab.h
index dbccea2..b9088a8 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -419,6 +419,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/* Initial value of the on-board touch screen brightness */
#define CFG_BRIGHTNESS 0x20
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
new file mode 100644
index 0000000..84998d4
--- /dev/null
+++ b/include/configs/trizepsiv.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
+
+#define CONFIG_MMC 1
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
+#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
+#define CONFIG_STUART 1 /* we use STUART on Conxs */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_SERVERIP 192.168.1.99
+#define CONFIG_BOOTCOMMAND "run boot_flash"
+#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
+ " rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "program_boot_mmc=" \
+ "mw.b 0xa0010000 0xff 0x20000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 u-boot.bin; " \
+ "then " \
+ "protect off 0x0 0x1ffff; " \
+ "erase 0x0 0x1ffff; " \
+ "cp.b 0xa0010000 0x0 0x20000; " \
+ "fi\0" \
+ "program_uzImage_mmc=" \
+ "mw.b 0xa0010000 0xff 0x180000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 uzImage; " \
+ "then " \
+ "protect off 0x40000 0x1bffff; " \
+ "erase 0x40000 0x1bffff; " \
+ "cp.b 0xa0010000 0x40000 0x180000; " \
+ "fi\0" \
+ "program_ramdisk_mmc=" \
+ "mw.b 0xa0010000 0xff 0x500000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 ramdisk.gz; " \
+ "then " \
+ "protect off 0x1c0000 0x6bffff; " \
+ "erase 0x1c0000 0x6bffff; " \
+ "cp.b 0xa0010000 0x1c0000 0x500000; " \
+ "fi\0" \
+ "boot_mmc=" \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0030000 uzImage && " \
+ "fatload mmc 0 0xa0800000 ramdisk.gz; " \
+ "then " \
+ "bootm 0xa0030000; " \
+ "fi\0" \
+ "boot_flash=" \
+ "cp.b 0x1c0000 0xa0800000 0x500000; " \
+ "bootm 0x40000\0" \
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+/* #define CONFIG_INITRD_TAG 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE 0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00018000
+#define CFG_GPSR1_VAL 0x00000000
+#define CFG_GPSR2_VAL 0x400dc000
+#define CFG_GPSR3_VAL 0x00000000
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPCR3_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x00018000
+#define CFG_GPDR1_VAL 0x00028801
+#define CFG_GPDR2_VAL 0x520dc000
+#define CFG_GPDR3_VAL 0x0001E000
+#define CFG_GAFR0_L_VAL 0x801c0000
+#define CFG_GAFR0_U_VAL 0x00000013
+#define CFG_GAFR1_L_VAL 0x6990100A
+#define CFG_GAFR1_U_VAL 0x00000008
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x010900F2
+#define CFG_GAFR3_L_VAL 0x54000003
+#define CFG_GAFR3_U_VAL 0x00002401
+#define CFG_GRER0_VAL 0x00000000
+#define CFG_GRER1_VAL 0x00000000
+#define CFG_GRER2_VAL 0x00000000
+#define CFG_GRER3_VAL 0x00000000
+#define CFG_GFER0_VAL 0x00000000
+#define CFG_GFER1_VAL 0x00000000
+#define CFG_GFER2_VAL 0x00000000
+#define CFG_GFER3_VAL 0x00000020
+
+
+#define CFG_PSSR_VAL 0x20 /* CHECK */
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN 0x01FFFFFF /* CHECK */
+#define CFG_CCCR 0x02000290 /* 520Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL 0x4df84df0
+#define CFG_MSC1_VAL 0x7ff87ff4
+#define CFG_MSC2_VAL 0xa26936d4
+#define CFG_MDCNFG_VAL 0x880009C9
+#define CFG_MDREFR_VAL 0x20ca201e
+#define CFG_MDMRS_VAL 0x00220022
+
+#define CFG_FLYCNFG_VAL 0x00000000
+#define CFG_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000001
+#define CFG_MCMEM0_VAL 0x00004204
+#define CFG_MCMEM1_VAL 0x00010204
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00008407
+#define CFG_MCIO1_VAL 0x0000c108
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
+/* #define CONFIG_DM9000_USE_8BIT */
+/* #define CONFIG_DM9000_USE_16BIT */
+#define CONFIG_DM9000_USE_32BIT
+
+#define CONFIG_USB_OHCI_NEW 1
+#define CFG_USB_OHCI_BOARD_INIT 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
+#define CFG_USB_OHCI_REGS_BASE 0x4C000000
+#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
+#define CONFIG_USB_STORAGE 1
+#define CFG_USB_OHCI_CPU_INIT 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_MONITOR_BASE 0
+#define CFG_MONITOR_LEN 0x40000
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index 561a8bc..edae6f4 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -207,6 +207,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index 35001d7..c9320c2 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007 Czech Technical University.
+ * (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
@@ -31,6 +31,7 @@
#define CONFIG_XUPV2P 1
/* uart */
+#define CONFIG_XILINX_UARTLITE
#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
@@ -48,11 +49,13 @@
* U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
* jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
*/
-#define CFG_RESET_ADDRESS 0x36000000
+/* #define CFG_RESET_ADDRESS 0x36000000 */
/* gpio */
+#ifdef XILINX_GPIO_BASEADDR
#define CFG_GPIO_0 1
#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
+#endif
/* interrupt controller */
#define CFG_INTC_0 1
@@ -65,6 +68,7 @@
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
/*
* memory layout - Example
@@ -119,7 +123,6 @@
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
-
/*
* BOOTP options
*/
@@ -128,29 +131,23 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
+#ifdef XILINX_SYSACE_BASEADDR
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#endif
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
@@ -162,7 +159,7 @@
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
-#define CONFIG_HOSTNAME "ml401"
+#define CONFIG_HOSTNAME "xupv2p"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.5
@@ -178,11 +175,13 @@
"echo"
/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
#define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define SYSTEMACE_CONFIG_FPGA
#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
#define CONFIG_DOS_PARTITION
+#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 6a5b7f1..35bce4a 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -359,6 +359,8 @@
#define CFG_EBC_PB2AP 0x04814500
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
+#define CFG_BCSR5_PCI66EN 0x80
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 906f046..74033b4 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -68,11 +68,11 @@
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -182,6 +182,7 @@
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -297,7 +298,7 @@
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
diff --git a/include/image.h b/include/image.h
index 2f575fd..432fa22 100644
--- a/include/image.h
+++ b/include/image.h
@@ -77,6 +77,7 @@
#define IH_CPU_NIOS2 15 /* Nios-II */
#define IH_CPU_BLACKFIN 16 /* Blackfin */
#define IH_CPU_AVR32 17 /* AVR32 */
+#define IH_CPU_ST200 18 /* STMicroelectronics ST200 */
/*
* Image Types
diff --git a/include/libfdt.h b/include/libfdt.h
index 340e89d..38c65a9 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -140,6 +140,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
})
#define fdt_setprop_string(fdt, nodeoffset, name, str) \
fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create);
int fdt_delprop(void *fdt, int nodeoffset, const char *name);
int fdt_add_subnode_namelen(void *fdt, int parentoffset,
const char *name, int namelen);
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
new file mode 100644
index 0000000..f194cf1
--- /dev/null
+++ b/include/linux/mtd/bbm.h
@@ -0,0 +1,127 @@
+/*
+ * linux/include/linux/mtd/bbm.h
+ *
+ * NAND family Bad Block Management (BBM) header file
+ * - Bad Block Table (BBT) implementation
+ *
+ * Copyright (c) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Copyright (c) 2000-2005
+ * Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#ifndef NAND_MAX_CHIPS
+#define NAND_MAX_CHIPS 8
+#endif
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @param options options for this descriptor
+ * @param pages the page(s) where we find the bbt, used with
+ * option BBT_ABSPAGE when bbt is searched,
+ * then we store the found bbts pages here.
+ * Its an array and supports up to 8 chips now
+ * @param offs offset of the pattern in the oob area of the page
+ * @param veroffs offset of the bbt version counter in the oob are of the page
+ * @param version version read from the bbt page during scan
+ * @param len length of the pattern, if 0 no pattern check is performed
+ * @param maxblocks maximum number of blocks to search for a bbt. This number of
+ * blocks is reserved at the end of the device
+ * where the tables are written.
+ * @param reserved_block_code if non-0, this pattern denotes a reserved
+ * (rather than bad) block in the stored bbt
+ * @param pattern pattern to identify bad block table or factory marked
+ * good / bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+ int options;
+ int pages[NAND_MAX_CHIPS];
+ int offs;
+ int veroffs;
+ uint8_t version[NAND_MAX_CHIPS];
+ int len;
+ int maxblocks;
+ int reserved_block_code;
+ uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK 0x0000000F
+#define NAND_BBT_1BIT 0x00000001
+#define NAND_BBT_2BIT 0x00000002
+#define NAND_BBT_4BIT 0x00000004
+#define NAND_BBT_8BIT 0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK 0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE 0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH 0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP 0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION 0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE 0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES 0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY 0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE 0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT 0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE 0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS 4
+
+/*
+ * Constants for oob configuration
+ */
+#define ONENAND_BADBLOCK_POS 0
+
+/**
+ * struct bbt_info - [GENERIC] Bad Block Table data structure
+ * @param bbt_erase_shift [INTERN] number of address bits in a bbt entry
+ * @param badblockpos [INTERN] position of the bad block marker in the oob area
+ * @param bbt [INTERN] bad block table pointer
+ * @param badblock_pattern [REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @param priv [OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+ int bbt_erase_shift;
+ int badblockpos;
+ int options;
+
+ uint8_t *bbt;
+
+ int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
+
+ /* TODO Add more NAND specific fileds */
+ struct nand_bbt_descr *badblock_pattern;
+
+ void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt (struct mtd_info *mtd);
+
+#endif /* __LINUX_MTD_BBM_H */
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
new file mode 100644
index 0000000..4b0c2df
--- /dev/null
+++ b/include/linux/mtd/onenand.h
@@ -0,0 +1,143 @@
+/*
+ * linux/include/linux/mtd/onenand.h
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/mtd/onenand_regs.h>
+
+/* Note: The header order is impoertant */
+#include <onenand_uboot.h>
+
+#include <linux/mtd/bbm.h>
+
+#define MAX_BUFFERRAM 2
+#define MAX_ONENAND_PAGESIZE (2048 + 64)
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release (struct mtd_info *mtd);
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+ FL_READY,
+ FL_READING,
+ FL_WRITING,
+ FL_ERASING,
+ FL_SYNCING,
+ FL_UNLOCKING,
+ FL_LOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param block block address in BufferRAM
+ * @param page page address in BufferRAM
+ * @param valid valid flag
+ */
+struct onenand_bufferram {
+ int block;
+ int page;
+ int valid;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base [BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize [INTERN] the size of one chip for multichip arrays
+ * @param device_id [INTERN] device ID
+ * @param verstion_id [INTERN] version ID
+ * @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift [INTERN] number of address bits in a block
+ * @param page_shift [INTERN] number of address bits in a page
+ * @param ppb_shift [INTERN] number of address bits in a pages per block
+ * @param page_mask [INTERN] a page per block mask
+ * @param bufferam_index [INTERN] BufferRAM index
+ * @param bufferam [INTERN] BufferRAM info
+ * @param readw [REPLACEABLE] hardware specific function for read short
+ * @param writew [REPLACEABLE] hardware specific function for write short
+ * @param command [REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait [REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock [INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq [INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state [INTERN] the current state of the OneNAND device
+ * @param autooob [REPLACEABLE] the default (auto)placement scheme
+ * @param priv [OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+ void __iomem *base;
+ unsigned int chipsize;
+ unsigned int device_id;
+ unsigned int options;
+
+ unsigned int erase_shift;
+ unsigned int page_shift;
+ unsigned int ppb_shift; /* Pages per block shift */
+ unsigned int page_mask;
+
+ unsigned int bufferram_index;
+ struct onenand_bufferram bufferram[MAX_BUFFERRAM];
+
+ int (*command) (struct mtd_info * mtd, int cmd, loff_t address,
+ size_t len);
+ int (*wait) (struct mtd_info * mtd, int state);
+ int (*read_bufferram) (struct mtd_info * mtd, int area,
+ unsigned char *buffer, int offset, size_t count);
+ int (*write_bufferram) (struct mtd_info * mtd, int area,
+ const unsigned char *buffer, int offset,
+ size_t count);
+ unsigned short (*read_word) (void __iomem * addr);
+ void (*write_word) (unsigned short value, void __iomem * addr);
+ void (*mmcontrol) (struct mtd_info * mtd, int sync_read);
+
+ spinlock_t chip_lock;
+ wait_queue_head_t wq;
+ onenand_state_t state;
+
+ struct nand_oobinfo *autooob;
+
+ void *bbm;
+
+ void *priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this) (this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK (0x0001)
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG 0xec
+#define ONENAND_MFR_UNKNOWN 0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name: Manufacturer name
+ * @param id: manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+ int id;
+ char *name;
+};
+
+#endif /* __LINUX_MTD_ONENAND_H */
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
new file mode 100644
index 0000000..c8a9f3e
--- /dev/null
+++ b/include/linux/mtd/onenand_regs.h
@@ -0,0 +1,181 @@
+/*
+ * linux/include/linux/mtd/onenand_regs.h
+ *
+ * OneNAND Register header file
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x) ((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
+#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
+#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT (4)
+#define ONENAND_DEVICE_IS_DDP (1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
+#define ONENAND_DEVICE_VCC_MASK (0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT (8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT (15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK (0x3f)
+#define ONENAND_FPA_SHIFT (2)
+#define ONENAND_FSA_MASK (0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK (0x03)
+#define ONENAND_BSA_SHIFT (8)
+#define ONENAND_BSA_BOOTRAM (0 << 2)
+#define ONENAND_BSA_DATARAM0 (2 << 2)
+#define ONENAND_BSA_DATARAM1 (3 << 2)
+#define ONENAND_BSC_MASK (0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ (0x00)
+#define ONENAND_CMD_READOOB (0x13)
+#define ONENAND_CMD_PROG (0x80)
+#define ONENAND_CMD_PROGOOB (0x1A)
+#define ONENAND_CMD_UNLOCK (0x23)
+#define ONENAND_CMD_LOCK (0x2A)
+#define ONENAND_CMD_LOCK_TIGHT (0x2C)
+#define ONENAND_CMD_ERASE (0x94)
+#define ONENAND_CMD_RESET (0xF0)
+#define ONENAND_CMD_READID (0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM (0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
+#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
+#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
+#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
+#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
+#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT (9)
+#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
+#define ONENAND_SYS_CFG1_RDY (1 << 7)
+#define ONENAND_SYS_CFG1_INT (1 << 6)
+#define ONENAND_SYS_CFG1_IOBE (1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO (1 << 15)
+#define ONENAND_CTRL_LOCK (1 << 14)
+#define ONENAND_CTRL_LOAD (1 << 13)
+#define ONENAND_CTRL_PROGRAM (1 << 12)
+#define ONENAND_CTRL_ERASE (1 << 11)
+#define ONENAND_CTRL_ERROR (1 << 10)
+#define ONENAND_CTRL_RSTB (1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER (1 << 15)
+#define ONENAND_INT_READ (1 << 7)
+#define ONENAND_INT_WRITE (1 << 6)
+#define ONENAND_INT_ERASE (1 << 5)
+#define ONENAND_INT_RESET (1 << 4)
+#define ONENAND_INT_CLEAR (0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US (1 << 2)
+#define ONENAND_WP_LS (1 << 1)
+#define ONENAND_WP_LTS (1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT (1 << 0)
+#define ONENAND_ECC_2BIT (1 << 1)
+#define ONENAND_ECC_2BIT_ALL (0xAAAA)
+
+#endif /* __ONENAND_REG_H */
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
new file mode 100644
index 0000000..bd1831e
--- /dev/null
+++ b/include/onenand_uboot.h
@@ -0,0 +1,39 @@
+/*
+ * Header file for OneNAND support for U-Boot
+ *
+ * Adaptation from kernel to U-Boot
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_ONENAND_H
+#define __UBOOT_ONENAND_H
+
+struct kvec {
+ void *iov_base;
+ size_t iov_len;
+};
+
+typedef int spinlock_t;
+typedef int wait_queue_head_t;
+
+/* Functions */
+extern void onenand_init(void);
+extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf);
+extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf);
+extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, const u_char * buf);
+extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
+
+extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
+
+extern void onenand_print_device_info(int device, int verbose);
+
+#endif /* __UBOOT_ONENAND_H */
diff --git a/include/serial.h b/include/serial.h
index f7412fd..30bfde3 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -36,6 +36,10 @@ extern struct serial_device eserial4_device;
#endif
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
extern void serial_initialize(void);
extern void serial_devices_init(void);
extern int serial_assign(char * name);
diff --git a/include/status_led.h b/include/status_led.h
index a646814..d12bb67 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -383,6 +383,27 @@ extern void __led_set (led_id_t mask, int state);
# include <asm/status_led.h>
#endif
+/*
+ * Coloured LEDs API
+ */
+#ifndef __ASSEMBLY__
+extern void coloured_LED_init (void);
+extern void red_LED_on(void);
+extern void red_LED_off(void);
+extern void green_LED_on(void);
+extern void green_LED_off(void);
+extern void yellow_LED_on(void);
+extern void yellow_LED_off(void);
+#else
+ .extern LED_init
+ .extern red_LED_on
+ .extern red_LED_off
+ .extern yellow_LED_on
+ .extern yellow_LED_off
+ .extern green_LED_on
+ .extern green_LED_off
+#endif
+
#endif /* CONFIG_STATUS_LED */
#endif /* _STATUS_LED_H_ */
diff --git a/lib_arm/board.c b/lib_arm/board.c
index d37e5da..7e97f13 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -58,6 +58,10 @@ DECLARE_GLOBAL_DATA_PTR;
void nand_init (void);
#endif
+#if defined(CONFIG_CMD_ONENAND)
+void onenand_init(void);
+#endif
+
ulong monitor_flash_len;
#ifdef CONFIG_HAS_DATAFLASH
@@ -112,6 +116,26 @@ void *sbrk (ptrdiff_t increment)
}
/************************************************************************
+ * Coloured LED functionality
+ ************************************************************************
+ * May be supplied by boards if desired
+ */
+void inline __coloured_LED_init (void) {}
+void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
+void inline __red_LED_on (void) {}
+void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
+void inline __red_LED_off(void) {}
+void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
+void inline __green_LED_on(void) {}
+void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
+void inline __green_LED_off(void) {}
+void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off")));
+void inline __yellow_LED_on(void) {}
+void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on")));
+void inline __yellow_LED_off(void) {}
+void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off")));
+
+/************************************************************************
* Init Utilities *
************************************************************************
* Some of this code should be moved into the core functions,
@@ -185,7 +209,6 @@ static void display_flash_config (ulong size)
}
#endif /* CFG_NO_FLASH */
-
/*
* Breathe some life into the board...
*
@@ -301,6 +324,10 @@ void start_armboot (void)
nand_init(); /* go init the NAND */
#endif
+#if defined(CONFIG_CMD_ONENAND)
+ onenand_init();
+#endif
+
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
@@ -314,6 +341,10 @@ void start_armboot (void)
drv_vfd_init();
#endif /* CONFIG_VFD */
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
+
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
diff --git a/lib_avr32/board.c b/lib_avr32/board.c
index 8b9ca38..11d864f 100644
--- a/lib_avr32/board.c
+++ b/lib_avr32/board.c
@@ -310,10 +310,20 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
malloc_bin_reloc();
dma_alloc_init();
board_init_info();
- flash_init();
+
+ bd->bi_flashstart = 0;
+ bd->bi_flashsize = 0;
+ bd->bi_flashoffset = 0;
+
+#ifndef CFG_NO_FLASH
+ bd->bi_flashstart = CFG_FLASH_BASE;
+ bd->bi_flashsize = flash_init();
+ bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
if (bd->bi_flashsize)
display_flash_config();
+#endif
+
if (bd->bi_dram[0].size)
display_dram_config();
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index 36a969e..7c9990f 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c
@@ -42,6 +42,8 @@
int post_flag;
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CFG_NO_FLASH
extern flash_info_t flash_info[];
#endif
@@ -126,8 +128,6 @@ static void display_flash_config(ulong size)
static int init_baudrate(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
char tmp[64];
int i = getenv_r("baudrate", tmp, sizeof(tmp));
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
@@ -139,7 +139,6 @@ static int init_baudrate(void)
#ifdef DEBUG
static void display_global_data(void)
{
- DECLARE_GLOBAL_DATA_PTR;
bd_t *bd;
bd = gd->bd;
printf("--flags:%x\n", gd->flags);
@@ -256,7 +255,6 @@ void init_cplbtables(void)
void board_init_f(ulong bootflag)
{
- DECLARE_GLOBAL_DATA_PTR;
ulong addr;
bd_t *bd;
int i;
@@ -325,7 +323,6 @@ static int init_func_i2c(void)
void board_init_r(gd_t * id, ulong dest_addr)
{
- DECLARE_GLOBAL_DATA_PTR;
ulong size;
extern void malloc_bin_reloc(void);
char *s, *e;
diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c
index 7c9478d..3c4d5c5 100644
--- a/lib_blackfin/post.c
+++ b/lib_blackfin/post.c
@@ -32,14 +32,14 @@
#ifdef CONFIG_POST
+DECLARE_GLOBAL_DATA_PTR;
+
#define POST_MAX_NUMBER 32
#define BOOTMODE_MAGIC 0xDEAD0000
int post_init_f(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int res = 0;
unsigned int i;
@@ -62,7 +62,6 @@ int post_init_f(void)
void post_bootmode_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
int bootmode = post_bootmode_get(0);
int newword;
@@ -109,20 +108,17 @@ int post_bootmode_get(unsigned int *last_test)
/* POST tests run before relocation only mark status bits .... */
static void post_log_mark_start(unsigned long testid)
{
- DECLARE_GLOBAL_DATA_PTR;
gd->post_log_word |= (testid) << 16;
}
static void post_log_mark_succ(unsigned long testid)
{
- DECLARE_GLOBAL_DATA_PTR;
gd->post_log_word |= testid;
}
/* ... and the messages are output once we are relocated */
void post_output_backlog(void)
{
- DECLARE_GLOBAL_DATA_PTR;
int j;
for (j = 0; j < post_list_size; j++) {
@@ -372,8 +368,6 @@ int post_log(char *format, ...)
void post_reloc(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned int i;
/*
diff --git a/lib_microblaze/time.c b/lib_microblaze/time.c
index 3fa1b11..b5d8f19 100644
--- a/lib_microblaze/time.c
+++ b/lib_microblaze/time.c
@@ -26,9 +26,17 @@
#include <common.h>
+#ifdef CFG_TIMER_0
void udelay (unsigned long usec)
{
int i;
i = get_timer (0);
while ((get_timer (0) - i) < (usec / 1000)) ;
}
+#else
+void udelay (unsigned long usec)
+{
+ unsigned int i;
+ for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++);
+}
+#endif
diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c
index 693bfe4..55fcc41 100644
--- a/libfdt/fdt_rw.c
+++ b/libfdt/fdt_rw.c
@@ -188,6 +188,32 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
return 0;
}
+/**
+ * fdt_find_and_setprop: Find a node and set it's property
+ *
+ * @fdt: ptr to device tree
+ * @node: path of node
+ * @prop: property name
+ * @val: ptr to new value
+ * @len: length of new property value
+ * @create: flag to create the property if it doesn't exist
+ *
+ * Convenience function to directly set a property given the path to the node.
+ */
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create)
+{
+ int nodeoff = fdt_find_node_by_path(fdt, node);
+
+ if (nodeoff < 0)
+ return nodeoff;
+
+ if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL))
+ return 0; /* create flag not set; so exit quietly */
+
+ return fdt_setprop(fdt, nodeoff, prop, val, len);
+}
+
int fdt_delprop(void *fdt, int nodeoffset, const char *name)
{
struct fdt_property *prop;
diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile
index 0df86f9..8b5461d 100644
--- a/nand_spl/board/amcc/bamboo/Makefile
+++ b/nand_spl/board/amcc/bamboo/Makefile
@@ -84,6 +84,12 @@ $(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)sdram.c:
+ @rm -f $(obj)sdram.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
+endif
+
#########################################################################
$(obj)%.o: $(obj)%.S
diff --git a/net/bootp.c b/net/bootp.c
index be1ee33..749d3e5 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -730,7 +730,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
break;
#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET)
case 2: /* Time offset */
- NetCopyLong (&NetTimeOffset, (ulong *) (popt + 2));
+ NetCopyLong ((ulong *)&NetTimeOffset, (ulong *) (popt + 2));
NetTimeOffset = ntohl (NetTimeOffset);
break;
#endif
diff --git a/net/net.c b/net/net.c
index c47610e..cde2680 100644
--- a/net/net.c
+++ b/net/net.c
@@ -541,11 +541,11 @@ restart:
case NETLOOP_SUCCESS:
if (NetBootFileXferSize > 0) {
- char buf[10];
+ char buf[20];
printf("Bytes transferred = %ld (%lx hex)\n",
NetBootFileXferSize,
NetBootFileXferSize);
- sprintf(buf, "%lx", NetBootFileXferSize);
+ sprintf(buf, "%lX", NetBootFileXferSize);
setenv("filesize", buf);
sprintf(buf, "%lX", (unsigned long)load_addr);