mpc83xx: cosmetic: ve8313.h checkpatch compliance

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

1 files changed, 109 insertions, 95 deletions

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 9d37359..479afba 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -70,7 +70,7 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 
@@ -78,59 +78,60 @@
  * Manually set up DDR parameters, as this board does not
  * have the SPD connected to I2C.
  */
-#define CONFIG_SYS_DDR_SIZE		128		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE	128	/* MB */
+#define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN \
 				| CSCONFIG_AP \
 				| 0x00040000 /* TODO */ \
-				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
 				/* 0x80840102 */
 
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
-				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
-				| ( 3 << TIMING_CFG0_RRT_SHIFT ) \
-				| ( 2 << TIMING_CFG0_WWT_SHIFT ) \
-				| ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
-				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
-				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
-				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (3 << TIMING_CFG0_RRT_SHIFT) \
+				| (2 << TIMING_CFG0_WWT_SHIFT) \
+				| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x0e720802 */
-#define CONFIG_SYS_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
-				| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
-				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
-				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
-				| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
-				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
-				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
-				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x26256222 */
-#define CONFIG_SYS_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
-				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
-				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
-				| ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
-				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
-				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
-				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 				/* 0x029028c7 */
-#define CONFIG_SYS_DDR_INTERVAL	( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
-				| ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_INTERVAL	((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x03202000 */
-#define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_32_BE )
+				| SDRAM_CFG_32_BE)
 				/* 0x43080000 */
-#define CONFIG_SYS_SDRAM_CFG2		0x00401000
-#define CONFIG_SYS_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
-				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
 				/* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE_2		0x8000C000
+#define CONFIG_SYS_DDR_MODE_2	0x8000C000
 
 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 				/*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_NOMZ \
 				| DDRCDR_NZ_NOMZ \
-				| DDRCDR_M_ODR )
+				| DDRCDR_M_ODR)
 				/* 0x73000002 */
 
 /*
@@ -143,16 +144,16 @@
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
 
-#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE | \
-				(2 << BR_PS_SHIFT) |	/* 16 bit */ \
-				BR_V)			/* valid */
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
+					| (2 << BR_PS_SHIFT)	/* 16 bit */ \
+					| BR_V)			/* valid */
 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV4 \
-				| OR_GPCM_SCY_5 \
-				| OR_GPCM_TRLX \
-				| OR_GPCM_EAD)
-				/* 0xfe000c55 */
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV4 \
+					| OR_GPCM_SCY_5 \
+					| OR_GPCM_TRLX \
+					| OR_GPCM_EAD)
+					/* 0xfe000c55 */
 
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32 MB window size */
@@ -171,10 +172,10 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE		0x1000	/* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
@@ -201,19 +202,19 @@
 #define CONFIG_NAND_FSL_ELBC 1
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 
-#define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
-				| BR_PS_8		\
-				| BR_DECC_CHK_GEN	\
-				| BR_MS_FCM		\
-				| BR_V )	/* valid */
-				/* 0x61000c21 */
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
+					| BR_PS_8		\
+					| BR_DECC_CHK_GEN	\
+					| BR_MS_FCM		\
+					| BR_V)	/* valid */
+					/* 0x61000c21 */
 #define CONFIG_SYS_NAND_OR_PRELIM	(0xffff8000 \
-				| OR_FCM_BCTLD \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_2 \
-				| OR_FCM_RST \
-				| OR_FCM_TRLX)
-				/* 0xffff90ac */
+					| OR_FCM_BCTLD \
+					| OR_FCM_CHT \
+					| OR_FCM_SCY_2 \
+					| OR_FCM_RST \
+					| OR_FCM_TRLX)
+					/* 0xffff90ac */
 
 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
@@ -227,27 +228,27 @@
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 
 /* CS2 NvRAM */
-#define CONFIG_SYS_BR2_PRELIM	(0x60000000	\
-				| BR_PS_8	\
+#define CONFIG_SYS_BR2_PRELIM	(0x60000000 \
+				| BR_PS_8 \
 				| BR_V)
 				/* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM	(0xfffe0000	\
-				| OR_GPCM_CSNT	\
-				| OR_GPCM_XACS	\
+#define CONFIG_SYS_OR2_PRELIM	(0xfffe0000 \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_3 \
 				| OR_GPCM_TRLX \
 				| OR_GPCM_EHTR \
 				| OR_GPCM_EAD)
 				/* 0xfffe0937 */
 /* local bus read write buffer mapping SRAM@0x64000000 */
-#define CONFIG_SYS_BR3_PRELIM	(0x62000000	\
-				| BR_PS_16	\
+#define CONFIG_SYS_BR3_PRELIM	(0x62000000 \
+				| BR_PS_16 \
 				| BR_V)
 				/* 0x62001001 */
 
-#define CONFIG_SYS_OR3_PRELIM	(0xfe000000	\
-				| OR_GPCM_CSNT	\
-				| OR_GPCM_XACS	\
+#define CONFIG_SYS_OR3_PRELIM	(0xfe000000 \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_15 \
 				| OR_GPCM_TRLX \
 				| OR_GPCM_EHTR \
@@ -289,9 +290,9 @@
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
 
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
@@ -320,13 +321,13 @@
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
-					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x4000
 /* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
-					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND	\
+			(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
@@ -371,7 +372,8 @@
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
 
 /* 0x64050000 */
 #define CONFIG_SYS_HRCW_LOW (\
@@ -421,18 +423,26 @@
 
 /* DDR @ 0x00000000 */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
-				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 
 #if defined(CONFIG_PCI)
 /* PCI @ 0x80000000 */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
-				BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
-				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
-				BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #else
 #define CONFIG_SYS_IBAT1L	(0)
 #define CONFIG_SYS_IBAT1U	(0)
@@ -447,10 +457,14 @@
 #define CONFIG_SYS_IBAT4U	(0)
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
-				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
-				BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 
 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
@@ -495,10 +509,10 @@
 	"u-boot_addr_r=100000\0"					\
 	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
 	"update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
-	"erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
-	"cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
-	" ${filesize};" \
-	"protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
+	"erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};"		\
+	"cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE)		\
+	" ${filesize};"							\
+	"protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"	\
 
 #undef MK_STR
 #undef XMK_STR