summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMarek Vasut <marex@denx.de>2013-07-12 01:03:04 +0200
committerStefano Babic <sbabic@denx.de>2013-07-12 09:29:32 +0200
commitab94cd491faf3e7b0a3b934f5817b15997bcb315 (patch)
tree2761f93234e1c2c1eaf9abe8c0d37f0dade70ec2
parent3104ce1f6f2d541e8bf2edfb698d0f51dc43b5fb (diff)
downloadu-boot-imx-ab94cd491faf3e7b0a3b934f5817b15997bcb315.zip
u-boot-imx-ab94cd491faf3e7b0a3b934f5817b15997bcb315.tar.gz
u-boot-imx-ab94cd491faf3e7b0a3b934f5817b15997bcb315.tar.bz2
net: fec: Avoid MX28 bus sync issue
The MX28 multi-layer AHB bus can be too slow and trigger the FEC DMA too early, before all the data hit the DRAM. This patch ensures the data are written in the RAM before the DMA starts. Please see the comment in the patch for full details. This patch was produced with an amazing help from Albert Aribaud, who pointed out it can possibly be such a bus synchronisation issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
-rw-r--r--drivers/net/fec_mxc.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 97bf8fe..ec5b9db 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -737,6 +737,28 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
flush_dcache_range(addr, addr + size);
/*
+ * Below we read the DMA descriptor's last four bytes back from the
+ * DRAM. This is important in order to make sure that all WRITE
+ * operations on the bus that were triggered by previous cache FLUSH
+ * have completed.
+ *
+ * Otherwise, on MX28, it is possible to observe a corruption of the
+ * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
+ * for the bus structure of MX28. The scenario is as follows:
+ *
+ * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
+ * to DRAM due to flush_dcache_range()
+ * 2) ARM core writes the FEC registers via AHB_ARB2
+ * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
+ *
+ * Note that 2) does sometimes finish before 1) due to reordering of
+ * WRITE accesses on the AHB bus, therefore triggering 3) before the
+ * DMA descriptor is fully written into DRAM. This results in occasional
+ * corruption of the DMA descriptor.
+ */
+ readl(addr + size - 4);
+
+ /*
* Enable SmartDMA transmit task
*/
fec_tx_task_enable(fec);