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authorWolfgang Denk <wd@denx.de>2008-04-08 00:04:39 +0200
committerWolfgang Denk <wd@denx.de>2008-04-08 00:04:39 +0200
commit5c395393cc9b85b14c5481dbcab6b67b54f31622 (patch)
tree888e8cd55173a99f636b19e2813e3dfe6afe3d44
parente59af4b611408adcdfb5e19bc5194a7d1f8b4dc3 (diff)
parent280df59a8d62c6e74c281b1cb7e2052df4d6cb00 (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-sh
-rw-r--r--CREDITS4
-rw-r--r--MAINTAINERS12
-rwxr-xr-xMAKEALL4
-rw-r--r--Makefile20
-rw-r--r--board/MigoR/Makefile48
-rw-r--r--board/MigoR/config.mk32
-rw-r--r--board/MigoR/lowlevel_init.S269
-rw-r--r--board/MigoR/migo_r.c54
-rw-r--r--board/MigoR/u-boot.lds106
-rw-r--r--board/mpr2/Makefile54
-rw-r--r--board/mpr2/config.mk37
-rw-r--r--board/mpr2/lowlevel_init.S148
-rw-r--r--board/mpr2/mpr2.c162
-rw-r--r--board/mpr2/u-boot.lds109
-rw-r--r--board/r2dplus/Makefile43
-rw-r--r--board/r2dplus/config.mk23
-rw-r--r--board/r2dplus/lowlevel_init.S154
-rw-r--r--board/r2dplus/r2dplus.c76
-rw-r--r--board/r2dplus/u-boot.lds105
-rw-r--r--board/r7780mp/Makefile44
-rw-r--r--board/r7780mp/config.mk27
-rw-r--r--board/r7780mp/lowlevel_init.S428
-rw-r--r--board/r7780mp/r7780mp.c81
-rw-r--r--board/r7780mp/r7780mp.h54
-rw-r--r--board/r7780mp/u-boot.lds105
-rw-r--r--cpu/sh4/cpu.c3
-rw-r--r--doc/README.sh51
-rw-r--r--drivers/pci/Makefile3
-rw-r--r--drivers/pci/pci_sh4.c76
-rw-r--r--drivers/pci/pci_sh7751.c199
-rw-r--r--drivers/pci/pci_sh7780.c107
-rw-r--r--drivers/serial/serial_sh.c70
-rw-r--r--include/asm-sh/cache.h35
-rw-r--r--include/asm-sh/cpu_sh4.h13
-rw-r--r--include/asm-sh/cpu_sh7720.h25
-rw-r--r--include/asm-sh/cpu_sh7750.h4
-rw-r--r--include/asm-sh/cpu_sh7780.h503
-rw-r--r--include/asm-sh/pci.h47
-rw-r--r--include/asm-sh/processor.h3
-rw-r--r--include/configs/MigoR.h151
-rw-r--r--include/configs/mpr2.h92
-rw-r--r--include/configs/r2dplus.h150
-rw-r--r--include/configs/r7780mp.h165
-rw-r--r--include/linux/stat.h4
-rw-r--r--lib_sh/board.c13
45 files changed, 3863 insertions, 50 deletions
diff --git a/CREDITS b/CREDITS
index 1627dc7..26d5f51 100644
--- a/CREDITS
+++ b/CREDITS
@@ -236,6 +236,10 @@ E: mark.jonas@freescale.com
D: Support for Freescale Total5200 platform
W: http://www.mobilegt.com/
+N: Mark Jonas
+E: mark.jonas@de.bosch.com
+D: Support for MPR2 board
+
N: Sam Song
E: samsongshu@yahoo.com.cn
D: Port to the RPXlite_DW board
diff --git a/MAINTAINERS b/MAINTAINERS
index d9ffebf..31c0311 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -695,15 +695,25 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
# Board CPU #
#########################################################################
-Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
+Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
MS7750SE SH7750
MS7722SE SH7722
+ R7780MP SH7780
+ R2DPlus SH7751R
+
+Mark Jonas <mark.jonas@de.bosch.com>
+
+ mpr2 SH7720
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
+Yusuke Goda <goda.yusuke@renesas.com>
+
+ MIGO-R SH7722
+
#########################################################################
# Blackfin Systems: #
# #
diff --git a/MAKEALL b/MAKEALL
index b2ae35b..c026b05 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -700,9 +700,13 @@ LIST_blackfin=" \
LIST_sh4=" \
ms7750se \
ms7722se \
+ Migo-R \
+ r7780mp \
+ r2dplus \
"
LIST_sh3=" \
+ mpr2 \
ms7720se \
"
diff --git a/Makefile b/Makefile
index 744abae..890c097 100644
--- a/Makefile
+++ b/Makefile
@@ -2842,6 +2842,11 @@ atngw100_config : unconfig
#########################################################################
## sh3 (Renesas SuperH)
#########################################################################
+mpr2_config: unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_MPR2 1" >> include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2
+
ms7720se_config: unconfig
@echo "#define CONFIG_MS7720SE 1" > include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se
@@ -2857,6 +2862,21 @@ ms7722se_config : unconfig
@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se
+MigoR_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_MIGO_R 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 MigoR
+
+r7780mp_config: unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_R7780MP 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 r7780mp
+
+r2dplus_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_R2DPLUS 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 r2dplus
+
#########################################################################
#########################################################################
#########################################################################
diff --git a/board/MigoR/Makefile b/board/MigoR/Makefile
new file mode 100644
index 0000000..5a9d651
--- /dev/null
+++ b/board/MigoR/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := migo_r.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/MigoR/config.mk b/board/MigoR/config.mk
new file mode 100644
index 0000000..c68cb72
--- /dev/null
+++ b/board/MigoR/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
+
diff --git a/board/MigoR/lowlevel_init.S b/board/MigoR/lowlevel_init.S
new file mode 100644
index 0000000..7fd771d
--- /dev/null
+++ b/board/MigoR/lowlevel_init.S
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D, r0 ! Instruction Cache Invalidate
+ mov.l r0, @r1
+
+ mov.l MMUCR_A, r1 ! Address of MMU Control Register
+ mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
+ mov.l r0, @r1
+
+ mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
+ mov.l MSTPCR0_D, r0 !
+ mov.l r0, @r1
+
+ mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
+ mov.l MSTPCR2_D, r0 !
+ mov.l r0, @r1
+
+ mov.l PFC_PULCR_A, r1
+ mov.w PFC_PULCR_D, r0
+ mov.w r0,@r1
+
+ mov.l PFC_DRVCR_A, r1
+ mov.w PFC_DRVCR_D, r0
+ mov.w r0, @r1
+
+ mov.l SBSCR_A, r1 !
+ mov.w SBSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l PSCR_A, r1 !
+ mov.w PSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
+ mov.w r0, @r1
+
+ mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
+ mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
+ mov.w r0, @r1
+
+ mov.l DLLFRQ_A, r1 ! 20080115
+ mov.l DLLFRQ_D, r0 ! 20080115
+ mov.l r0, @r1
+
+ mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
+ mov.l FRQCR_D, r0 ! 20080115
+ mov.l r0, @r1
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D_2, r0 ! ??
+ mov.l r0, @r1
+
+bsc_init:
+
+ mov.l CMNCR_A, r1 ! CMNCR address -> R1
+ mov.l CMNCR_D, r0 ! CMNCR data -> R0
+ mov.l r0, @r1 ! CMNCR set
+
+ mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
+ mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
+ mov.l r0, @r1 ! CS0BCR set
+
+ mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
+ mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
+ mov.l r0, @r1 ! CS4BCR set
+
+ mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
+ mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
+ mov.l r0, @r1 ! CS5ABCR set
+
+ mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
+ mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
+ mov.l r0, @r1 ! CS5BBCR set
+
+ mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
+ mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
+ mov.l r0, @r1 ! CS6ABCR set
+
+ mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
+ mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
+ mov.l r0, @r1 ! CS0WCR set
+
+ mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
+ mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
+ mov.l r0, @r1 ! CS4WCR set
+
+ mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
+ mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
+ mov.l r0, @r1 ! CS5AWCR set
+
+ mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
+ mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
+ mov.l r0, @r1 ! CS5BWCR set
+
+ mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
+ mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
+ mov.l r0, @r1 ! CS6AWCR set
+
+ ! SDRAM initialization
+ mov.l SDCR_A, r1 ! SB_SDCR address -> R1
+ mov.l SDCR_D, r0 ! SB_SDCR data -> R0
+ mov.l r0, @r1 ! SB_SDCR set
+
+ mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
+ mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
+ mov.l r0, @r1 ! SB_SDWCR set
+
+ mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
+ mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
+ mov.l r0, @r1 ! SB_SDPCR set
+
+ mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
+ mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
+ mov.l r0, @r1 ! SB_RTCOR set
+
+ mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
+ mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
+ mov.l r0, @r1
+
+ mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
+ mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
+ mov.l r0, @r1 ! SB_RTCSR set
+
+ mov.l RFCR_A, r1 ! SB_RFCR address -> R1
+ mov.l RFCR_D, r0 ! SB_RFCR data -> R0
+ mov.l r0, @r1
+
+ mov.l SDMR3_A, r1 ! SDMR3 address -> R1
+ mov #0x00, r0 ! SDMR3 data -> R0
+ mov.b r0, @r1 ! SDMR3 set
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+
+
+ .align 4
+
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+MSTPCR0_A: .long MSTPCR0
+MSTPCR2_A: .long MSTPCR2
+PFC_PULCR_A: .long PULCR
+PFC_DRVCR_A: .long DRVCR
+SBSCR_A: .long SBSCR
+PSCR_A: .long PSCR
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+PLLCR_A: .long PLLCR
+DLLFRQ_A: .long DLLFRQ
+
+CCR_D: .long 0x00000800
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+PFC_PULCR_D: .long 0x6000
+PFC_DRVCR_D: .long 0x0464
+FRQCR_D: .long 0x07033639
+PLLCR_D: .long 0x00005000
+DLLFRQ_D: .long 0x000004F6 ! 20080115
+
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x0000001B ! 20080115
+CS0BCR_A: .long CS0BCR ! Flash bank 1
+CS0BCR_D: .long 0x24920400
+CS4BCR_A: .long CS4BCR !
+CS4BCR_D: .long 0x10003400 ! 20080115
+CS5ABCR_A: .long CS5ABCR !
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_A: .long CS5BBCR !
+CS5BBCR_D: .long 0x24920400
+CS6ABCR_A: .long CS6ABCR !
+CS6ABCR_D: .long 0x24920400
+
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000380
+CS4WCR_A: .long CS4WCR
+CS4WCR_D: .long 0x00100A81 ! 20080115
+CS5AWCR_A: .long CS5AWCR
+CS5AWCR_D: .long 0x00000300
+CS5BWCR_A: .long CS5BWCR
+CS5BWCR_D: .long 0x00000300
+CS6AWCR_A: .long CS6AWCR
+CS6AWCR_D: .long 0x00000300
+
+SDCR_A: .long SBSC_SDCR
+SDCR_D: .long 0x80160809 ! 20080115
+SDWCR_A: .long SBSC_SDWCR
+SDWCR_D: .long 0x0014450C ! 20080115
+SDPCR_A: .long SBSC_SDPCR
+SDPCR_D: .long 0x00000087
+RTCOR_A: .long SBSC_RTCOR
+RTCNT_A: .long SBSC_RTCNT
+RTCNT_D: .long 0xA55A0012
+RTCOR_D: .long 0xA55A001C ! 20080115
+RTCSR_A: .long SBSC_RTCSR
+RFCR_A: .long SBSC_RFCR
+RFCR_D: .long 0xA55A0221
+RTCSR_D: .long 0xA55A009a ! 20080115
+SDMR3_A: .long 0xFE581180 ! 20080115
+
+SR_MASK_D: .long 0xEFFFFF0F
+
+ .align 2
+
+SBSCR_D: .word 0x0044
+PSCR_D: .word 0x0000
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA504 ! 20080115
+RWTCNT_D: .word 0x5A00
+
diff --git a/board/MigoR/migo_r.c b/board/MigoR/migo_r.c
new file mode 100644
index 0000000..53f4bb2
--- /dev/null
+++ b/board/MigoR/migo_r.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/migo_r.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas MigoR\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+}
+
diff --git a/board/MigoR/u-boot.lds b/board/MigoR/u-boot.lds
new file mode 100644
index 0000000..1877b81
--- /dev/null
+++ b/board/MigoR/u-boot.lds
@@ -0,0 +1,106 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
+
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
new file mode 100644
index 0000000..17ca17e
--- /dev/null
+++ b/board/mpr2/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# (C) Copyright 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mpr2.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpr2/config.mk b/board/mpr2/config.mk
new file mode 100644
index 0000000..6d41d97
--- /dev/null
+++ b/board/mpr2/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# Copyright (C) 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S
new file mode 100644
index 0000000..060957a
--- /dev/null
+++ b/board/mpr2/lowlevel_init.S
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * board/mpr2/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+/*
+ * Set frequency multipliers and dividers in FRQCR.
+ */
+ mov.l WTCSR_A,r1
+ mov.l WTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l WTCNT_A,r1
+ mov.l WTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l FRQCR_A,r1
+ mov.l FRQCR_D,r0
+ mov.w r0,@r1
+
+/*
+ * Setup CS0 (Flash).
+ */
+ mov.l CS0BCR_A, r1
+ mov.l CS0BCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS0WCR_A, r1
+ mov.l CS0WCR_D, r0
+ mov.l r0, @r1
+
+/*
+ * Setup CS3 (SDRAM).
+ */
+ mov.l CS3BCR_A, r1
+ mov.l CS3BCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS3WCR_A, r1
+ mov.l CS3WCR_D, r0
+ mov.l r0, @r1
+
+ mov.l SDCR_A, r1
+ mov.l SDCR_D1, r0
+ mov.l r0, @r1
+
+ mov.l RTCSR_A, r1
+ mov.l RTCSR_D, r0
+ mov.l r0, @r1
+
+ mov.l RTCNT_A, r1
+ mov.l RTCNT_D, r0
+ mov.l r0, @r1
+
+ mov.l RTCOR_A, r1
+ mov.l RTCOR_D, r0
+ mov.l r0, @r1
+
+ mov.l SDCR_A, r1
+ mov.l SDCR_D2, r0
+ mov.l r0, @r1
+
+ mov.l SDMR3_A, r1
+ mov.l SDMR3_D, r0
+ add r0, r1
+ mov #0, r0
+ mov.w r0, @r1
+
+ rts
+ nop
+
+ .align 4
+
+/*
+ * Configuration for MPR2 A.3 through A.7
+ */
+
+/*
+ * PLL Settings
+ */
+FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
+WTCNT_D: .long 0x5A00 /* start counting at zero */
+WTCSR_D: .long 0xA507 /* divide by 4096 */
+
+/*
+ * Spansion S29GL256N11 @ 48 MHz
+ */
+CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
+CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+
+/*
+ * Samsung K4S511632B-UL75 @ 48 MHz
+ * Micron MT48LC32M16A2-75 @ 48 MHz
+ */
+CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D2: .long 0x00000812 /* refresh */
+RTCSR_D: .long 0xA55A0008 /* 1/4, once */
+RTCNT_D: .long 0xA55A005D /* count 93 */
+RTCOR_D: .long 0xa55a005d /* count 93 */
+SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
+
+/*
+ * Registers
+ */
+
+FRQCR_A: .long 0xA415FF80
+WTCNT_A: .long 0xA415FF84
+WTCSR_A: .long 0xA415FF86
+
+#define BSC_BASE 0xA4FD0000
+CS0BCR_A: .long BSC_BASE + 0x04
+CS3BCR_A: .long BSC_BASE + 0x0C
+CS0WCR_A: .long BSC_BASE + 0x24
+CS3WCR_A: .long BSC_BASE + 0x2C
+SDCR_A: .long BSC_BASE + 0x44
+RTCSR_A: .long BSC_BASE + 0x48
+RTCNT_A: .long BSC_BASE + 0x4C
+RTCOR_A: .long BSC_BASE + 0x50
+SDMR3_A: .long BSC_BASE + 0x5000
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
new file mode 100644
index 0000000..2ddb0c1
--- /dev/null
+++ b/board/mpr2/mpr2.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * board/mpr2/mpr2.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: MPR2\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * For MPR2 A.3 through A.7
+ */
+
+ /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
+ __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
+ __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
+
+ /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
+ __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
+ __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
+ __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
+ __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
+
+ /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
+ __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
+
+ /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
+ __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
+
+ /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
+ __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
+
+ /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
+ __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
+
+ /* OTH: (00) Other fuction
+ * GPO: (01) General Purpose Output
+ * GPI: (11) General Purpose Input
+ * GPI+: (10) General Purpose Input with internal pull-up
+ *-------------------------------------------------------
+ * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
+ * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
+ __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
+
+ /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
+ * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
+ __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
+ * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
+ __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
+
+ /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
+ * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
+ __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
+ * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
+ __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
+
+ /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
+ * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
+ __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
+
+ /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
+ * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
+ __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
+
+ /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
+ * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
+ __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
+
+ /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
+ * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
+ __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* K7 (x); K6 (x); K5 (x); K4 (x)
+ * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
+ __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
+
+ /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
+ * L3 TCK; L2 (x); L1 (x); L0 (x); */
+ __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
+ * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
+ __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
+ __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
+
+ /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
+ * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
+ __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
+ __raw_writeb(0x10, PPDR); /* no current flow through pullup */
+
+ /* R7 A25; R6 A24; R5 A23; R4 A22;
+ * R3 A21; R2 A20; R1 A19; R0 A0; */
+ __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
+ * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
+ __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
+
+ /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
+ * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
+ __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
+
+ /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
+ * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
+ __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
+
+ /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
+ * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
+ __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
diff --git a/board/mpr2/u-boot.lds b/board/mpr2/u-boot.lds
new file mode 100644
index 0000000..6fee7f2
--- /dev/null
+++ b/board/mpr2/u-boot.lds
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x8C000000.
+ U-Boot resides in the last 256 kB of the 64 MB.
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh3/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile
new file mode 100644
index 0000000..ed609ea
--- /dev/null
+++ b/board/r2dplus/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := r2dplus.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
diff --git a/board/r2dplus/config.mk b/board/r2dplus/config.mk
new file mode 100644
index 0000000..1ec7dcc
--- /dev/null
+++ b/board/r2dplus/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x0FFC0000
diff --git a/board/r2dplus/lowlevel_init.S b/board/r2dplus/lowlevel_init.S
new file mode 100644
index 0000000..5755de8
--- /dev/null
+++ b/board/r2dplus/lowlevel_init.S
@@ -0,0 +1,154 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_D, r0
+ mov.l r0,@r1
+
+ mov.l MMUCR_A,r1
+ mov.l MMUCR_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR1_A,r1
+ mov.l BCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR2_A,r1
+ mov.l BCR2_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR3_A,r1
+ mov.l BCR3_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR4_A,r1
+ mov.l BCR4_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR1_A,r1
+ mov.l WCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR2_A,r1
+ mov.l WCR2_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR3_A,r1
+ mov.l WCR3_D,r0
+ mov.l r0,@r1
+
+ mov.l PCR_A,r1
+ mov.l PCR_D,r0
+ mov.w r0,@r1
+
+ mov.l LED_A,r1
+ mov #0xff,r0
+ mov.w r0,@r1
+
+ mov.l MCR_A,r1
+ mov.l MCR_D1,r0
+ mov.l r0,@r1
+
+ mov.l RTCNT_A,r1
+ mov.l RTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCOR_A,r1
+ mov.l RTCOR_D,r0
+ mov.w r0,@r1
+
+ mov.l RFCR_A,r1
+ mov.l RFCR_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCSR_A,r1
+ mov.l RTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0x55,r0
+ mov.b r0,@r1
+
+ /* Wait DRAM refresh 30 times */
+ mov.l RFCR_A,r1
+ mov #30,r3
+1:
+ mov.w @r1,r0
+ extu.w r0,r2
+ cmp/hi r3,r2
+ bf 1b
+
+ mov.l MCR_A,r1
+ mov.l MCR_D2,r0
+ mov.l r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0,r0
+ mov.b r0,@r1
+
+ mov.l IRLMASK_A,r1
+ mov.l IRLMASK_D,r0
+ mov.l r0,@r1
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_E, r0
+ mov.l r0, @r1
+
+ rts
+ nop
+
+ .align 2
+CCR_A: .long CCR /* Cache Control Register */
+CCR_D_D: .long 0x0808 /* Flush the cache, disable */
+CCR_D_E: .long 0x8000090B
+
+FRQCR_A: .long FRQCR /* FRQCR Address */
+FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
+BCR1_A: .long BCR1 /* BCR1 Address */
+BCR1_D: .long 0x00180008
+BCR2_A: .long BCR2 /* BCR2 Address */
+BCR2_D: .long 0xabe8
+BCR3_A: .long BCR3 /* BCR3 Address */
+BCR3_D: .long 0x0000
+BCR4_A: .long BCR4 /* BCR4 Address */
+BCR4_D: .long 0x00000010
+WCR1_A: .long WCR1 /* WCR1 Address */
+WCR1_D: .long 0x33343333
+WCR2_A: .long WCR2 /* WCR2 Address */
+WCR2_D: .long 0xcff86fbf
+WCR3_A: .long WCR3 /* WCR3 Address */
+WCR3_D: .long 0x07777707
+LED_A: .long 0x04000036 /* LED Address */
+RTCNT_A: .long RTCNT /* RTCNT Address */
+RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
+RTCOR_A: .long RTCOR /* RTCOR Address */
+RTCOR_D: .long 0xA534 /* RTCOR Write Code */
+RTCSR_A: .long RTCSR /* RTCSR Address */
+RTCSR_D: .long 0xA510 /* RTCSR Write Code */
+SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
+SDMR3_D: .long 0x55
+MCR_A: .long MCR /* MCR Address */
+MCR_D1: .long 0x081901F4 /* MRSET:'0' */
+MCR_D2: .long 0x481901F4 /* MRSET:'1' */
+RFCR_A: .long RFCR /* RFCR Address */
+RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
+PCR_A: .long PCR /* PCR Address */
+PCR_D: .long 0x0000
+MMUCR_A: .long MMUCR /* MMUCCR Address */
+MMUCR_D: .long 0x00000000 /* MMUCCR Data */
+IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
+IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c
new file mode 100644
index 0000000..2ee3ea2
--- /dev/null
+++ b/board/r2dplus/r2dplus.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Solutions R2D Plus\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset){
+ (*(vu_short *)FPGA_CFCTL) = 0x432;
+ (*(vu_short *)FPGA_CFPOW) |= 0x02;
+ (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ }
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7751_init( &hose );
+}
+#endif /* CONFIG_PCI */
diff --git a/board/r2dplus/u-boot.lds b/board/r2dplus/u-boot.lds
new file mode 100644
index 0000000..96d8d81
--- /dev/null
+++ b/board/r2dplus/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x0C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
diff --git a/board/r7780mp/Makefile b/board/r7780mp/Makefile
new file mode 100644
index 0000000..554dca1
--- /dev/null
+++ b/board/r7780mp/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r7780mp/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := r7780mp.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/r7780mp/config.mk b/board/r7780mp/config.mk
new file mode 100644
index 0000000..6a045a1
--- /dev/null
+++ b/board/r7780mp/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r77870mp/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x0FFC0000
diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S
new file mode 100644
index 0000000..eb5d8b7
--- /dev/null
+++ b/board/r7780mp/lowlevel_init.S
@@ -0,0 +1,428 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * u-boot/board/r7780mp/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 /* Address of Cache Control Register */
+ mov.l CCR_D, r0 /* Instruction Cache Invalidate */
+ mov.l r0, @r1
+
+ mov.l FRQCR_A, r1 /* Frequency control register */
+ mov.l FRQCR_D, r0
+ mov.l r0, @r1
+
+ /* pin_multi_setting */
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR1,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR1_A,r1
+ mov.l BBG_PMSR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR2,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR2_A,r1
+ mov.l BBG_PMSR2_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR3,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR3_A,r1
+ mov.l BBG_PMSR3_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR4,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR4_A,r1
+ mov.l BBG_PMSR4_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSRG,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSRG_A,r1
+ mov.l BBG_PMSRG_D,r0
+ mov.l r0,@r1
+
+ /* cpg_setting */
+ mov.l FRQCR_A,r1
+ mov.l FRQCR_D,r0
+ mov.l r0,@r1
+
+ mov.l DLLCSR_A,r1
+ mov.l DLLCSR_D,r0
+ mov.l r0,@r1
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* wait 200us */
+ mov.l REPEAT0_R3,r3
+ mov #0,r2
+repeat0:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat0
+ nop
+
+ /* bsc_setting */
+ mov.l MMSELR_A,r1
+ mov.l MMSELR_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR_A,r1
+ mov.l BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS0BCR_A,r1
+ mov.l CS0BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS1BCR_A,r1
+ mov.l CS1BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS2BCR_A,r1
+ mov.l CS2BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS4BCR_A,r1
+ mov.l CS4BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5BCR_A,r1
+ mov.l CS5BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6BCR_A,r1
+ mov.l CS6BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS0WCR_A,r1
+ mov.l CS0WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS1WCR_A,r1
+ mov.l CS1WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS2WCR_A,r1
+ mov.l CS2WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS4WCR_A,r1
+ mov.l CS4WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5WCR_A,r1
+ mov.l CS5WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6WCR_A,r1
+ mov.l CS6WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5PCR_A,r1
+ mov.l CS5PCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6PCR_A,r1
+ mov.l CS6PCR_D,r0
+ mov.l r0,@r1
+
+ /* ddr_setting */
+ /* wait 200us */
+ mov.l REPEAT0_R3,r3
+ mov #0,r2
+repeat1:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat1
+ nop
+
+ mov.l MIM_U_A,r0
+ mov.l MIM_U_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l MIM_L_A,r0
+ mov.l MIM_L_D0,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l STR_L_A,r0
+ mov.l STR_L_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l SDR_L_A,r0
+ mov.l SDR_L_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D0,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D1,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l EMRS_A,r0
+ mov.l EMRS_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS1_A,r0
+ mov.l MRS1_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D2,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D3,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D4,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS2_A,r0
+ mov.l MRS2_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D5,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ /* wait 200us */
+ mov.l REPEAT0_R1,r3
+ mov #0,r2
+repeat2:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat2
+
+ synco
+
+ mov.l MIM_L_A,r0
+ mov.l MIM_L_D1,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ rts
+ nop
+ .align 4
+
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
+
+BBG_PMMR_A: .long 0xFF800010
+BBG_PMSR1_A: .long 0xFF800014
+BBG_PMSR2_A: .long 0xFF800018
+BBG_PMSR3_A: .long 0xFF80001C
+BBG_PMSR4_A: .long 0xFF800020
+BBG_PMSRG_A: .long 0xFF800024
+
+BBG_PMMR_D_PMSR1: .long 0xffffbffd
+BBG_PMSR1_D: .long 0x00004002
+BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
+BBG_PMSR2_D: .long 0x03de5800
+BBG_PMMR_D_PMSR3: .long 0xfffffff8
+BBG_PMSR3_D: .long 0x00000007
+BBG_PMMR_D_PMSR4: .long 0xdffdfff9
+BBG_PMSR4_D: .long 0x20020006
+BBG_PMMR_D_PMSRG: .long 0xffffffff
+BBG_PMSRG_D: .long 0x00000000
+
+FRQCR_A: .long FRQCR
+DLLCSR_A: .long 0xffc40010
+FRQCR_D: .long 0x40233035
+DLLCSR_D: .long 0x00000000
+
+/* for DDR-SDRAM */
+MIM_U_A: .long MIM_1
+MIM_L_A: .long MIM_2
+SCR_U_A: .long SCR_1
+SCR_L_A: .long SCR_2
+STR_U_A: .long STR_1
+STR_L_A: .long STR_2
+SDR_U_A: .long SDR_1
+SDR_L_A: .long SDR_2
+
+EMRS_A: .long 0xFEC02000
+MRS1_A: .long 0xFEC00B08
+MRS2_A: .long 0xFEC00308
+
+MIM_U_D: .long 0x00004000
+MIM_L_D0: .long 0x03e80009
+MIM_L_D1: .long 0x03e80209
+SCR_L_D0: .long 0x3
+SCR_L_D1: .long 0x2
+SCR_L_D2: .long 0x2
+SCR_L_D3: .long 0x4
+SCR_L_D4: .long 0x4
+SCR_L_D5: .long 0x0
+STR_L_D: .long 0x000f0000
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x0
+MRS1_D: .long 0x0
+MRS2_D: .long 0x0
+
+/* Cache Controller */
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+RWTCNT_A: .long WTCNT
+
+CCR_D: .long 0x0000090b
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+
+/* local Bus State Controller */
+MMSELR_A: .long MMSELR
+BCR_A: .long BCR
+CS0BCR_A: .long CS0BCR
+CS1BCR_A: .long CS1BCR
+CS2BCR_A: .long CS2BCR
+CS4BCR_A: .long CS4BCR
+CS5BCR_A: .long CS5BCR
+CS6BCR_A: .long CS6BCR
+CS0WCR_A: .long CS0WCR
+CS1WCR_A: .long CS1WCR
+CS2WCR_A: .long CS2WCR
+CS4WCR_A: .long CS4WCR
+CS5WCR_A: .long CS5WCR
+CS6WCR_A: .long CS6WCR
+CS5PCR_A: .long CS5PCR
+CS6PCR_A: .long CS6PCR
+
+MMSELR_D: .long 0xA5A50003
+BCR_D: .long 0x00000000
+CS0BCR_D: .long 0x77777770
+CS1BCR_D: .long 0x77777670
+CS2BCR_D: .long 0x77777770
+CS4BCR_D: .long 0x77777770
+CS5BCR_D: .long 0x77777670
+CS6BCR_D: .long 0x77777770
+CS0WCR_D: .long 0x00020006
+CS1WCR_D: .long 0x00232304
+CS2WCR_D: .long 0x7777770F
+CS4WCR_D: .long 0x7777770F
+CS5WCR_D: .long 0x00101006
+CS6WCR_D: .long 0x77777703
+CS5PCR_D: .long 0x77000000
+CS6PCR_D: .long 0x77000000
+
+REPEAT0_R3: .long 0x00002000
+REPEAT0_R1: .long 0x0000200
diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c
new file mode 100644
index 0000000..1a37711
--- /dev/null
+++ b/board/r7780mp/r7780mp.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include "r7780mp.h"
+
+int checkboard(void)
+{
+#if defined(CONFIG_R7780MP)
+ puts("BOARD: Renesas Solutions R7780MP\n");
+#else
+ puts("BOARD: Renesas Solutions R7780RP\n");
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* SCIF Enable */
+ *(vu_short*)PHCR = 0x0000;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+
+}
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset){
+ (*(vu_short *)FPGA_CFCTL) = 0x432;
+#if defined(CONFIG_R7780MP)
+ (*(vu_short *)FPGA_CFPOW) |= 0x01;
+#else
+ (*(vu_short *)FPGA_CFPOW) |= 0x02;
+#endif
+ (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ }
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7780_init( &hose );
+}
+#endif
diff --git a/board/r7780mp/r7780mp.h b/board/r7780mp/r7780mp.h
new file mode 100644
index 0000000..476a413
--- /dev/null
+++ b/board/r7780mp/r7780mp.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/board/r7780mp/r7780mp.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_R7780MP_R7780MP_H_
+#define _BOARD_R7780MP_R7780MP_H_
+
+/* R7780MP's FPGA register map */
+#define FPGA_BASE 0xa4000000
+#define FPGA_IRLMSK (FPGA_BASE + 0x00)
+#define FPGA_IRLMON (FPGA_BASE + 0x02)
+#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
+#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
+#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
+#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
+#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
+#define FPGA_PCIBD (FPGA_BASE + 0x0E)
+#define FPGA_PCICD (FPGA_BASE + 0x10)
+#define FPGA_EXTGIO (FPGA_BASE + 0x16)
+#define FPGA_IVDRMON (FPGA_BASE + 0x18)
+#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
+#define FPGA_OBLED (FPGA_BASE + 0x1C)
+#define FPGA_OBSW (FPGA_BASE + 0x1E)
+#define FPGA_TPCTL (FPGA_BASE + 0x100)
+#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
+#define FPGA_TPCLR (FPGA_BASE + 0x104)
+#define FPGA_TPXPOS (FPGA_BASE + 0x106)
+#define FPGA_TPYPOS (FPGA_BASE + 0x108)
+#define FPGA_DBSW (FPGA_BASE + 0x200)
+#define FPGA_VERSION (FPGA_BASE + 0x700)
+#define FPGA_CFCTL (FPGA_BASE + 0x300)
+#define FPGA_CFPOW (FPGA_BASE + 0x302)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
+#define FPGA_PMR (FPGA_BASE + 0x900)
+
+#endif /* _BOARD_R7780RP_R7780RP_H_ */
diff --git a/board/r7780mp/u-boot.lds b/board/r7780mp/u-boot.lds
new file mode 100644
index 0000000..e7499e5
--- /dev/null
+++ b/board/r7780mp/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x08000000 + (128*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c
index 0ebf951..d94e139 100644
--- a/cpu/sh4/cpu.c
+++ b/cpu/sh4/cpu.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <command.h>
#include <asm/processor.h>
+#include <asm/cache.h>
int checkcpu(void)
{
@@ -51,7 +52,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
void flush_cache (unsigned long addr, unsigned long size)
{
-
+ dcache_invalid_range( addr , addr + size );
}
void icache_enable (void)
diff --git a/doc/README.sh b/doc/README.sh
index 075d360..6baee08 100644
--- a/doc/README.sh
+++ b/doc/README.sh
@@ -1,6 +1,6 @@
U-Boot for Renesas SuperH
- Last update 08/10/2007 by Nobuhiro Iwamatsu
+ Last update 01/18/2008 by Nobuhiro Iwamatsu
================================================================================
0. What's this?
@@ -18,7 +18,19 @@ U-Boot for Renesas SuperH
2. Supported CPUs
2.1. Renesas SH7750/SH7750R
+ This CPU has the SH4 core.
+
2.2. Renesas SH7722
+ This CPU has the SH4AL-DSP core.
+
+ 2.3. Renesas SH7720
+ This CPU has the SH3 core.
+
+ 2.4. Renesas SH7710/SH7712
+ This CPU has the SH3-DSP core and Ethernet controller.
+
+ 2.5. Renesas SH7780
+ This CPU has the SH4A core.
================================================================================
3. Supported Boards
@@ -26,10 +38,42 @@ U-Boot for Renesas SuperH
3.1. Hitachi UL MS7750SE01/MS7750RSE01
Board specific code is in board/ms7750se
To use this board, type "make ms7750se_config".
+ Support devices are :
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
3.2. Hitachi UL MS7722SE01
Board specific code is in board/ms7722se
To use this board, type "make ms7722se_config".
+ Support devices are :
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+ - SMC91x ethernet
+
+ 3.2. Hitachi UL MS7720ERP01
+ Board specific code is in board/ms7720se
+ To use this board, type "make ms7720se_config".
+ Support devices are :
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+
+ 3.3. Renesas R7780MP
+ Board specific code is in board/r7780mp
+ To use this board, type "make r7780mp_config".
+ Support devices are :
+ - SCIF
+ - DDR-SDRAM
+ - NOR Flash
+ - Compact Flash
+ - ASIX ethernet
+ - SH7780 PCI bridge
+ - RTL8110 ethernet
** README **
In SuperH, S-record and binary of made u-boot work on the memory.
@@ -49,13 +93,12 @@ U-Boot for Renesas SuperH
5. Future
I plan to support the following CPUs and boards.
5.1. CPUs
- - SH7710/SH7712 (SH3)
- - SH7780(SH4)
+ - SH7751R(SH4)
- SH7785(SH4)
5.2. Boards
- Many boards ;-)
================================================================================
-Copyright (c) 2007
+Copyright (c) 2007,2008
Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index fe45839..ad1b7dd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -31,6 +31,9 @@ COBJS-y += pci_auto.o
COBJS-y += pci_indirect.o
COBJS-y += tsi108_pci.o
COBJS-y += w83c553f.o
+COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
+COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
+COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c
new file mode 100644
index 0000000..1290c0a
--- /dev/null
+++ b/drivers/pci/pci_sh4.c
@@ -0,0 +1,76 @@
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/cpu/sh4/pci-sh4.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <pci.h>
+
+int pci_sh4_init(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->region_count = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+ hose->region_count++;
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count++;
+
+ udelay(1000);
+
+ pci_set_ops(hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ pci_sh4_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ pci_sh4_write_config_dword);
+
+ pci_register_hose(hose);
+
+ udelay(1000);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ hose->last_busno = pci_hose_scan(hose);
+ return 0;
+}
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
new file mode 100644
index 0000000..a058e1d
--- /dev/null
+++ b/drivers/pci/pci_sh7751.c
@@ -0,0 +1,199 @@
+/*
+ * SH7751 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* Register addresses and such */
+#define SH7751_BCR1 (vu_long *)0xFF800000
+#define SH7751_BCR2 (vu_short*)0xFF800004
+#define SH7751_WCR1 (vu_long *)0xFF800008
+#define SH7751_WCR2 (vu_long *)0xFF80000C
+#define SH7751_WCR3 (vu_long *)0xFF800010
+#define SH7751_MCR (vu_long *)0xFF800014
+#define SH7751_BCR3 (vu_short*)0xFF800050
+#define SH7751_PCICONF0 (vu_long *)0xFE200000
+#define SH7751_PCICONF1 (vu_long *)0xFE200004
+#define SH7751_PCICONF2 (vu_long *)0xFE200008
+#define SH7751_PCICONF3 (vu_long *)0xFE20000C
+#define SH7751_PCICONF4 (vu_long *)0xFE200010
+#define SH7751_PCICONF5 (vu_long *)0xFE200014
+#define SH7751_PCICONF6 (vu_long *)0xFE200018
+#define SH7751_PCICR (vu_long *)0xFE200100
+#define SH7751_PCILSR0 (vu_long *)0xFE200104
+#define SH7751_PCILSR1 (vu_long *)0xFE200108
+#define SH7751_PCILAR0 (vu_long *)0xFE20010C
+#define SH7751_PCILAR1 (vu_long *)0xFE200110
+#define SH7751_PCIMBR (vu_long *)0xFE2001C4
+#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
+#define SH7751_PCIPINT (vu_long *)0xFE2001CC
+#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
+#define SH7751_PCICLKR (vu_long *)0xFE2001D4
+#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
+#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
+#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
+#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
+#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
+#define SH7751_PCIMCR (vu_long *)0xFE2001F4
+#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
+
+#define BCR1_BREQEN 0x00080000
+#define PCI_SH7751_ID 0x35051054
+#define PCI_SH7751R_ID 0x350E1054
+#define SH7751_PCICONF1_WCC 0x00000080
+#define SH7751_PCICONF1_PER 0x00000040
+#define SH7751_PCICONF1_BUM 0x00000004
+#define SH7751_PCICONF1_MES 0x00000002
+#define SH7751_PCICONF1_CMDS 0x000000C6
+#define SH7751_PCI_HOST_BRIDGE 0x6
+#define SH7751_PCICR_PREFIX 0xa5000000
+#define SH7751_PCICR_PRST 0x00000002
+#define SH7751_PCICR_CFIN 0x00000001
+#define SH7751_PCIPINT_D3 0x00000002
+#define SH7751_PCIPINT_D0 0x00000001
+#define SH7751_PCICLKR_PREFIX 0xa5000000
+
+#define SH7751_PCI_MEM_BASE 0xFD000000
+#define SH7751_PCI_MEM_SIZE 0x01000000
+#define SH7751_PCI_IO_BASE 0xFE240000
+#define SH7751_PCI_IO_SIZE 0x00040000
+
+#define SH7751_CS3_BASE_ADDR 0x0C000000
+#define SH7751_P2CS3_BASE_ADDR 0xAC000000
+
+#define SH7751_PCIPAR (vu_long *)0xFE2001C0
+#define SH7751_PCIPDR (vu_long *)0xFE200220
+
+#define p4_in(addr) *(addr)
+#define p4_out(data,addr) *(addr) = (data)
+
+/* Double word */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 * value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
+ *value = p4_in(SH7751_PCIPDR);
+
+ return 0;
+}
+
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 * value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
+ p4_out(value, SH7751_PCIPDR);
+
+ return 0;
+}
+
+int pci_sh7751_init(struct pci_controller *hose)
+{
+ /* Double-check that we're a 7751 or 7751R chip */
+ if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
+ && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
+ printf("PCI: Unknown PCI host bridge.\n");
+ return 1;
+ }
+ printf("PCI: SH7751 PCI host bridge found.\n");
+
+ /* Double-check some BSC config settings */
+ /* (Area 3 non-MPX 32-bit, PCI bus pins) */
+ if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
+ printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+ return 2;
+ }
+ if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
+ printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+ return 3;
+ }
+ if (p4_in(SH7751_BCR2) & 0x01) {
+ printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+ return 4;
+ }
+
+ /* Force BREQEN in BCR1 to allow PCIC access */
+ p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
+
+ /* Toggle PCI reset pin */
+ p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
+ udelay(32);
+ p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
+
+ /* Set cmd bits: WCC, PER, BUM, MES */
+ /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
+ p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
+
+ /* Define this host as the host bridge */
+ p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
+
+ /* Force PCI clock(s) on */
+ p4_out(0, SH7751_PCICLKR);
+ p4_out(0x03, SH7751_PCICLKR);
+
+ /* Clear powerdown IRQs, also mask them (unused) */
+ p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
+ p4_out(0, SH7751_PCIPINTM);
+
+ p4_out(0xab000001, SH7751_PCICONF4);
+
+ /* Set up target memory mappings (for external DMA access) */
+ /* Map both P0 and P2 range to Area 3 RAM for ease of use */
+ p4_out((64 - 1) << 20, SH7751_PCILSR0);
+ p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
+ p4_out(0, SH7751_PCILSR1);
+ p4_out(0, SH7751_PCILAR1);
+ p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
+ p4_out(0xd0000000, SH7751_PCICONF6);
+
+ /* Map memory window to same address on PCI bus */
+ p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
+
+ /* Map IO window to same address on PCI bus */
+ p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
+
+ /* set BREQEN */
+ p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
+
+ /* Copy BSC registers into PCI BSC */
+ p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
+ p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2);
+ p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3);
+ p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
+ p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
+ p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
+ p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
+
+ /* Finally, set central function init complete */
+ p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
+
+ pci_sh4_init(hose);
+
+ return 0;
+}
diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c
new file mode 100644
index 0000000..d63d67d
--- /dev/null
+++ b/drivers/pci/pci_sh7780.c
@@ -0,0 +1,107 @@
+/*
+ * SH7780 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define SH7780_VENDOR_ID 0x1912
+#define SH7780_DEVICE_ID 0x0002
+#define SH7780_PCICR_PREFIX 0xA5000000
+#define SH7780_PCICR_PFCS 0x00000800
+#define SH7780_PCICR_FTO 0x00000400
+#define SH7780_PCICR_PFE 0x00000200
+#define SH7780_PCICR_TBS 0x00000100
+#define SH7780_PCICR_ARBM 0x00000040
+#define SH7780_PCICR_IOCS 0x00000004
+#define SH7780_PCICR_PRST 0x00000002
+#define SH7780_PCICR_CFIN 0x00000001
+
+#define p4_in(addr) *((vu_long *)addr)
+#define p4_out(data,addr) *(vu_long *)(addr) = (data)
+#define p4_inw(addr) *((vu_short *)addr)
+#define p4_outw(data,addr) *(vu_short *)(addr) = (data)
+
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 *value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
+ *value = p4_in(SH7780_PCIPDR);
+
+ return 0;
+}
+
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
+ p4_out(value, SH7780_PCIPDR);
+ return 0;
+}
+
+int pci_sh7780_init(struct pci_controller *hose)
+{
+ p4_out(0x01, SH7780_PCIECR);
+
+ if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
+ && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+ printf("PCI: Unknown PCI host bridge.\n");
+ return;
+ }
+ printf("PCI: SH7780 PCI host bridge found.\n");
+
+ /* Toggle PCI reset pin */
+ p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
+ udelay(100000);
+ p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
+ p4_outw(0x0047, SH7780_PCICMD);
+
+ p4_out(0x07F00001, SH7780_PCILSR0);
+ p4_out(0x08000000, SH7780_PCILAR0);
+ p4_out(0x00000000, SH7780_PCILSR1);
+ p4_out(0, SH7780_PCILAR1);
+ p4_out(0x08000000, SH7780_PCIMBAR0);
+ p4_out(0x00000000, SH7780_PCIMBAR1);
+
+ p4_out(0xFD000000, SH7780_PCIMBR0);
+ p4_out(0x00FC0000, SH7780_PCIMBMR0);
+
+ /* if use Operand Cache then enable PCICSCR Soonp bits. */
+ p4_out(0x08000000, SH7780_PCICSAR0);
+ p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
+
+ p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
+ | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
+ SH7780_PCICR);
+
+ pci_sh4_init(hose);
+ return 0;
+}
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 70fd23f..522f96d 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -37,39 +37,46 @@
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
-#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
-#define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
-#define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
+# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
+# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
#else
-#define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
-#define SCFSR (vu_short *)(SCIF_BASE + 0x10)
-#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
+# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
+# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
#endif
-#if defined(CONFIG_SH4A)
-#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
-#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
-#define SCLSR (vu_short *)(SCIF_BASE + 0x28)
-#define SCRER (vu_short *)(SCIF_BASE + 0x2C)
-#define LSR_ORER 1
-#elif defined (CONFIG_SH4)
-#define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
-#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-#define LSR_ORER 1
-#elif defined (CONFIG_SH3)
-#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
-#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-#define LSR_ORER 0x0200
-#else
-#define SCLSR SCFSR /* SCSSR */
-#define LSR_ORER 1
-#endif
+#if defined(CONFIG_CPU_SH7780) || \
+ defined(CONFIG_CPU_SH7785)
+# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
+# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
+# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0xFF
+#elif defined(CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751) || \
+ defined(CONFIG_CPU_SH7722)
+# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0x1F
+#elif defined(CONFIG_CPU_SH7720)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER 0x0200
+# define FIFOLEVEL_MASK 0x1F
+#elif defined(CONFIG_CPU_SH7710)
+ defined(CONFIG_CPU_SH7712)
+# define SCLSR SCFSR /* SCSSR */
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0x1F
#endif
+/* SCBRR register value setting */
#if defined(CONFIG_CPU_SH7720)
-#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#else /* Generic SuperH */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
#define SCR_RE (1 << 4)
@@ -105,14 +112,13 @@ int serial_init (void)
return 0;
}
-static int serial_tx_fifo_level (void)
-{
- return (*SCFDR >> 8) & 0x1F;
-}
-
static int serial_rx_fifo_level (void)
{
- return (*SCFDR >> 0) & 0x1F;
+#if defined(CONFIG_SH4A)
+ return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+#else
+ return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+#endif
}
void serial_raw_putc (const char c)
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
new file mode 100644
index 0000000..67474c7
--- /dev/null
+++ b/include/asm-sh/cache.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+
+#define L1_CACHE_BYTES 32
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+void dcache_wback_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES-1);
+ for (v = start; v < end; v+=L1_CACHE_BYTES) {
+ asm volatile("ocbwb %0"
+ : /* no output */
+ : "m" (__m(v)));
+ }
+}
+
+void dcache_invalid_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES-1);
+ for (v = start; v < end; v+=L1_CACHE_BYTES) {
+ asm volatile("ocbi %0"
+ : /* no output */
+ : "m" (__m(v)));
+ }
+}
+#endif /* CONFIG_SH4 || CONFIG_SH4A */
+
+#endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
index 2658039..c200ba5 100644
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -30,12 +30,15 @@
#define CACHE_OC_NUM_ENTRIES 512
#define CACHE_OC_ENTRY_SHIFT 5
-#if defined (CONFIG_CPU_SH7750)
-#include <asm/cpu_sh7750.h>
+#if defined (CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751)
+# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
-#include <asm/cpu_sh7722.h>
+# include <asm/cpu_sh7722.h>
+#elif defined (CONFIG_CPU_SH7780)
+# include <asm/cpu_sh7780.h>
#else
-#error "Unknown SH4 variant"
+# error "Unknown SH4 variant"
#endif
#endif /* _ASM_CPU_SH4_H_ */
diff --git a/include/asm-sh/cpu_sh7720.h b/include/asm-sh/cpu_sh7720.h
index bafb8de..1b393b8 100644
--- a/include/asm-sh/cpu_sh7720.h
+++ b/include/asm-sh/cpu_sh7720.h
@@ -1,5 +1,9 @@
/*
- * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ * Copyright 2007 (C)
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright 2008 (C)
+ * Mark Jonas <mark.jonas@de.bosch.com>
*
* SH7720 Internal I/O register
*
@@ -201,6 +205,25 @@
#define PSELD (PFC_BASE + 0x2A)
/* I/O Port */
+#define PORT_BASE 0xA4050100
+#define PADR (PORT_BASE + 0x40)
+#define PBDR (PORT_BASE + 0x42)
+#define PCDR (PORT_BASE + 0x44)
+#define PDDR (PORT_BASE + 0x46)
+#define PEDR (PORT_BASE + 0x48)
+#define PFDR (PORT_BASE + 0x4A)
+#define PGDR (PORT_BASE + 0x4C)
+#define PHDR (PORT_BASE + 0x4E)
+#define PJDR (PORT_BASE + 0x50)
+#define PKDR (PORT_BASE + 0x52)
+#define PLDR (PORT_BASE + 0x54)
+#define PMDR (PORT_BASE + 0x56)
+#define PPDR (PORT_BASE + 0x58)
+#define PRDR (PORT_BASE + 0x5A)
+#define PSDR (PORT_BASE + 0x5C)
+#define PTDR (PORT_BASE + 0x5E)
+#define PUDR (PORT_BASE + 0x60)
+#define PVDR (PORT_BASE + 0x62)
/* H-UDI */
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
index bb6461a..3c3c309 100644
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@@ -25,10 +25,10 @@
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
-#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
+#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */
diff --git a/include/asm-sh/cpu_sh7780.h b/include/asm-sh/cpu_sh7780.h
new file mode 100644
index 0000000..d4f824e
--- /dev/null
+++ b/include/asm-sh/cpu_sh7780.h
@@ -0,0 +1,503 @@
+#ifndef _ASM_CPU_SH7780_H_
+#define _ASM_CPU_SH7780_H_
+
+/*
+ * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
+ * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#define CACHE_OC_NUM_WAYS 1
+#define CCR_CACHE_INIT 0x0000090b
+
+/* Exceptions */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* Memory Management Unit */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define PASCR 0xFF000070
+#define IRMCR 0xFF000078
+
+/* Cache Controller */
+#define CCR 0xFF00001C
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
+#define RAMCR 0xFF000074
+
+/* L Memory */
+#define RAMCR 0xFF000074
+#define LSA0 0xFF000050
+#define LSA1 0xFF000054
+#define LDA0 0xFF000058
+#define LDA1 0xFF00005C
+
+/* Interrupt Controller */
+#define ICR0 0xFFD00000
+#define ICR1 0xFFD0001C
+#define INTPRI 0xFFD00010
+#define INTREQ 0xFFD00024
+#define INTMSK0 0xFFD00044
+#define INTMSK1 0xFFD00048
+#define INTMSK2 0xFFD40080
+#define INTMSKCLR0 0xFFD00064
+#define INTMSKCLR1 0xFFD00068
+#define INTMSKCLR2 0xFFD40084
+#define NMIFCR 0xFFD000C0
+#define USERIMASK 0xFFD30000
+#define INT2PRI0 0xFFD40000
+#define INT2PRI1 0xFFD40004
+#define INT2PRI2 0xFFD40008
+#define INT2PRI3 0xFFD4000C
+#define INT2PRI4 0xFFD40010
+#define INT2PRI5 0xFFD40014
+#define INT2PRI6 0xFFD40018
+#define INT2PRI7 0xFFD4001C
+#define INT2A0 0xFFD40030
+#define INT2A1 0xFFD40034
+#define INT2MSKR 0xFFD40038
+#define INT2MSKCR 0xFFD4003C
+#define INT2B0 0xFFD40040
+#define INT2B1 0xFFD40044
+#define INT2B2 0xFFD40048
+#define INT2B3 0xFFD4004C
+#define INT2B4 0xFFD40050
+#define INT2B5 0xFFD40054
+#define INT2B6 0xFFD40058
+#define INT2B7 0xFFD4005C
+#define INT2GPIC 0xFFD40090
+
+/* local Bus State Controller */
+#define MMSELR 0xFF400020
+#define BCR 0xFF801000
+#define CS0BCR 0xFF802000
+#define CS1BCR 0xFF802010
+#define CS2BCR 0xFF802020
+#define CS4BCR 0xFF802040
+#define CS5BCR 0xFF802050
+#define CS6BCR 0xFF802060
+#define CS0WCR 0xFF802008
+#define CS1WCR 0xFF802018
+#define CS2WCR 0xFF802028
+#define CS4WCR 0xFF802048
+#define CS5WCR 0xFF802058
+#define CS6WCR 0xFF802068
+#define CS5PCR 0xFF802070
+#define CS6PCR 0xFF802080
+
+/* DDR-SDRAM I/F */
+#define MIM_1 0xFE800008
+#define MIM_2 0xFE80000C
+#define SCR_1 0xFE800010
+#define SCR_2 0xFE800014
+#define STR_1 0xFE800018
+#define STR_2 0xFE80001C
+#define SDR_1 0xFE800030
+#define SDR_2 0xFE800034
+#define DBK_1 0xFE800400
+#define DBK_2 0xFE800404
+
+/* PCI Controller */
+#define SH7780_PCIECR 0xFE000008
+#define SH7780_PCIVID 0xFE040000
+#define SH7780_PCIDID 0xFE040002
+#define SH7780_PCICMD 0xFE040004
+#define SH7780_PCISTATUS 0xFE040006
+#define SH7780_PCIRID 0xFE040008
+#define SH7780_PCIPIF 0xFE040009
+#define SH7780_PCISUB 0xFE04000A
+#define SH7780_PCIBCC 0xFE04000B
+#define SH7780_PCICLS 0xFE04000C
+#define SH7780_PCILTM 0xFE04000D
+#define SH7780_PCIHDR 0xFE04000E
+#define SH7780_PCIBIST 0xFE04000F
+#define SH7780_PCIIBAR 0xFE040010
+#define SH7780_PCIMBAR0 0xFE040014
+#define SH7780_PCIMBAR1 0xFE040018
+#define SH7780_PCISVID 0xFE04002C
+#define SH7780_PCISID 0xFE04002E
+#define SH7780_PCICP 0xFE040034
+#define SH7780_PCIINTLINE 0xFE04003C
+#define SH7780_PCIINTPIN 0xFE04003D
+#define SH7780_PCIMINGNT 0xFE04003E
+#define SH7780_PCIMAXLAT 0xFE04003F
+#define SH7780_PCICID 0xFE040040
+#define SH7780_PCINIP 0xFE040041
+#define SH7780_PCIPMC 0xFE040042
+#define SH7780_PCIPMCSR 0xFE040044
+#define SH7780_PCIPMCSRBSE 0xFE040046
+#define SH7780_PCI_CDD 0xFE040047
+#define SH7780_PCICR 0xFE040100
+#define SH7780_PCILSR0 0xFE040104
+#define SH7780_PCILSR1 0xFE040108
+#define SH7780_PCILAR0 0xFE04010C
+#define SH7780_PCILAR1 0xFE040110
+#define SH7780_PCIIR 0xFE040114
+#define SH7780_PCIIMR 0xFE040118
+#define SH7780_PCIAIR 0xFE04011C
+#define SH7780_PCICIR 0xFE040120
+#define SH7780_PCIAINT 0xFE040130
+#define SH7780_PCIAINTM 0xFE040134
+#define SH7780_PCIBMIR 0xFE040138
+#define SH7780_PCIPAR 0xFE0401C0
+#define SH7780_PCIPINT 0xFE0401CC
+#define SH7780_PCIPINTM 0xFE0401D0
+#define SH7780_PCIMBR0 0xFE0401E0
+#define SH7780_PCIMBMR0 0xFE0401E4
+#define SH7780_PCIMBR1 0xFE0401E8
+#define SH7780_PCIMBMR1 0xFE0401EC
+#define SH7780_PCIMBR2 0xFE0401F0
+#define SH7780_PCIMBMR2 0xFE0401F4
+#define SH7780_PCIIOBR 0xFE0401F8
+#define SH7780_PCIIOBMR 0xFE0401FC
+#define SH7780_PCICSCR0 0xFE040210
+#define SH7780_PCICSCR1 0xFE040214
+#define SH7780_PCICSAR0 0xFE040218
+#define SH7780_PCICSAR1 0xFE04021C
+#define SH7780_PCIPDR 0xFE040220
+
+/* DMAC */
+#define DMAC_SAR0 0xFC808020
+#define DMAC_DAR0 0xFC808024
+#define DMAC_TCR0 0xFC808028
+#define DMAC_CHCR0 0xFC80802C
+#define DMAC_SAR1 0xFC808030
+#define DMAC_DAR1 0xFC808034
+#define DMAC_TCR1 0xFC808038
+#define DMAC_CHCR1 0xFC80803C
+#define DMAC_SAR2 0xFC808040
+#define DMAC_DAR2 0xFC808044
+#define DMAC_TCR2 0xFC808048
+#define DMAC_CHCR2 0xFC80804C
+#define DMAC_SAR3 0xFC808050
+#define DMAC_DAR3 0xFC808054
+#define DMAC_TCR3 0xFC808058
+#define DMAC_CHCR3 0xFC80805C
+#define DMAC_DMAOR0 0xFC808060
+#define DMAC_SAR4 0xFC808070
+#define DMAC_DAR4 0xFC808074
+#define DMAC_TCR4 0xFC808078
+#define DMAC_CHCR4 0xFC80807C
+#define DMAC_SAR5 0xFC808080
+#define DMAC_DAR5 0xFC808084
+#define DMAC_TCR5 0xFC808088
+#define DMAC_CHCR5 0xFC80808C
+#define DMAC_SARB0 0xFC808120
+#define DMAC_DARB0 0xFC808124
+#define DMAC_TCRB0 0xFC808128
+#define DMAC_SARB1 0xFC808130
+#define DMAC_DARB1 0xFC808134
+#define DMAC_TCRB1 0xFC808138
+#define DMAC_SARB2 0xFC808140
+#define DMAC_DARB2 0xFC808144
+#define DMAC_TCRB2 0xFC808148
+#define DMAC_SARB3 0xFC808150
+#define DMAC_DARB3 0xFC808154
+#define DMAC_TCRB3 0xFC808158
+#define DMAC_DMARS0 0xFC809000
+#define DMAC_DMARS1 0xFC809004
+#define DMAC_DMARS2 0xFC809008
+#define DMAC_SAR6 0xFC818020
+#define DMAC_DAR6 0xFC818024
+#define DMAC_TCR6 0xFC818028
+#define DMAC_CHCR6 0xFC81802C
+#define DMAC_SAR7 0xFC818030
+#define DMAC_DAR7 0xFC818034
+#define DMAC_TCR7 0xFC818038
+#define DMAC_CHCR7 0xFC81803C
+#define DMAC_SAR8 0xFC818040
+#define DMAC_DAR8 0xFC818044
+#define DMAC_TCR8 0xFC818048
+#define DMAC_CHCR8 0xFC81804C
+#define DMAC_SAR9 0xFC818050
+#define DMAC_DAR9 0xFC818054
+#define DMAC_TCR9 0xFC818058
+#define DMAC_CHCR9 0xFC81805C
+#define DMAC_DMAOR1 0xFC818060
+#define DMAC_SAR10 0xFC818070
+#define DMAC_DAR10 0xFC818074
+#define DMAC_TCR10 0xFC818078
+#define DMAC_CHCR10 0xFC81807C
+#define DMAC_SAR11 0xFC818080
+#define DMAC_DAR11 0xFC818084
+#define DMAC_TCR11 0xFC818088
+#define DMAC_CHCR11 0xFC81808C
+#define DMAC_SARB6 0xFC818120
+#define DMAC_DARB6 0xFC818124
+#define DMAC_TCRB6 0xFC818128
+#define DMAC_SARB7 0xFC818130
+#define DMAC_DARB7 0xFC818134
+#define DMAC_TCRB7 0xFC818138
+#define DMAC_SARB8 0xFC818140
+#define DMAC_DARB8 0xFC818144
+#define DMAC_TCRB8 0xFC818148
+#define DMAC_SARB9 0xFC818150
+#define DMAC_DARB9 0xFC818154
+#define DMAC_TCRB9 0xFC818158
+
+/* Clock Pulse Generator */
+#define FRQCR 0xFFC80000
+#define PLLCR 0xFFC80024
+#define MSTPCR 0xFFC80030
+
+/* Watchdog Timer and Reset */
+#define WTCNT WDTCNT
+#define WDTST 0xFFCC0000
+#define WDTCSR 0xFFCC0004
+#define WDTBST 0xFFCC0008
+#define WDTCNT 0xFFCC0010
+#define WDTBCNT 0xFFCC0018
+
+/* System Control */
+#define MSTPCR 0xFFC80030
+
+/* Timer Unit */
+#define TSTR TSTR0
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
+#define TSTR1 0xFFDC0004
+#define TCOR3 0xFFDC0008
+#define TCNT3 0xFFDC000C
+#define TCR3 0xFFDC0010
+#define TCOR4 0xFFDC0014
+#define TCNT4 0xFFDC0018
+#define TCR4 0xFFDC001C
+#define TCOR5 0xFFDC0020
+#define TCNT5 0xFFDC0024
+#define TCR5 0xFFDC0028
+
+/* Timer/Counter */
+#define CMTCFG 0xFFE30000
+#define CMTFRT 0xFFE30004
+#define CMTCTL 0xFFE30008
+#define CMTIRQS 0xFFE3000C
+#define CMTCH0T 0xFFE30010
+#define CMTCH0ST 0xFFE30020
+#define CMTCH0C 0xFFE30030
+#define CMTCH1T 0xFFE30014
+#define CMTCH1ST 0xFFE30024
+#define CMTCH1C 0xFFE30034
+#define CMTCH2T 0xFFE30018
+#define CMTCH2C 0xFFE30038
+#define CMTCH3T 0xFFE3001C
+#define CMTCH3C 0xFFE3003C
+
+/* Realtime Clock */
+#define R64CNT 0xFFE80000
+#define RSECCNT 0xFFE80004
+#define RMINCNT 0xFFE80008
+#define RHRCNT 0xFFE8000C
+#define RWKCNT 0xFFE80010
+#define RDAYCNT 0xFFE80014
+#define RMONCNT 0xFFE80018
+#define RYRCNT 0xFFE8001C
+#define RSECAR 0xFFE80020
+#define RMINAR 0xFFE80024
+#define RHRAR 0xFFE80028
+#define RWKAR 0xFFE8002C
+#define RDAYAR 0xFFE80030
+#define RMONAR 0xFFE80034
+#define RCR1 0xFFE80038
+#define RCR2 0xFFE8003C
+#define RCR3 0xFFE80050
+#define RYRAR 0xFFE80054
+
+/* Serial Communication Interface with FIFO */
+#define SCIF0_BASE SCSMR0
+#define SCSMR0 0xFFE00000
+#define SCBRR0 0xFFE00004
+#define SCSCR0 0xFFE00008
+#define SCFSR0 0xFFE00010
+#define SCFCR0 0xFFE00018
+#define SCTFDR0 0xFFE0001C
+#define SCRFDR0 0xFFE00020
+#define SCSPTR0 0xFFE00024
+#define SCLSR0 0xFFE00028
+#define SCRER0 0xFFE0002C
+#define SCSMR1 0xFFE10000
+#define SCBRR1 0xFFE10004
+#define SCSCR1 0xFFE10008
+#define SCFSR1 0xFFE10010
+#define SCFCR1 0xFFE10018
+#define SCTFDR1 0xFFE1001C
+#define SCRFDR1 0xFFE10020
+#define SCSPTR1 0xFFE10024
+#define SCLSR1 0xFFE10028
+#define SCRER1 0xFFE1002C
+
+/* Serial I/O with FIFO */
+#define SIMDR 0xFFE20000
+#define SISCR 0xFFE20002
+#define SITDAR 0xFFE20004
+#define SIRDAR 0xFFE20006
+#define SICDAR 0xFFE20008
+#define SICTR 0xFFE2000C
+#define SIFCTR 0xFFE20010
+#define SISTR 0xFFE20014
+#define SIIER 0xFFE20016
+#define SITCR 0xFFE20028
+#define SIRCR 0xFFE2002C
+#define SPICR 0xFFE20030
+
+/* Serial Protocol Interface */
+#define SPCR 0xFFE50000
+#define SPSR 0xFFE50004
+#define SPSCR 0xFFE50008
+#define SPTBR 0xFFE5000C
+#define SPRBR 0xFFE50010
+
+/* Multimedia Card Interface */
+#define CMDR0 0xFFE60000
+#define CMDR1 0xFFE60001
+#define CMDR2 0xFFE60002
+#define CMDR3 0xFFE60003
+#define CMDR4 0xFFE60004
+#define CMDR5 0xFFE60005
+#define CMDSTRT 0xFFE60006
+#define OPCR 0xFFE6000A
+#define CSTR 0xFFE6000B
+#define INTCR0 0xFFE6000C
+#define INTCR1 0xFFE6000D
+#define INTSTR0 0xFFE6000E
+#define INTSTR1 0xFFE6000F
+#define CLKON 0xFFE60010
+#define CTOCR 0xFFE60011
+#define TBCR 0xFFE60014
+#define MODER 0xFFE60016
+#define CMDTYR 0xFFE60018
+#define RSPTYR 0xFFE60019
+#define TBNCR 0xFFE6001A
+#define RSPR0 0xFFE60020
+#define RSPR1 0xFFE60021
+#define RSPR2 0xFFE60022
+#define RSPR3 0xFFE60023
+#define RSPR4 0xFFE60024
+#define RSPR5 0xFFE60025
+#define RSPR6 0xFFE60026
+#define RSPR7 0xFFE60027
+#define RSPR8 0xFFE60028
+#define RSPR9 0xFFE60029
+#define RSPR10 0xFFE6002A
+#define RSPR11 0xFFE6002B
+#define RSPR12 0xFFE6002C
+#define RSPR13 0xFFE6002D
+#define RSPR14 0xFFE6002E
+#define RSPR15 0xFFE6002F
+#define RSPR16 0xFFE60030
+#define RSPRD 0xFFE60031
+#define DTOUTR 0xFFE60032
+#define DR 0xFFE60040
+#define DMACR 0xFFE60044
+#define INTCR2 0xFFE60046
+#define INTSTR2 0xFFE60048
+
+/* Audio Codec Interface */
+#define HACCR 0xFFE40008
+#define HACCSAR 0xFFE40020
+#define HACCSDR 0xFFE40024
+#define HACPCML 0xFFE40028
+#define HACPCMR 0xFFE4002C
+#define HACTIER 0xFFE40050
+#define HACTSR 0xFFE40054
+#define HACRIER 0xFFE40058
+#define HACRSR 0xFFE4005C
+#define HACACR 0xFFE40060
+
+/* Serial Sound Interface */
+#define SSICR 0xFFE70000
+#define SSISR 0xFFE70004
+#define SSITDR 0xFFE70008
+#define SSIRDR 0xFFE7000C
+
+/* Flash memory Controller */
+#define FLCMNCR 0xFFE90000
+#define FLCMDCR 0xFFE90004
+#define FLCMCDR 0xFFE90008
+#define FLADR 0xFFE9000C
+#define FLDATAR 0xFFE90010
+#define FLDTCNTR 0xFFE90014
+#define FLINTDMACR 0xFFE90018
+#define FLBSYTMR 0xFFE9001C
+#define FLBSYCNT 0xFFE90020
+#define FLTRCR 0xFFE9002C
+
+/* General Purpose I/O */
+#define PACR 0xFFEA0000
+#define PBCR 0xFFEA0002
+#define PCCR 0xFFEA0004
+#define PDCR 0xFFEA0006
+#define PECR 0xFFEA0008
+#define PFCR 0xFFEA000A
+#define PGCR 0xFFEA000C
+#define PHCR 0xFFEA000E
+#define PJCR 0xFFEA0010
+#define PKCR 0xFFEA0012
+#define PLCR 0xFFEA0014
+#define PMCR 0xFFEA0016
+#define PADR 0xFFEA0020
+#define PBDR 0xFFEA0022
+#define PCDR 0xFFEA0024
+#define PDDR 0xFFEA0026
+#define PEDR 0xFFEA0028
+#define PFDR 0xFFEA002A
+#define PGDR 0xFFEA002C
+#define PHDR 0xFFEA002E
+#define PJDR 0xFFEA0030
+#define PKDR 0xFFEA0032
+#define PLDR 0xFFEA0034
+#define PMDR 0xFFEA0036
+#define PEPUPR 0xFFEA0048
+#define PHPUPR 0xFFEA004E
+#define PJPUPR 0xFFEA0050
+#define PKPUPR 0xFFEA0052
+#define PMPUPR 0xFFEA0056
+#define PPUPR1 0xFFEA0060
+#define PPUPR2 0xFFEA0062
+#define PMSELR 0xFFEA0080
+
+/* User Break Controller */
+#define CBR0 0xFF200000
+#define CRR0 0xFF200004
+#define CAR0 0xFF200008
+#define CAMR0 0xFF20000C
+#define CBR1 0xFF200020
+#define CRR1 0xFF200024
+#define CAR1 0xFF200028
+#define CAMR1 0xFF20002C
+#define CDR1 0xFF200030
+#define CDMR1 0xFF200034
+#define CETR1 0xFF200038
+#define CCMFR 0xFF200600
+#define CBCR 0xFF200620
+
+#endif /* _ASM_CPU_SH7780_H_ */
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
new file mode 100644
index 0000000..bc59491
--- /dev/null
+++ b/include/asm-sh/pci.h
@@ -0,0 +1,47 @@
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/include/asm-sh/pci.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_PCI_H_
+#define _ASM_PCI_H_
+
+#include <pci.h>
+#if defined(CONFIG_SH7751_PCI)
+int pci_sh7751_init(struct pci_controller *hose);
+#elif defined(CONFIG_SH7780_PCI)
+int pci_sh7780_init(struct pci_controller *hose);
+#else
+#error "Not support PCI."
+#endif
+
+/* PCI dword read for sh4 */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 *value);
+
+/* PCI dword write for sh4 */
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value);
+
+#endif /* _ASM_PCI_H_ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index bb9a35f..388aa69 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -2,7 +2,8 @@
#define _ASM_SH_PROCESSOR_H_
#if defined CONFIG_SH3
# include <asm/cpu_sh3.h>
-#elif defined (CONFIG_SH4)
+#elif defined (CONFIG_SH4) || \
+ defined (CONFIG_SH4A)
# include <asm/cpu_sh4.h>
#endif
#endif
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
new file mode 100644
index 0000000..99e1179
--- /dev/null
+++ b/include/configs/MigoR.h
@@ -0,0 +1,151 @@
+/*
+ * Configuation settings for the Renesas Solutions Migo-R board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MIGO_R_H
+#define __MIGO_R_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7722 1
+#define CONFIG_MIGO_R 1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.10.100
+#define CONFIG_SERVERIP 192.168.10.77
+#define CONFIG_GATEWAYIP 192.168.10.77
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE (0xB0000000)
+
+/* MEMORY */
+#define MIGO_R_SDRAM_BASE (0x8C000000)
+#define MIGO_R_FLASH_BASE_1 (0xA0000000)
+#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console
+ information at boot */
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START (MIGO_R_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef CFG_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef CFG_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE (MIGO_R_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
+/* Monitor size */
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CFG_FLASH_BASE (MIGO_R_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CFG_MAX_FLASH_SECT 512
+
+/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
+
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef CFG_FLASH_PROTECTION
+#undef CFG_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __MIGO_R_H */
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
new file mode 100644
index 0000000..0fc0b97
--- /dev/null
+++ b/include/configs/mpr2.h
@@ -0,0 +1,92 @@
+/*
+ * Configuation settings for MPR2
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPR2_H
+#define __MPR2_H
+
+/* Supported commands */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+
+/* Default environment variables */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_BOOTFILE /boot/zImage
+#define CONFIG_LOADADDR 0x8E000000
+#define CONFIG_VERSION_VARIABLE
+
+/* CPU and platform */
+#define CONFIG_SH 1
+#define CONFIG_SH3 1
+#define CONFIG_CPU_SH7720 1
+#define CONFIG_MPR2 1
+
+/* U-Boot internals */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_GBL_DATA_SIZE 256
+
+/* Memory */
+#define CFG_SDRAM_BASE 0x8C000000
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_BASE 0xA0000000
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Clocks */
+#define CONFIG_SYS_CLK_FREQ 24000000
+#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* UART */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+
+#endif /* __MPR2_H */
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
new file mode 100644
index 0000000..c20baca
--- /dev/null
+++ b/include/configs/r2dplus.h
@@ -0,0 +1,150 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7751 1
+#define CONFIG_CPU_SH_TYPE_R 1
+#define CONFIG_R2DPLUS 1
+#define __LITTLE_ENDIAN__ 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF1 1
+#define BOARD_LATE_INIT 1
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* Network setting */
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_IPADDR 10.0.192.51
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE (0x8C000000)
+#define CFG_SDRAM_SIZE (0x04000000)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/*
+ * NOR Flash
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_R2DPLUS_OLD)
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_MAX_FLASH_BANKS (1) /* Max number of
+ * Flash memory banks
+ */
+#define CFG_MAX_FLASH_SECT 142
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#else /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT 270
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+ CFG_FLASH_BASE + 0x100000,\
+ CFG_FLASH_BASE + 0x400000,\
+ CFG_FLASH_BASE + 0x700000, }
+#endif /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ 60000000
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CFG_PLL_SETTLING_TIME 100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xb4000000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7751_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
+
+/*
+ * Network device (RTL8139) support
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
+#define _IO_BASE 0x00000000
+#define KSEG1ADDR(x) (x)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
new file mode 100644
index 0000000..42787f4
--- /dev/null
+++ b/include/configs/r7780mp.h
@@ -0,0 +1,165 @@
+/*
+ * Configuation settings for the Renesas R7780MP board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __R7780RP_H
+#define __R7780RP_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4A 1
+#define CONFIG_CPU_SH7780 1
+#define CONFIG_R7780MP 1
+#define __LITTLE_ENDIAN 1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF0 1
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* check for keypress on bootdelay==0 */
+/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
+
+/* Network setting */
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_IPADDR 10.0.192.82
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+
+#define CFG_SDRAM_BASE (0x08000000)
+#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+/* NOR Flash (S29PL127J60TFI130) */
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT 270
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+ CFG_FLASH_BASE + 0x100000,\
+ CFG_FLASH_BASE + 0x400000,\
+ CFG_FLASH_BASE + 0x700000, }
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (112 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+#define CFG_RX_ETH_BUFFER (8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (16 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* PCI Controller */
+#if defined(CONFIG_CMD_PCI)
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
+#endif /* CONFIG_CMD_PCI */
+
+#if defined(CONFIG_CMD_NET)
+/* #define CONFIG_NET_MULTI
+ #define CONFIG_RTL8169 */
+/* AX88696L Support(NE2000 base chip) */
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_AX88796L
+#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
+#endif
+
+/* Compact flash Support */
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xb4000000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#endif /* CONFIG_CMD_IDE */
+
+#endif /* __R7780RP_H */
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 37f2924..2ce1c25 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -126,7 +126,7 @@ struct stat {
#endif /* __MIPS__ */
-#if defined(__AVR32__)
+#if defined(__AVR32__) || defined(__SH__)
struct stat {
unsigned long st_dev;
@@ -149,7 +149,7 @@ struct stat {
unsigned long __unused5;
};
-#endif /* __AVR32__ */
+#endif /* __AVR32__ || __SH__ */
#ifdef __cplusplus
}
diff --git a/lib_sh/board.c b/lib_sh/board.c
index 2cd60d7..883c381 100644
--- a/lib_sh/board.c
+++ b/lib_sh/board.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007
+ * Copyright (C) 2007,2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
@@ -95,6 +95,14 @@ static int sh_marubun_init(void)
}
#endif /* (CONFIG_CMD_IDE) */
+#if defined(CONFIG_PCI)
+static int sh_pci_init(void)
+{
+ pci_init();
+ return 0;
+}
+#endif /* CONFIG_PCI */
+
static int sh_mem_env_init(void)
{
mem_malloc_init();
@@ -141,6 +149,9 @@ init_fnc_t *init_sequence[] =
#if defined(CONFIG_CMD_NAND)
sh_nand_init, /* Flash memory (NAND) init */
#endif
+#if defined(CONFIG_PCI)
+ sh_pci_init, /* PCI Init */
+#endif
devices_init,
console_init_r,
interrupt_init,