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authorGrant Erickson <gerickson@nuovations.com>2008-07-09 11:55:46 -0700
committerStefan Roese <sr@denx.de>2008-07-11 13:18:12 +0200
commit5b457d00730d4aa0c6450d21a9104723e606fb98 (patch)
tree3f89dc42f698f5f891a3fba0d712fc705b61c2c3
parent0ce5c8675bb2c61f1d71fb97f0bbe822663fb93d (diff)
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PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)
While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in the 405EX(r), SDRAM_MCSTAT has a different DCR value. Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF which causes SDRAM initialization to periodically fail since it can prematurely indicate SDRAM ready status. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--include/asm-ppc/ppc4xx-sdram.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index cdccd8f..59f1c30 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -354,7 +354,11 @@
/*
* Memory controller registers
*/
+#ifndef CONFIG_405EX
#define SDRAM_MCSTAT 0x14 /* memory controller status */
+#else
+#define SDRAM_MCSTAT 0x1F /* memory controller status */
+#endif
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */