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authorDave Gerlach <d-gerlach@ti.com>2014-02-18 07:31:59 -0500
committerTom Rini <trini@ti.com>2014-03-04 09:42:07 -0500
commit4800be4a0c0058fd1670576ec0872980f3ed78f5 (patch)
tree5f025d4db9398565de230a989a42e8d7ea7fd967
parent3a3939bf3d216900486748ffc330a33d565c242b (diff)
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ARM: AM43xx: EMIF: configure self-refresh entry delay
Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the desired delay in cycles that the EMIF waits without an access to enter self-refresh, in this case 8192 cycles. With this, code desiring to enter self refresh only has to toggle one bit to enable it. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index d05e666..4173a10 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -80,8 +80,8 @@ static void configure_mr(int nr, u32 cs)
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
- writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
- writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);