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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2013-10-07 11:46:56 +0900
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-12-06 21:03:35 +0100
commit3064d599afaed1e601479efa372a6e83d4ea9deb (patch)
tree91328188f830cefea0c2a7fcc2b24c2d745b02f2
parent375a4496ff250baf6e4b845c1ebf40e4b3c409a3 (diff)
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ARM: align MVBAR on 32 byte boundary
The lower 5 bit of MVBAR is UNK/SBZP. So, Monitor Vector Base Address must be 32-byte aligned. On the other hand, the secure monitor handler does not need 32-byte alignment. This commit moves ".algin 5" directive to the correct place. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
-rw-r--r--arch/arm/cpu/armv7/nonsec_virt.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 24b4c18..6367e09 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -14,6 +14,7 @@
.arch_extension sec
.arch_extension virt
+ .align 5
/* the vector table for secure state and HYP mode */
_monitor_vectors:
.word 0 /* reset */
@@ -32,7 +33,6 @@ _monitor_vectors:
* to non-secure state.
* We use only r0 and r1 here, due to constraints in the caller.
*/
- .align 5
_secure_monitor:
mrc p15, 0, r1, c1, c1, 0 @ read SCR
bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits