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| author | Ye.Li <B37916@freescale.com> | 2013-11-18 16:21:30 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-13 10:17:02 -0500 |
| commit | 2ead2f9501c6d2571e0f5365bd808ed7c73257ef (patch) | |
| tree | 55d9abffd2cd3ef37f31eadddacb45f3aa97c021 | |
| parent | e3b699dab2c92268799b56c28c6a8fcda4f6110b (diff) | |
| download | u-boot-imx-2ead2f9501c6d2571e0f5365bd808ed7c73257ef.zip u-boot-imx-2ead2f9501c6d2571e0f5365bd808ed7c73257ef.tar.gz u-boot-imx-2ead2f9501c6d2571e0f5365bd808ed7c73257ef.tar.bz2 | |
ENGR00315499-19 Fix eMMC fast boot hang issue
When booting in eMMC fast boot, the uboot v2013.04 always hangs.
The root cause is that MMC host does not exit from boot mode after
bootrom loading image. So the first command 'CMD0' sent
in uboot will pull down the CMD line to low and cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Signed-off-by: Ye Li <b37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 37 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 9 |
2 files changed, 37 insertions, 9 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4c3b93d..1f834d7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc + * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc. * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -47,20 +47,30 @@ struct fsl_esdhc { uint fevt; /* Force event register */ uint admaes; /* ADMA error status register */ uint adsaddr; /* ADMA system address register */ - char reserved2[160]; /* reserved */ + char reserved2[4]; + uint dllctrl; + uint dllstat; + uint clktunectrlstatus; + char reserved3[84]; + uint vendorspec; + uint mmcboot; + uint vendorspec2; + char reserved4[48]; uint hostver; /* Host controller version register */ - char reserved3[4]; /* reserved */ +#ifndef ARCH_MXC + char reserved5[4]; /* reserved */ uint dmaerraddr; /* DMA error address register */ - char reserved4[4]; /* reserved */ + char reserved6[4]; /* reserved */ uint dmaerrattr; /* DMA error attribute register */ - char reserved5[4]; /* reserved */ + char reserved7[4]; /* reserved */ uint hostcapblt2; /* Host controller capabilities register 2 */ - char reserved6[8]; /* reserved */ + char reserved8[8]; /* reserved */ uint tcr; /* Tuning control register */ - char reserved7[28]; /* reserved */ + char reserved9[28]; /* reserved */ uint sddirctl; /* SD direction control register */ - char reserved8[712]; /* reserved */ + char reserved10[712];/* reserved */ uint scr; /* eSDHC control register */ +#endif }; /* Return the XFERTYP flags for a given command and data packet */ @@ -484,6 +494,17 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000); +#if defined(CONFIG_FSL_USDHC) + /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ + esdhc_write32(®s->mmcboot, 0x0); + /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ + esdhc_write32(®s->mixctrl, 0x0); + esdhc_write32(®s->clktunectrlstatus, 0x0); + + /* Put VEND_SPEC to default value */ + esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); +#endif + #ifndef ARCH_MXC /* Enable cache snooping */ esdhc_write32(®s->scr, 0x00000040); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index a6e3a5d..b06aafb 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc + * Copyright 2007-2008, 2010-2013 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -29,6 +29,12 @@ #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 +#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809 + #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) #define IRQSTAT_AC12E (0x01000000) @@ -82,6 +88,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDSTB (0x00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) |