Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

7 files changed, 188 insertions, 73 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 48b3826..2d65157 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -22,6 +22,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <fsl_usb.h>
 #include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
@@ -605,7 +606,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 	{
-		ccsr_usb_phy_t *usb_phy1 =
+		struct ccsr_usb_phy __iomem *usb_phy1 =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 		out_be32(&usb_phy1->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
@@ -613,7 +614,7 @@ skip_l2:
 #endif
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 	{
-		ccsr_usb_phy_t *usb_phy2 =
+		struct ccsr_usb_phy __iomem *usb_phy2 =
 			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 		out_be32(&usb_phy2->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
@@ -635,7 +636,7 @@ skip_l2:
 #endif
 
 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
-		ccsr_usb_phy_t *usb_phy =
+		struct ccsr_usb_phy __iomem *usb_phy =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 		setbits_be32(&usb_phy->pllprg[1],
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index de6bd11..39d9409 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -13,8 +13,12 @@
 #include <asm/errno.h>
 #include "fsl_corenet2_serdes.h"
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 static u64 serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 static u64 serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 static u64 serdes3_prtcl_map;
 #endif
@@ -78,8 +82,12 @@ int is_serdes_configured(enum srds_prtcl device)
 {
 	u64 ret = 0;
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	ret |= (1ULL << device) & serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	ret |= (1ULL << device) & serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	ret |= (1ULL << device) & serdes3_prtcl_map;
 #endif
@@ -97,14 +105,18 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 	int i;
 
 	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	case FSL_SRDS_1:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	case FSL_SRDS_2:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 		break;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	case FSL_SRDS_3:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
@@ -163,14 +175,18 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 void fsl_serdes_init(void)
 {
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
 		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
 		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 89966e0..eb7cbbc 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -121,11 +121,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
 	const char *modes[] = { "host", "peripheral", "otg" };
 	const char *phys[] = { "ulpi", "utmi" };
-	const char *mode = NULL;
-	const char *phy_type = NULL;
 	const char *dr_mode_type = NULL;
 	const char *dr_phy_type = NULL;
-	char usb1_defined = 0;
 	int usb_mode_off = -1;
 	int usb_phy_off = -1;
 	char str[5];
@@ -159,12 +156,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 			dr_mode_type = modes[mode_idx];
 			dr_phy_type = phys[phy_idx];
 
-			/* use usb_dr_mode and usb_phy_type if
-			   usb1_defined = 0; these variables are to
-			   be deprecated */
-			if (!strcmp(str, "usb1"))
-				usb1_defined = 1;
-
 			if (mode_idx < 0 && phy_idx < 0) {
 				printf("WARNING: invalid phy or mode\n");
 				return;
@@ -183,19 +174,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 		if (usb_phy_off < 0)
 			return;
 	}
-
-	if (!usb1_defined) {
-		int usb_off = -1;
-		mode = getenv("usb_dr_mode");
-		phy_type = getenv("usb_phy_type");
-		if (mode || phy_type) {
-			printf("WARNING: usb_dr_mode and usb_phy_type "
-				"are to be deprecated soon. Use "
-				"hwconfig to set these values instead!!\n");
-			fdt_fixup_usb_mode_phy_type(blob, mode,
-				phy_type, usb_off);
-		}
-	}
 }
 #endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ce1bf05..e1fc0f7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -535,6 +535,8 @@
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SRDS_3
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
@@ -565,6 +567,8 @@
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 2ed384e..3a10d77 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2846,54 +2846,6 @@ typedef struct ccsr_pme {
 	u8	res4[0x400];
 } ccsr_pme_t;
 
-#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-struct ccsr_usb_port_ctrl {
-	u32	ctrl;
-	u32	drvvbuscfg;
-	u32	pwrfltcfg;
-	u32	sts;
-	u8	res_14[0xc];
-	u32	bistcfg;
-	u32	biststs;
-	u32	abistcfg;
-	u32	abiststs;
-	u8	res_30[0x10];
-	u32	xcvrprg;
-	u32	anaprg;
-	u32	anadrv;
-	u32	anasts;
-};
-
-typedef struct ccsr_usb_phy {
-	u32	id;
-	struct  ccsr_usb_port_ctrl port1;
-	u8	res_50[0xc];
-	u32	tvr;
-	u32	pllprg[4];
-	u8	res_70[0x4];
-	u32	anaccfg;
-	u32	dbg;
-	u8	res_7c[0x4];
-	struct  ccsr_usb_port_ctrl port2;
-	u8	res_dc[0x334];
-} ccsr_usb_phy_t;
-
-#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
-#else
-typedef struct ccsr_usb_phy {
-	u8	res0[0x18];
-	u32	usb_enable_override;
-	u8	res[0xe4];
-} ccsr_usb_phy_t;
-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
-#endif
-
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
 	u8	res0[0x543];
diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README
new file mode 100644
index 0000000..430f0824
--- /dev/null
+++ b/board/freescale/c29xpcie/README
@@ -0,0 +1,100 @@
+Overview
+=========
+C29XPCIE board is a series of Freescale PCIe add-in cards to perform
+as public key crypto accelerator or secure key management module.
+It includes C293PCIE board, C293PCIE board and C291PCIE board.
+The Freescale C29x family is a high performance crypto co-processor.
+It combines a single e500v2 core with necessary SEC engines.
+(maximum core frequency 1000/1200 MHz).
+
+The C29xPCIE board features are as follows:
+Memory subsystem:
+	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 64 Mbyte NOR flash single-chip memory
+	- 4 Gbyte NAND flash memory
+	- 1 Mbit AT24C1024 I2C EEPROM
+	- 16 Mbyte SPI memory
+
+Interfaces:
+	- 10/100/1000 BaseT Ethernet ports:
+		- eTSEC1, RGMII: one 10/100/1000 port
+		- eTSEC2, RGMII: one 10/100/1000 port
+	- DUART interface:
+		- DUART interface: supports two UARTs up to 115200 bps for
+		   console display
+
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+
+Physical Memory Map on C29xPCIE
+===============================
+Address Start   Address End   Memory type
+0x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
+0xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
+0xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
+0xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
+0xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
+0xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
+0xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR
+
+Serial Port Configuration on C29xPCIE
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+Settings of DIP-switch
+======================
+  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
+  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
+Note: 1 stands for 'off', 0 stands for 'on'
+
+Build and program u-boot to NOR flash
+==================================
+1. Build u-boot.bin image example:
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make C293PCIE
+
+2. Program u-boot.bin into NOR flash
+	=> tftp $loadaddr $uboot
+	=> protect off eff80000 +$filesize
+	=> erase eff80000 +$filesize
+	=> cp.b $loadaddr eff80000 $filesize
+
+3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
+
+Alternate NOR bank
+==================
+There are four banks in C29XPCIE board, example to change bank booting:
+1. Program u-boot.bin into alternate NOR bank
+	=> tftp $loadaddr $uboot
+	=> protect off e9f80000 +$filesize
+	=> erase e9f80000 +$filesize
+	=> cp.b $loadaddr e9f80000 $filesize
+
+2. Switch to alternate NOR bank
+	=> cpld_cmd reset altbank [bank]
+	- [bank] bank value select 1-4
+	- bank 1 on the flash 0x0000000~0x0ffffff
+	- bank 2 on the flash 0x1000000~0x1ffffff
+	- bank 3 on the flash 0x2000000~0x2ffffff
+	- bank 4 on the flash 0x3000000~0x3ffffff
+	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
+
+Build and program u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+	make C29xPCIE_SPIFLASH_config; make
+	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
+
+2. Program u-boot-spi.bin into SPI flash
+	=> tftp $loadaddr $uboot-spi
+	=> sf erase 0 100000
+	=> sf write $loadaddr 0 $filesize
+
+3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
new file mode 100644
index 0000000..915774c
--- /dev/null
+++ b/include/fsl_usb.h
@@ -0,0 +1,64 @@
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_FSL_USB_H_
+#define _ASM_FSL_USB_H_
+
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+	u32	ctrl;
+	u32	drvvbuscfg;
+	u32	pwrfltcfg;
+	u32	sts;
+	u8	res_14[0xc];
+	u32	bistcfg;
+	u32	biststs;
+	u32	abistcfg;
+	u32	abiststs;
+	u8	res_30[0x10];
+	u32	xcvrprg;
+	u32	anaprg;
+	u32	anadrv;
+	u32	anasts;
+};
+
+struct ccsr_usb_phy {
+	u32	id;
+	struct ccsr_usb_port_ctrl port1;
+	u8	res_50[0xc];
+	u32	tvr;
+	u32	pllprg[4];
+	u8	res_70[0x4];
+	u32	anaccfg;
+	u32	dbg;
+	u8	res_7c[0x4];
+	struct ccsr_usb_port_ctrl port2;
+	u8	res_dc[0x334];
+};
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#else
+struct ccsr_usb_phy {
+	u8	res0[0x18];
+	u32	usb_enable_override;
+	u8	res[0xe4];
+};
+#define	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE	1
+#endif
+
+#endif /*_ASM_FSL_USB_H_ */