Merge branch 'master' of git://git.denx.de/u-boot-arm

131 files changed, 2455 insertions, 803 deletions

diff --git a/Makefile b/Makefile
index bf8165e..27c6962 100644
--- a/Makefile
+++ b/Makefile
@@ -313,11 +313,8 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-ifeq ($(SOC),mx5)
-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
-endif
-ifeq ($(SOC),mx6)
-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif
 
 ifeq ($(SOC),s5pc1xx)
@@ -776,6 +773,7 @@ clean:
 	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
 	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
 	       $(obj)tools/mk{smdk5250,}spl				  \
+	       $(obj)tools/mxsboot					  \
 	       $(obj)tools/ncb		   $(obj)tools/ubsha1
 	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 8873fb7..93f429c 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
@@ -30,16 +31,17 @@
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = GET_PLL_MFI(reg);
-	u32 mfn = GET_PLL_MFN(reg);
+	s32 mfn = GET_PLL_MFN(reg);
 	u32 mfd = GET_PLL_MFD(reg);
 	u32 pd =  GET_PLL_PD(reg);
 
 	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
 	mfd += 1;
 	pd += 1;
 
-	return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-		(mfd * pd)) << 10;
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
 }
 
 static u32 mx31_get_mpl_dpdgck_clk(void)
@@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
 	u32 infreq;
 
 	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-		infreq = CONFIG_MX31_CLK32 * 1024;
+		infreq = MXC_CLK32 * 1024;
 	else
-		infreq = CONFIG_MX31_HCLK_FREQ;
+		infreq = MXC_HCLK;
 
 	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c
index 72081a8..36266da 100644
--- a/arch/arm/cpu/arm1136/mx31/timer.c
+++ b/arch/arm/cpu/arm1136/mx31/timer.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <div64.h>
 #include <watchdog.h>
 #include <asm/io.h>
@@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX31_CLK32);
+	do_div(tick, MXC_CLK32);
 	return tick;
 }
 
 static inline unsigned long long time_to_tick(unsigned long long time)
 {
-	time *= CONFIG_MX31_CLK32;
+	time *= MXC_CLK32;
 	do_div(time, CONFIG_SYS_HZ);
 	return time;
 }
 
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	us = us * CONFIG_MX31_CLK32 + 999999;
+	us = us * MXC_CLK32 + 999999;
 	do_div(us, 1000000);
 	return us;
 }
 #else
 /* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
-							/ CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
+#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / MXC_CLK32)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -128,7 +128,7 @@ ulong get_timer_masked(void)
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -159,7 +159,7 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-	return CONFIG_MX31_CLK32;
+	return MXC_CLK32;
 }
 
 void reset_cpu(ulong addr)
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index d435e8a..ef65176 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0)
 static u32 decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
+	s32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
 	u32 pd = (reg >> 26) & 0xf;
 
 	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
 	mfd += 1;
 	pd += 1;
 
-	return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
 }
 
 static u32 get_mcu_main_clk(void)
@@ -146,9 +149,7 @@ static u32 get_mcu_main_clk(void)
 	struct ccm_regs *ccm =
 		(struct ccm_regs *)IMX_CCM_BASE;
 	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
-	fi *=
-		decode_pll(readl(&ccm->mpctl),
-			CONFIG_MX35_HCLK_FREQ);
+	fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
 	return fi / (arm_div * fd);
 }
 
@@ -171,17 +172,14 @@ static u32 get_ipg_per_clk(void)
 	u32 pdr4 = readl(&ccm->pdr4);
 	u32 div;
 	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-		div = (CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_PER0_PRDF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
-			(CCM_GET_DIVIDER(pdr4,
+		div = CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_PER0_PODF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
 	} else {
 		div = CCM_GET_DIVIDER(pdr0,
 			MXC_CCM_PDR0_PER_PODF_MASK,
 			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-		freq /= get_ahb_div(pdr0);
+		div *= get_ahb_div(pdr0);
 	}
 	return freq / div;
 }
@@ -193,25 +191,20 @@ u32 imx_get_uartclk(void)
 		(struct ccm_regs *)IMX_CCM_BASE;
 	u32 pdr4 = readl(&ccm->pdr4);
 
-	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
+	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
 		freq = get_mcu_main_clk();
-	} else {
-		freq = decode_pll(readl(&ccm->ppctl),
-			CONFIG_MX35_HCLK_FREQ);
-	}
-	freq /= ((CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_UART_PRDF_MASK,
-			MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
-		(CCM_GET_DIVIDER(pdr4,
+	else
+		freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+	freq /= CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_UART_PODF_MASK,
-			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
+			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
 	return freq;
 }
 
 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
 	u32 nfc_pdf, hsp_podf;
-	u32 pll, ret_val = 0, usb_prdf, usb_podf;
+	u32 pll, ret_val = 0, usb_podf;
 	struct ccm_regs *ccm =
 		(struct ccm_regs *)IMX_CCM_BASE;
 
@@ -255,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 		ret_val = pll / (nfc_pdf + 1);
 		break;
 	case USB_CLK:
-		usb_prdf = (reg4 >> 25) & 0x7;
-		usb_podf = (reg4 >> 22) & 0x7;
-		if (reg4 & 0x200) {
+		usb_podf = (reg4 >> 22) & 0x3F;
+		if (reg4 & 0x200)
 			pll = get_mcu_main_clk();
-		} else {
-			pll = decode_pll(readl(&ccm->ppctl),
-				CONFIG_MX35_HCLK_FREQ);
-		}
+		else
+			pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
 
-		ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+		ret_val = pll / (usb_podf + 1);
 		break;
 	default:
 		printf("Unknown clock: %d\n", clk);
@@ -287,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
 	case UART2_BAUD:
 	case UART3_BAUD:
 		clk_sel = mpdr3 & (1 << 14);
-		pre_pdf = (mpdr4 >> 13) & 0x7;
-		pdf = (mpdr4 >> 10) & 0x7;
+		pdf = (mpdr4 >> 10) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case SSI1_BAUD:
 		pre_pdf = (mpdr2 >> 24) & 0x7;
 		pdf = mpdr2 & 0x3F;
 		clk_sel = mpdr2 & (1 << 6);
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	case SSI2_BAUD:
@@ -306,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
 		pdf = (mpdr2 >> 8) & 0x3F;
 		clk_sel = mpdr2 & (1 << 6);
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	case CSI_BAUD:
 		clk_sel = mpdr2 & (1 << 7);
-		pre_pdf = (mpdr2 >> 16) & 0x7;
-		pdf = (mpdr2 >> 19) & 0x7;
+		pdf = (mpdr2 >> 16) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case MSHC_CLK:
 		pre_pdf = readl(&ccm->pdr1);
@@ -323,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
 		pdf = (pre_pdf >> 22) & 0x3F;
 		pre_pdf = (pre_pdf >> 28) & 0x7;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	case ESDHC1_CLK:
 		clk_sel = mpdr3 & 0x40;
-		pre_pdf = mpdr3 & 0x7;
-		pdf = (mpdr3>>3) & 0x7;
+		pdf = mpdr3 & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case ESDHC2_CLK:
 		clk_sel = mpdr3 & 0x40;
-		pre_pdf = (mpdr3 >> 8) & 0x7;
-		pdf = (mpdr3 >> 11) & 0x7;
+		pdf = (mpdr3 >> 8) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case ESDHC3_CLK:
 		clk_sel = mpdr3 & 0x40;
-		pre_pdf = (mpdr3 >> 16) & 0x7;
-		pdf = (mpdr3 >> 19) & 0x7;
+		pdf = (mpdr3 >> 16) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case SPDIF_CLK:
 		clk_sel = mpdr3 & 0x400000;
 		pre_pdf = (mpdr3 >> 29) & 0x7;
 		pdf = (mpdr3 >> 23) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	default:
diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c
index 04937a1..9680b7f 100644
--- a/arch/arm/cpu/arm1136/mx35/timer.c
+++ b/arch/arm/cpu/arm1136/mx35/timer.c
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)	/* Software reset */
 #define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (0x100<<6)	/* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6)	/* Clock source */
+#define GPTCR_CLKSOURCE_32   (4<<6)	/* Clock source */
 #define GPTCR_TEN       (1)	/* Timer enable */
 
-#define	TIMER_FREQ_HZ	mxc_get_clock(MXC_IPG_CLK)
-
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, TIMER_FREQ_HZ);
+	do_div(tick, MXC_CLK32);
 
 	return tick;
 }
 
-static inline unsigned long long us_to_tick(unsigned long long usec)
+static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	usec *= TIMER_FREQ_HZ;
-	do_div(usec, 1000000);
+	us = us * MXC_CLK32 + 999999;
+	do_div(us, 1000000);
 
-	return usec;
+	return us;
 }
 
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
 int timer_init(void)
 {
 	int i;
 	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
 
 	/* setup GP Timer 1 */
 	writel(GPTCR_SWR, &gpt->ctrl);
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl);	/* We have no udelay by now */
 
-	writel(0, &gpt->pre);
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&gpt->ctrl) |
-		GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-		&gpt->ctrl);
+	writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
 
 	return 0;
 }
@@ -101,7 +111,7 @@ ulong get_timer_masked(void)
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -132,5 +142,5 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-	return TIMER_FREQ_HZ;
+	return MXC_CLK32;
 }
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
index 6d4d66b..ddf8d97 100644
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra20/cpu.c
@@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable)
 
 static int is_cpu_powered(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
 	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 }
 
 static void remove_cpu_io_clamps(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
 	/* Remove the clamps on the CPU I/O signals */
@@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void)
 
 static void powerup_cpu(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 	int timeout = IO_STABILIZATION_DELAY;
 
@@ -157,7 +157,7 @@ static void powerup_cpu(void)
 
 static void enable_cpu_power_rail(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
 	reg = readl(&pmc->pmc_cntrl);
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index a412a8f..90e584a 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
 static ulong imx_get_mpllclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = 24000000;
+	ulong fref = MXC_HCLK;
 
 	return imx_decode_pll(readl(&ccm->mpctl), fref);
 }
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 1cfd02b..4dc4041 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -40,6 +40,7 @@
 #include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX25_CLK32);
+	do_div(tick, MXC_CLK32);
 	return tick;
 }
 
 static inline unsigned long long time_to_tick(unsigned long long time)
 {
-	time *= CONFIG_MX25_CLK32;
+	time *= MXC_CLK32;
 	do_div(time, CONFIG_SYS_HZ);
 	return time;
 }
 
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	us = us * CONFIG_MX25_CLK32 + 999999;
+	us = us * MXC_CLK32 + 999999;
 	do_div(us, 1000000);
 	return us;
 }
 #else
 /* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX25_CLK32)
+#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / MXC_CLK32)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -144,7 +144,7 @@ ulong get_timer_masked(void)
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -177,6 +177,6 @@ ulong get_tbclk(void)
 {
 	ulong tbclk;
 
-	tbclk = CONFIG_MX25_CLK32;
+	tbclk = MXC_CLK32;
 	return tbclk;
 }
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index ddafddb..ad66c57 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -38,12 +38,14 @@
  * takes a few seconds to roll. The boot doesn't take that long, so to keep the
  * code simple, it doesn't take rolling into consideration.
  */
-#define	HW_DIGCTRL_MICROSECONDS	0x8001c0c0
 void early_delay(int delay)
 {
-	uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+	uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
 	st += delay;
-	while (st > readl(HW_DIGCTRL_MICROSECONDS))
+	while (st > readl(&digctl_regs->hw_digctl_microseconds))
 		;
 }
 
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 792b11d..c3948d3 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -292,7 +292,9 @@ int arch_misc_init(void)
 	writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
 	writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
 	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
+	writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
 	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
+	writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
 
 	/* initialize timer */
 	timer_init_r();
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index b387ac2..ecc2671 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -37,7 +37,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static const struct gpio_bank gpio_bank_am33xx[4] = {
@@ -119,22 +118,6 @@ static int read_eeprom(void)
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-/* Initialize timer */
-static void init_timer(void)
-{
-	/* Reset the Timer */
-	writel(0x2, (&timer_base->tscir));
-
-	/* Wait until the reset is done */
-	while (readl(&timer_base->tiocp_cfg) & 1)
-		;
-
-	/* Start the Timer */
-	writel(0x1, (&timer_base->tclr));
-}
-#endif
-
 /*
  * Determine what type of DDR we have.
  */
@@ -183,9 +166,6 @@ void s_init(void)
 	regVal |= UART_SMART_IDLE_EN;
 	writel(regVal, &uart_base->uartsyscfg);
 
-	/* Initialize the Timer */
-	init_timer();
-
 	preloader_console_init();
 
 	/* Initalize the board header */
diff --git a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
index 75cadb0..925f841 100644
--- a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
+++ b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
@@ -46,7 +46,7 @@
 static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
 	puts("Entering RCM...\n");
 	udelay(50000);
diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c
index 178bb13..cac0918 100644
--- a/arch/arm/cpu/armv7/tegra20/usb.c
+++ b/arch/arm/cpu/armv7/tegra20/usb.c
@@ -137,24 +137,29 @@ static const u8 utmip_elastic_limit = 16;
 /* UTMIP High Speed Sync Start Delay */
 static const u8 utmip_hs_sync_start_delay = 9;
 
-/* Put the port into host mode (this only works for OTG ports) */
+/* Put the port into host mode */
 static void set_host_mode(struct fdt_usb *config)
 {
-	if (config->dr_mode == DR_MODE_OTG) {
-		/* Check whether remote host from USB1 is driving VBus */
-		if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
-			return;
-
-		/*
-		 * If not driving, we set the GPIO to enable VBUS. We assume
-		 * that the pinmux is set up correctly for this.
-		 */
-		if (fdt_gpio_isvalid(&config->vbus_gpio)) {
-			fdtdec_setup_gpio(&config->vbus_gpio);
-			gpio_direction_output(config->vbus_gpio.gpio, 1);
-			debug("set_host_mode: GPIO %d high\n",
-			      config->vbus_gpio.gpio);
-		}
+	/*
+	 * If we are an OTG port, check if remote host is driving VBus and
+	 * bail out in this case.
+	 */
+	if (config->dr_mode == DR_MODE_OTG &&
+		(readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
+		return;
+
+	/*
+	 * If not driving, we set the GPIO to enable VBUS. We assume
+	 * that the pinmux is set up correctly for this.
+	 */
+	if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+		fdtdec_setup_gpio(&config->vbus_gpio);
+		gpio_direction_output(config->vbus_gpio.gpio,
+			(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+				 0 : 1);
+		debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
+			(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+				"low" : "high");
 	}
 }
 
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile
index 43c96c6..9e91e5c 100644
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -33,7 +33,7 @@ LIB	= $(obj)lib$(SOC)-common.o
 
 SOBJS += lowlevel_init.o
 COBJS-y	+= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
+COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
 COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 
diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c
index 00588da..c0ca6eb 100644
--- a/arch/arm/cpu/tegra20-common/ap20.c
+++ b/arch/arm/cpu/tegra20-common/ap20.c
@@ -32,7 +32,7 @@
 int tegra_get_chip_type(void)
 {
 	struct apb_misc_gp_ctlr *gp;
-	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 	uint tegra_sku_id, rev;
 
 	/*
@@ -40,7 +40,7 @@ int tegra_get_chip_type(void)
 	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
 	 * Tegra30
 	 */
-	gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
 
 	tegra_sku_id = readl(&fuse->sku_info) & 0xff;
@@ -101,7 +101,7 @@ static u32 get_odmdata(void)
 
 static void init_pmc_scratch(void)
 {
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 odmdata;
 	int i;
 
diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c
index 598023a..8a8d338 100644
--- a/arch/arm/cpu/tegra20-common/board.c
+++ b/arch/arm/cpu/tegra20-common/board.c
@@ -47,7 +47,7 @@ enum {
 
 unsigned int query_sdram_size(void)
 {
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
 	reg = readl(&pmc->pmc_scratch20);
@@ -81,11 +81,11 @@ int checkboard(void)
 #endif	/* CONFIG_DISPLAY_BOARDINFO */
 
 static int uart_configs[] = {
-#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
 	FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA20_UARTA_GPU)
+#elif defined(CONFIG_TEGRA_UARTA_GPU)
 	FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
+#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
 	FUNCMUX_UART1_SDIO1,
 #else
 	FUNCMUX_UART1_IRRX_IRTX,
@@ -125,13 +125,13 @@ void board_init_uart_f(void)
 {
 	int uart_ids = 0;	/* bit mask of which UART ids to enable */
 
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
 	uart_ids |= UARTA;
 #endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTB
+#ifdef CONFIG_TEGRA_ENABLE_UARTB
 	uart_ids |= UARTB;
 #endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTD
+#ifdef CONFIG_TEGRA_ENABLE_UARTD
 	uart_ids |= UARTD;
 #endif
 	setup_uarts(uart_ids);
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c
index 8cfed64..b2129ad 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/cpu/tegra20-common/funcmux.c
@@ -234,6 +234,13 @@ int funcmux_select(enum periph_id id, int config)
 		}
 		break;
 
+	case PERIPH_ID_NDFLASH:
+		if (config == FUNCMUX_NDFLASH_ATC) {
+			pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
+			pinmux_tristate_disable(PINGRP_ATC);
+		}
+		break;
+
 	default:
 		debug("%s: invalid periph_id %d", __func__, id);
 		return -1;
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 809ea01..6ce995e 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -39,7 +39,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
 #endif
 
 /*
@@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void)
 	u32 ram_code;
 	struct sdram_params sdram;
 	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	struct apb_misc_gp_ctlr *gp =
-			(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+			(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
 	union scratch2_reg scratch2;
 	union scratch4_reg scratch4;
@@ -205,7 +205,7 @@ static u32 get_major_version(void)
 {
 	u32 major_id;
 	struct apb_misc_gp_ctlr *gp =
-		(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
 	major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
 			HIDREV_MAJORPREV_SHIFT;
@@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse)
 
 static int ap20_is_odm_production_mode(void)
 {
-	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
 	if (!is_failure_analysis_mode(fuse) &&
 	    is_odm_production_mode_fuse_set(fuse))
@@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void)
 
 static int ap20_is_production_mode(void)
 {
-	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
 	if (get_major_version() == 0)
 		return 1;
@@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void)
 {
 	u32 chip_id;
 	struct apb_misc_gp_ctlr *gp =
-		(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
 	chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
 			HIDREV_CHIPID_SHIFT;
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c
index cd01908..80a5a15 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c
@@ -38,7 +38,7 @@
 void wb_start(void)
 {
 	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index f95be58..d936b1e 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -204,4 +204,11 @@
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x0078>;
 	};
+
+	nand: nand-controller@70008000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-nand";
+		reg = <0x70008000 0x100>;
+	};
 };
diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 16fba8d..b3e608e 100644
--- a/arch/arm/cpu/armv7/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk
 
 LIB     = $(obj)libimx-common.o
 
+ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 COBJS-y	= iomux-v3.o timer.o cpu.o speed.o
-COBJS-$(CONFIG_I2C_MXC) += i2c.o
+COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+endif
 COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 COBJS	:= $(sort $(COBJS-y))
 
diff --git a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c
index 02fe72e..02fe72e 100644
--- a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c
+++ b/arch/arm/imx-common/cmd_bmode.c
diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index fa1d468..fa1d468 100644
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c b/arch/arm/imx-common/i2c-mxv7.c
index da2b26f..da2b26f 100644
--- a/arch/arm/cpu/armv7/imx-common/i2c.c
+++ b/arch/arm/imx-common/i2c-mxv7.c
diff --git a/arch/arm/cpu/armv7/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index da093fb..da093fb 100644
--- a/arch/arm/cpu/armv7/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/imx-common/speed.c
index 80989c4..80989c4 100644
--- a/arch/arm/cpu/armv7/imx-common/speed.c
+++ b/arch/arm/imx-common/speed.c
diff --git a/arch/arm/cpu/armv7/imx-common/timer.c b/arch/arm/imx-common/timer.c
index e2725e1..e2725e1 100644
--- a/arch/arm/cpu/armv7/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h
index c79bed7..113f258 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -49,6 +49,7 @@ struct kwspi_registers {
 #define MISO_MPP11	(1 << 2)
 
 #define KWSPI_CLKPRESCL_MASK	0x1f
+#define KWSPI_CLKPRESCL_MIN	0x12
 #define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
 #define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
 #define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h
index 0f47eaf..a313b80 100644
--- a/arch/arm/include/asm/arch-mx25/clock.h
+++ b/arch/arm/include/asm/arch-mx25/clock.h
@@ -26,6 +26,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_MX25_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX25_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX25_CLK32
+#define MXC_CLK32	CONFIG_MX25_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_CSI_CLK,
 	MXC_EPIT_CLK,
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index 852c19c..9468b45 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -24,6 +24,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_MX31_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX31_HCLK_FREQ
+#else
+#define MXC_HCLK	26000000
+#endif
+
+#ifdef CONFIG_MX31_CLK32
+#define MXC_CLK32	CONFIG_MX31_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_ARM_CLK,
 	MXC_IPG_CLK,
diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h
index e94f124..eb7458a 100644
--- a/arch/arm/include/asm/arch-mx35/clock.h
+++ b/arch/arm/include/asm/arch-mx35/clock.h
@@ -24,6 +24,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_MX35_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX35_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX35_CLK32
+#define MXC_CLK32	CONFIG_MX35_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_ARM_CLK,
 	MXC_AHB_CLK,
diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h
index 7a2d1bb..3fcde0b 100644
--- a/arch/arm/include/asm/arch-mx35/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx35/crm_regs.h
@@ -32,8 +32,8 @@
 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
 #define MXC_CCM_CCMR_ROMW_OFFSET               18
 #define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET               21
-#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 21)
+#define MXC_CCM_CCMR_RAMW_OFFSET               16
+#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 16)
 #define MXC_CCM_CCMR_LPM_OFFSET                 14
 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
 #define MXC_CCM_CCMR_UPE                        (1 << 9)
@@ -47,7 +47,7 @@
 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
 #define MXC_CCM_PDR0_CKIL_SEL			(1 << 15)
 #define MXC_CCM_PDR0_PER_PODF_OFFSET            12
-#define MXC_CCM_PDR0_PER_PODF_MASK              (0xF << 12)
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x7 << 12)
 #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
 #define MXC_CCM_PDR0_AUTO_CON	                0x1
@@ -62,10 +62,8 @@
 #define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
 #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
 #define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PRDF_OFFSET            19
-#define MXC_CCM_PDR2_CSI_PRDF_MASK              (0x7 << 19)
 #define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
-#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x7 << 16)
+#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x3F << 16)
 #define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
 #define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
 #define MXC_CCM_PDR2_CSI_M_U			(1 << 7)
@@ -78,35 +76,23 @@
 #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
 #define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
 #define MXC_CCM_PDR3_SPDIF_M_U			(1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET         19
-#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK           (0x7 << 19)
 #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_PDR3_UART_M_U			(1 << 15)
-#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET         11
-#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK           (0x7 << 11)
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x3F << 16)
+#define MXC_CCM_PDR3_UART_M_U			(1 << 14)
 #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x7 << 8)
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x3F << 8)
 #define MXC_CCM_PDR3_ESDHC_M_U			(1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET         3
-#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK           (0x7 << 3)
 #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x7)
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x3F)
 
 #define MXC_CCM_PDR4_NFC_PODF_OFFSET		28
 #define MXC_CCM_PDR4_NFC_PODF_MASK		(0xF << 28)
-#define MXC_CCM_PDR4_USB_PRDF_OFFSET		25
-#define MXC_CCM_PDR4_USB_PRDF_MASK		(0x7 << 25)
 #define MXC_CCM_PDR4_USB_PODF_OFFSET		22
-#define MXC_CCM_PDR4_USB_PODF_MASK		(0x7 << 22)
-#define MXC_CCM_PDR4_PER0_PRDF_OFFSET		19
-#define MXC_CCM_PDR4_PER0_PRDF_MASK		(0x7 << 19)
+#define MXC_CCM_PDR4_USB_PODF_MASK		(0x3F << 22)
 #define MXC_CCM_PDR4_PER0_PODF_OFFSET		16
-#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x7 << 16)
-#define MXC_CCM_PDR4_UART_PRDF_OFFSET		13
-#define MXC_CCM_PDR4_UART_PRDF_MASK		(0x7 << 13)
+#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x3F << 16)
 #define MXC_CCM_PDR4_UART_PODF_OFFSET		10
-#define MXC_CCM_PDR4_UART_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_PDR4_UART_PODF_MASK		(0x3F << 10)
 #define MXC_CCM_PDR4_USB_M_U			(1 << 9)
 
 /* Bit definitions for RCSR */
@@ -144,6 +130,12 @@
 #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK		(0xF << 0)
 
 /* Bit definitions for Clock gating Register*/
+#define MXC_CCM_CGR_CG_MASK			0x3
+#define MXC_CCM_CGR_CG_OFF			0x0
+#define MXC_CCM_CGR_CG_RUN_ON			0x1
+#define MXC_CCM_CGR_CG_RUN_WAIT_ON		0x2
+#define MXC_CCM_CGR_CG_ON			0x3
+
 #define MXC_CCM_CGR0_ASRC_OFFSET		0
 #define MXC_CCM_CGR0_ASRC_MASK			(0x3 << 0)
 #define MXC_CCM_CGR0_ATA_OFFSET			2
@@ -251,10 +243,8 @@
 #define MXC_CCM_COSR_CLKOSEL_OFFSET		0
 #define MXC_CCM_COSR_CLKOEN			(1 << 5)
 #define MXC_CCM_COSR_CLKOUTDIV_1		(1 << 6)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK		(0x7 << 10)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET	10
-#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK		(0x7 << 13)
-#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET	13
+#define MXC_CCM_COSR_CLKOUT_DIV_MASK		(0x3F << 10)
+#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET		10
 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK	(0x3 << 16)
 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET	16
 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK	(0x3 << 18)
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index a1255f9..d23abd7 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -34,21 +34,21 @@
 #define IOMUXC_GPR13_SATA_PHY_2_MASK	(0x1f<<2)
 #define IOMUXC_GPR13_SATA_PHY_1_MASK	(3<<0)
 
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0b000<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(0b001<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(0b010<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(0b011<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(0b100<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(0b101<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(0b110<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(0b111<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(1<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(2<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(3<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(4<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(5<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(6<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(7<<24)
 
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0b11010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0x1A<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0x1A<<19)
 
 #define IOMUXC_GPR13_SATA_SPEED_1P5G	(0<<15)
 #define IOMUXC_GPR13_SATA_SPEED_3G	(1<<15)
@@ -63,55 +63,55 @@
 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16		(4<<11)
 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16		(5<<11)
 
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0b0000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(0b0001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(0b0010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(0b0011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(0b0100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(0b0101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(0b0110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(0b0111<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(0b1000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(0b1001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0b1010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0b1011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0b1100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0b1101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0b1110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0b1111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(1<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(2<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(3<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(4<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(5<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(6<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(7<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(8<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(9<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0xA<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0xB<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0xC<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0xD<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0xE<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0xF<<7)
 
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0b00000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(0b00001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(0b00010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(0b00011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(0b00100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(0b00101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(0b00110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(0b00111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(0b01000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(0b01001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0b01010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0b01011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0b01100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0b01101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0b01110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0b01111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0b10000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0b10001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0b10010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0b10011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0b10100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0b10101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0b10110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0b10111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0b11000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0b11001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0b11010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0b11011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0b11100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0b11101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0b11110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0b11111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(1<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(2<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(3<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(4<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(5<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(6<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(7<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(8<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(9<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0xA<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0xB<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0xC<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0xD<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0xE<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0xF<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0x10<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0x11<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0x12<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0x13<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0x14<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0x15<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0x16<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0x17<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0x18<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0x19<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0x1A<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0x1B<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0x1C<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0x1D<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0x1E<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0x1F<<2)
 
 #define IOMUXC_GPR13_SATA_PHY_1_FAST	0
 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM	1
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index a830c43..54add4b 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -142,7 +142,6 @@ struct venc_regs {
 };
 
 /* Few Register Offsets */
-#define FRAME_MODE_SHIFT			1
 #define TFTSTN_SHIFT				3
 #define DATALINES_SHIFT				8
 
@@ -182,6 +181,16 @@ struct panel_config {
 	void *frame_buffer;
 };
 
+#define DSS_HBP(bp)    (((bp) - 1) << 20)
+#define DSS_HFP(fp)    (((fp) - 1) << 8)
+#define DSS_HSW(sw)    ((sw) - 1)
+#define DSS_VBP(bp)    ((bp) << 20)
+#define DSS_VFP(fp)    ((fp) << 8)
+#define DSS_VSW(sw)    ((sw) - 1)
+
+#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
+#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+
 /* Generic DSS Functions */
 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
 			u32 height, u32 width);
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 71f183d..6e92b23 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -451,6 +451,11 @@
 #define CONTROL_PADCONF_GPIO128		0x0A58
 #define CONTROL_PADCONF_GPIO129		0x0A5A
 
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL		(OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ	(1<<6)
+
 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
 
diff --git a/arch/arm/include/asm/arch-tegra20/ap20.h b/arch/arm/include/asm/arch-tegra20/ap20.h
index c84d22f..70d94c5 100644
--- a/arch/arm/include/asm/arch-tegra20/ap20.h
+++ b/arch/arm/include/asm/arch-tegra20/ap20.h
@@ -95,9 +95,6 @@
 #define HALT_COP_EVENT_IRQ_1		(1 << 11)
 #define HALT_COP_EVENT_FIQ_1		(1 << 9)
 
-/* Start up the tegra20 SOC */
-void tegra20_start(void);
-
 /* This is the main entry into U-Boot, used by the Cortex-A9 */
 extern void _start(void);
 
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
index 258f7b6..bd511db 100644
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -57,6 +57,9 @@ enum {
 
 	/* Serial Flash configs */
 	FUNCMUX_SPI1_GMC_GMD = 0,
+
+	/* NAND flags */
+	FUNCMUX_NDFLASH_ATC = 0,
 };
 
 /**
diff --git a/arch/arm/include/asm/arch-tegra20/mmc.h b/arch/arm/include/asm/arch-tegra20/mmc.h
index 916a353..5c95047 100644
--- a/arch/arm/include/asm/arch-tegra20/mmc.h
+++ b/arch/arm/include/asm/arch-tegra20/mmc.h
@@ -19,9 +19,9 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA20_MMC_H_
-#define _TEGRA20_MMC_H_
+#ifndef _TEGRA_MMC_H_
+#define _TEGRA_MMC_H_
 
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
 
-#endif /* TEGRA20_MMC_H_ */
+#endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/sys_proto.h b/arch/arm/include/asm/arch-tegra20/sys_proto.h
index 643d542..919aec7 100644
--- a/arch/arm/include/asm/arch-tegra20/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra20/sys_proto.h
@@ -24,12 +24,12 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-struct tegra20_sysinfo {
+struct tegra_sysinfo {
 	char *board_string;
 };
 
 void invalidate_dcache(void);
 
-extern const struct tegra20_sysinfo sysinfo;
+extern const struct tegra_sysinfo sysinfo;
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra20/tegra20.h
index 6750754..c9485a1 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20.h
@@ -33,21 +33,22 @@
 #define NV_PA_GPIO_BASE		0x6000D000
 #define NV_PA_EVP_BASE		0x6000F000
 #define NV_PA_APB_MISC_BASE	0x70000000
-#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
 #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
 #define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
 #define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
-#define TEGRA20_SPI_BASE	(NV_PA_APB_MISC_BASE + 0xC380)
-#define TEGRA20_PMC_BASE	(NV_PA_APB_MISC_BASE + 0xE400)
-#define TEGRA20_FUSE_BASE	(NV_PA_APB_MISC_BASE + 0xF800)
+#define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
 #define NV_PA_CSITE_BASE	0x70040000
 #define TEGRA_USB1_BASE		0xC5000000
 #define TEGRA_USB3_BASE		0xC5008000
 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
 
-#define TEGRA20_SDRC_CS0	NV_PA_SDRAM_BASE
+#define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
 #define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
 #define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
@@ -85,7 +86,7 @@ enum {
 };
 
 #else  /* __ASSEMBLY__ */
-#define PRM_RSTCTRL		TEGRA20_PMC_BASE
+#define PRM_RSTCTRL		NV_PA_PMC_BASE
 #endif
 
 #endif	/* TEGRA20_H */
diff --git a/drivers/mmc/tegra_mmc.h b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
index b1f2564..dd746ca 100644
--- a/drivers/mmc/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
@@ -22,13 +22,13 @@
 #ifndef __TEGRA_MMC_H_
 #define __TEGRA_MMC_H_
 
-#define TEGRA20_SDMMC1_BASE	0xC8000000
-#define TEGRA20_SDMMC2_BASE	0xC8000200
-#define TEGRA20_SDMMC3_BASE	0xC8000400
-#define TEGRA20_SDMMC4_BASE	0xC8000600
+#define TEGRA_SDMMC1_BASE	0xC8000000
+#define TEGRA_SDMMC2_BASE	0xC8000200
+#define TEGRA_SDMMC3_BASE	0xC8000400
+#define TEGRA_SDMMC4_BASE	0xC8000600
 
 #ifndef __ASSEMBLY__
-struct tegra20_mmc {
+struct tegra_mmc {
 	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
 	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
 	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
@@ -118,7 +118,7 @@ struct tegra20_mmc {
 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
 
 struct mmc_host {
-	struct tegra20_mmc *reg;
+	struct tegra_mmc *reg;
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
 	unsigned int base;	/* Base address, SDMMC1/2/3/4 */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_spi.h b/arch/arm/include/asm/arch-tegra20/tegra_spi.h
index 8978bea..d53a93f 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra_spi.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra_spi.h
@@ -70,6 +70,6 @@ struct spi_tegra {
 #define SPI_STAT_CUR_BLKCNT		(1 << 15)
 
 #define SPI_TIMEOUT		1000
-#define TEGRA20_SPI_MAX_FREQ	52000000
+#define TEGRA_SPI_MAX_FREQ	52000000
 
 #endif	/* _TEGRA_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/timer.h b/arch/arm/include/asm/arch-tegra20/timer.h
index 43f7ab4..fdb99a7 100644
--- a/arch/arm/include/asm/arch-tegra20/timer.h
+++ b/arch/arm/include/asm/arch-tegra20/timer.h
@@ -21,8 +21,8 @@
 
 /* Tegra20 timer functions */
 
-#ifndef _TEGRA20_TIMER_H
-#define _TEGRA20_TIMER_H
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
 
 /* returns the current monotonic timer value in microseconds */
 unsigned long timer_get_us(void);
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index f1951e8..109a1ac 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -241,6 +241,9 @@ init_fnc_t *init_sequence[] = {
 	fdtdec_check_fdt,
 #endif
 	timer_init,		/* initialize timer */
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+	board_postclk_init,
+#endif
 #ifdef CONFIG_FSL_ESDHC
 	get_clocks,
 #endif
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index 776226f..e98244b 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -267,9 +267,9 @@ int drv_video_init(void)
 		display_height = 256;
 	printf("%ld x %ld pixel matrix\n", display_width, display_height);
 
-	/* RWH = 7 | RWS =7  | TDF = 15 | NWS = 0x7F */
-	csr =	AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
-		AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+	/* RWH = 2 | RWS =2  | TDF = 4 | NWS = 0x6 */
+	csr =	AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+		AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
 		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
 		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
 	writel(csr, &mc->smc.csr[2]);
diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg
index 3b9c53f..55be3a3 100644
--- a/board/Marvell/sheevaplug/kwbimage.cfg
+++ b/board/Marvell/sheevaplug/kwbimage.cfg
@@ -21,8 +21,8 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
-# and create kirkwood boot image
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
 #
 
 # Boot Media configurations
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index a0a4d1d..93f12ea 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -78,7 +78,7 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	/* init dev 0, SD slot, with 4-bit bus */
-	tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+	tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
 
 	return 0;
 }
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 9faebd8..bb3851b 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -55,4 +55,15 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index fe15511..b3f31d6 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -158,7 +158,7 @@ static void set_led(int state)
 {
 	switch (state) {
 	case LED_OFF:
-		__set_led(0, 0, 0, 0, 0, 0);
+		__set_led(0, 0, 0, 1, 1, 1);
 		break;
 	case LED_ALARM_ON:
 		__set_led(0, 0, 0, 0, 1, 1);
@@ -192,6 +192,25 @@ int board_init(void)
 }
 
 #ifdef CONFIG_MISC_INIT_R
+static void check_power_switch(void)
+{
+	if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
+		/* turn off HDD and USB power */
+		kw_gpio_set_value(GPIO_HDD_POWER, 0);
+		kw_gpio_set_value(GPIO_USB_VBUS, 0);
+		set_led(LED_OFF);
+
+		/* loop until released */
+		while (kw_gpio_get_value(GPIO_POWER_SWITCH))
+			;
+
+		/* turn power on again */
+		kw_gpio_set_value(GPIO_HDD_POWER, 1);
+		kw_gpio_set_value(GPIO_USB_VBUS, 1);
+		set_led(LED_POWER_BLINKING);
+	}
+}
+
 void check_enetaddr(void)
 {
 	uchar enetaddr[6];
@@ -261,6 +280,7 @@ static void check_push_button(void)
 
 int misc_init_r(void)
 {
+	check_power_switch();
 	check_enetaddr();
 	check_push_button();
 
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index cd684f2..0f8f167 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -70,11 +70,11 @@ int board_mmc_init(bd_t *bd)
 	debug("board_mmc_init: init eMMC\n");
 	/* init dev 0, eMMC chip, with 4-bit bus */
 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra20_mmc_init(0, 4, -1, -1);
+	tegra_mmc_init(0, 4, -1, -1);
 
 	debug("board_mmc_init: init SD slot\n");
 	/* init dev 3, SD slot, with 4-bit bus */
-	tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
+	tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
 
 	return 0;
 }
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index 5dae15b..893cca8 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -69,10 +69,10 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
-	tegra20_mmc_init(0, 4, -1, GPIO_PP1);
+	tegra_mmc_init(0, 4, -1, GPIO_PP1);
 
 	/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
-	tegra20_mmc_init(3, 4, -1, -1);
+	tegra_mmc_init(3, 4, -1, -1);
 
 	return 0;
 }
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 16a6d8a..ae6eda3 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -173,7 +173,7 @@ const iomux_cfg_t iomux_setup[] = {
 #define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
 					ADDR_PINS << 8 | APREBIT)
 
-void mx28_adjust_memory_params(uint32_t *dram_vals)
+void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
 }
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
index 867d3c8..d782aea 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -49,8 +49,8 @@ int board_early_init_f(void)
 
 	/* SSP0 clock at 96MHz */
 	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
-	/* SSP2 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
 
 #ifdef	CONFIG_CMD_USB
 	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README
index 3d69ed5..7232b53 100644
--- a/board/freescale/mx35pdk/README
+++ b/board/freescale/mx35pdk/README
@@ -71,91 +71,17 @@ exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nf
 Flashing U-Boot
 --------------------------------
 
-There are two options: the original bootloader in NAND can be replaced with
-u-boot, or u-boot can be stored on the NOR flash without erasing
-the delivered bootloader.
+U-boot should be stored on the NOR flash.
+
 The boot storage can be select using the switches on the personality board
 (SW1-SW2) and on the DEBUG board (SW4-SW10).
 
-The second option is to be preferred if you have not a JTAG debugger.
 If something goes wrong flashing the bootloader, it is always possible to
 recover the board booting from the other device.
 
-Replacing the bootloader on the NAND
---------------------------------------
-To replace RedBoot with U-Boot, the easy way is to do this in linux.
-Start the kernel with the suggested options. Make sure to have set the
-mtdparts exactly as described, because this matches the layout on the
-mx35pdk.
-
-You should see in your boot log the following entries for the NAND
-flash:
-
-5 cmdlinepart partitions found on MTD device mxc_nand
-Creating 5 MTD partitions on "mxc_nand":
-0x000000000000-0x000000100000 : "boot"
-0x000000100000-0x000000600000 : "linux"
-0x000000600000-0x000006600000 : "root"
-0x000006600000-0x000006e00000 : "cfg"
-0x000006e00000-0x000080000000 : "user"
-
-You can use the utilities flash_eraseall and nandwrite to put
-u-boot on the NAND. The bootloader is marked as "boot", and 1MB is
-reserved. If everything is correct, this partition is accessed as
-/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and
-get the device node from the partition name:
-
-$ cat /proc/mtd | grep boot
-
-I suggest you try the utilities on a different partition to be sure
-if everything works correctly. If not, and you remove RedBoot, you have to
-reinstall it using the ATK tool as suggested by Freescale, or using a
-JTAG debugger.
-
-I report the versions of the utilities I used (they are provided with ELDK):
-
--bash-3.2# nandwrite --version
-nandwrite $Revision: 1.32 $
-
-flash_eraseall --version
-flash_eraseall $Revision: 1.22 $
-
-nandwrite reports a warning if the file to be saved is not sector aligned.
-This should have no consequences, but I preferred to pad u-boot.bin
-to get no problem at all.
-$ dd if=/dev/zero of=zeros bs=1 count=74800
-$ cat u-boot.bin zeros > u-boot-padded.bin
-
-To erase the partition:
-$ flash_eraseall /dev/mtd4
-
-Writing u-boot:
-
-$ nandwrite /dev/mtd4 u-boot-padded.bin
-
-Now U-Boot is stored on the booting partition.
-
-To boot from NAND, you have to select the switches as follows:
-
-Personality board
-	SW2	1, 4, 5 on
-		2, 3, 6, 7, 8 off
-	SW1	all off
-
-Debug Board:
-	SW5	0
-	SW6	0
-	SW7	0
-	SW8	1
-	SW9	1
-	SW10	0
-
-
 Saving U-Boot in the NOR flash
 ---------------------------------
 
-The procedure to save in the NOR flash is quite the same as to write into the NAND.
-
 Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
 the boot partition should be /dev/mtd0.
 
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index 787c923..7cb6b30 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -32,6 +32,8 @@
 #include <i2c.h>
 #include <pmic.h>
 #include <fsl_pmic.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
 #include <mc9sdz60.h>
 #include <mc13892.h>
 #include <linux/types.h>
@@ -275,3 +277,26 @@ int board_eth_init(bd_t *bis)
 
 	return rc;
 }
+
+#if defined(CONFIG_FSL_ESDHC)
+
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+	/* configure pins for SDHC1 only */
+	mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
+}
+#endif
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 909ccca..4b4e89b 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -197,18 +197,18 @@ static iomux_v3_cfg_t button_pads[] = {
 
 static void setup_iomux_enet(void)
 {
-	gpio_direction_output(87, 0);  /* GPIO 3-23 */
-	gpio_direction_output(190, 1); /* GPIO 6-30 */
-	gpio_direction_output(185, 1); /* GPIO 6-25 */
-	gpio_direction_output(187, 1); /* GPIO 6-27 */
-	gpio_direction_output(188, 1); /* GPIO 6-28*/
-	gpio_direction_output(189, 1); /* GPIO 6-29 */
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
-	gpio_direction_output(184, 1); /* GPIO 6-24 */
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 
 	/* Need delay 10ms according to KSZ9021 spec */
 	udelay(1000 * 10);
-	gpio_set_value(87, 1);  /* GPIO 3-23 */
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 
 	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 }
@@ -249,11 +249,11 @@ int board_mmc_getcd(struct mmc *mmc)
        int ret;
 
        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-	       gpio_direction_input(192); /*GPIO7_0*/
-	       ret = !gpio_get_value(192);
+		gpio_direction_input(IMX_GPIO_NR(7, 0));
+		ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
        } else {
-	       gpio_direction_input(38); /*GPIO2_6*/
-	       ret = !gpio_get_value(38);
+		gpio_direction_input(IMX_GPIO_NR(2, 6));
+		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
        }
 
        return ret;
diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile
index bd2174f..f95356f 100644
--- a/board/genesi/mx51_efikamx/Makefile
+++ b/board/genesi/mx51_efikamx/Makefile
@@ -27,11 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= efikamx.o
-
-ifdef	CONFIG_CMD_USB
-COBJS	+= efikamx-usb.o
-endif
+COBJS	:= efikamx.o efikamx-usb.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c
index e9273d0..cf020c3 100644
--- a/board/genesi/mx51_efikamx/efikamx-usb.c
+++ b/board/genesi/mx51_efikamx/efikamx-usb.c
@@ -214,3 +214,15 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
 	if (port)
 		mdelay(10);
 }
+
+/*
+ * Ethernet on the Smarttop is on the USB bus. Rather than give an error about
+ * "CPU Net Initialization Failed", just pass this test since no other settings
+ * are required. Smartbook doesn't have built-in Ethernet but we will let it
+ * pass anyway considering someone may have plugged in a USB stick and all
+ * they need to do is run "usb start".
+ */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 6d98c94..cfd2e93 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -492,9 +492,6 @@ int board_late_init(void)
 					ARRAY_SIZE(efikamx_pata_pads));
 	setup_iomux_usb();
 
-	if (machine_is_efikasb())
-		setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
-
 	return 0;
 }
 
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index 9bc3c21..eaa924f 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -163,7 +163,7 @@ static int ivm_findinventorystring(int type,
 		if (addr == INVENTORYDATASIZE) {
 			xcode = -1;
 			printf("Error end of string not found\n");
-		} else if ((size >= (maxlen - 1)) &&
+		} else if ((size > (maxlen - 1)) &&
 			   (buf[addr] != '\r')) {
 			xcode = -1;
 			printf("string too long till next CR\n");
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 930c80e..be8f51c 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -331,26 +331,6 @@ void board_spi_release_bus(struct spi_slave *slave)
 	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
 }
 
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	/* Fix this */
-	gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
-				kw_sdram_bs(0));
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
-						       kw_sdram_bs(i));
-	}
-}
-
 #if (defined(CONFIG_KM_PIGGY4_88E6061))
 
 #define	PHY_LED_SEL_REG		0x18
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 7ab2040..afe832a 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -45,8 +45,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const struct tegra20_sysinfo sysinfo = {
-	CONFIG_TEGRA20_BOARD_STRING
+const struct tegra_sysinfo sysinfo = {
+	CONFIG_TEGRA_BOARD_STRING
 };
 
 #ifndef CONFIG_SPL_BUILD
@@ -79,7 +79,7 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
 static void power_det_init(void)
 {
 #if defined(CONFIG_TEGRA20)
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
 	/* turn off power detects */
 	writel(0, &pmc->pmc_pwr_det_latch);
@@ -132,7 +132,7 @@ int board_init(void)
 	board_usb_init(gd->fdt_blob);
 #endif
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
 	/* save Sdram params to PMC 2, 4, and 24 for WB0 */
 	warmboot_save_sdram_params();
 
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index c351954..ca5facb 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -54,4 +54,14 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index 3352539..25a63a0 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -153,4 +153,14 @@
 			0x1f04008a>;
 		linux,fn-keymap = <0x05040002>;
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index b6efa1c..88b9dcf 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -24,10 +24,6 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 44977c7..b4a811d 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -73,11 +73,11 @@ int board_mmc_init(bd_t *bd)
 	debug("board_mmc_init: init SD slot J26\n");
 	/* init dev 0, SD slot J26, with 4-bit bus */
 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+	tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
 
 	debug("board_mmc_init: init SD slot J5\n");
 	/* init dev 2, SD slot J5, with 4-bit bus */
-	tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
+	tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
 
 	return 0;
 }
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index b6efa1c..88b9dcf 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -24,10 +24,6 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 3298a6b..667f60a 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -81,11 +81,11 @@ int board_mmc_init(bd_t *bd)
 	debug("board_mmc_init: init eMMC\n");
 	/* init dev 0, eMMC chip, with 4-bit bus */
 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra20_mmc_init(0, 4, -1, -1);
+	tegra_mmc_init(0, 4, -1, -1);
 
 	debug("board_mmc_init: init SD slot\n");
 	/* init dev 1, SD slot, with 4-bit bus */
-	tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
+	tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
 
 	return 0;
 }
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index e3b7435..147d0bc 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -24,9 +24,7 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common $(obj)../seaboard)
-endif
+$(shell mkdir -p $(obj)../seaboard)
 
 LIB	= $(obj)lib$(BOARD).o
 
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile
index a910577..913f1ce 100644
--- a/board/nvidia/whistler/Makefile
+++ b/board/nvidia/whistler/Makefile
@@ -24,10 +24,6 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
index c0a114d..598b2e5 100644
--- a/board/nvidia/whistler/whistler.c
+++ b/board/nvidia/whistler/whistler.c
@@ -81,10 +81,10 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
-	tegra20_mmc_init(0, 8, -1, -1);
+	tegra_mmc_init(0, 8, -1, -1);
 
 	/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
-	tegra20_mmc_init(1, 8, -1, -1);
+	tegra_mmc_init(1, 8, -1, -1);
 
 	return 0;
 }
diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c
index 5e07bf8..06df0af 100644
--- a/board/taskit/stamp9g20/stamp9g20.c
+++ b/board/taskit/stamp9g20/stamp9g20.c
@@ -159,15 +159,28 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int board_init(void)
+int board_postclk_init(void)
 {
-	/* Adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	/*
+	 * Initialize the serial interface here, because be need a running
+	 * timer to set PC9 to high and wait for some time to enable the
+	 * level converter of the RS232 interface on the PortuxG20 board.
+	 */
 
-	/* Enable the serial interface */
+#ifdef CONFIG_PORTUXG20
 	at91_set_gpio_output(AT91_PIN_PC9, 1);
+	mdelay(1);
+#endif
 	at91_seriald_hw_init();
 
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
 	stamp9G20_nand_hw_init();
 #ifdef CONFIG_MACB
 	stamp9G20_macb_hw_init();
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index c2b10ac..7429e93 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -100,8 +100,18 @@ int board_init(void)
 
 int misc_init_r(void)
 {
+	char *eth_addr;
+
 	dieid_num_r();
 
+	eth_addr = getenv("ethaddr");
+	if (eth_addr)
+		return 0;
+
+#ifndef CONFIG_SPL_BUILD
+	TAM3517_READ_MAC_FROM_EEPROM;
+#endif
+
 	return 0;
 }
 
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index 9fbaedd..b8ad447 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -21,13 +21,17 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <malloc.h>
 #include <fpga.h>
+#include <video_fb.h>
 #include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_gpio.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/dss.h>
+#include <asm/arch/clocks.h>
 #include <i2c.h>
 #include <spartan3.h>
 #include <asm/gpio.h>
@@ -39,6 +43,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BUZZER		140
+#define SPEAKER		141
+
 #ifndef CONFIG_FPGA
 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
 #endif
@@ -50,6 +57,42 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FPGA_INIT	119
 #define FPGA_DONE	154
 
+#define LCD_PWR		138
+#define LCD_PON_PIN	139
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct {
+	u32 xres;
+	u32 yres;
+} panel_resolution[] = {
+	{ 480, 272 },
+	{ 800, 480 }
+};
+
+static struct panel_config lcd_cfg[] = {
+	{
+	.timing_h       = PANEL_TIMING_H(4, 8, 41),
+	.timing_v       = PANEL_TIMING_V(2, 4, 10),
+	.pol_freq       = 0x00000000, /* Pol Freq */
+	.divisor        = 0x0001000d, /* 33Mhz Pixel Clock */
+	.panel_type     = 0x01, /* TFT */
+	.data_lines     = 0x03, /* 24 Bit RGB */
+	.load_mode      = 0x02, /* Frame Mode */
+	.panel_color	= 0,
+	},
+	{
+	.timing_h       = PANEL_TIMING_H(20, 192, 4),
+	.timing_v       = PANEL_TIMING_V(2, 20, 10),
+	.pol_freq       = 0x00004000, /* Pol Freq */
+	.divisor        = 0x0001000E, /* 36Mhz Pixel Clock */
+	.panel_type     = 0x01, /* TFT */
+	.data_lines     = 0x03, /* 24 Bit RGB */
+	.load_mode      = 0x02, /* Frame Mode */
+	.panel_color	= 0,
+	}
+};
+#endif
+
 /* Timing definitions for FPGA */
 static const u32 gpmc_fpga[] = {
 	FPGA_GPMC_CONFIG1,
@@ -193,6 +236,33 @@ int board_init(void)
 
 	mt_ventoux_init_fpga();
 
+	/* GPIO_140: speaker #mute */
+	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4))
+	/* GPIO_141: Buzz Hi */
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4))
+
+	/* Turning off the buzzer */
+	gpio_request(BUZZER, "BUZZER_MUTE");
+	gpio_request(SPEAKER, "SPEAKER");
+	gpio_direction_output(BUZZER, 0);
+	gpio_direction_output(SPEAKER, 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char *eth_addr;
+
+	dieid_num_r();
+
+	eth_addr = getenv("ethaddr");
+	if (eth_addr)
+		return 0;
+
+#ifndef CONFIG_SPL_BUILD
+	TAM3517_READ_MAC_FROM_EEPROM;
+#endif
 	return 0;
 }
 
@@ -224,3 +294,46 @@ int board_mmc_init(bd_t *bis)
 	return omap_mmc_init(0, 0, 0);
 }
 #endif
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+int board_video_init(void)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	struct panel_config *panel = &lcd_cfg[0];
+	char *s;
+	u32 index = 0;
+
+	void *fb;
+
+	fb = (void *)0x88000000;
+
+	s = getenv("panel");
+	if (s) {
+		index = simple_strtoul(s, NULL, 10);
+		if (index < ARRAY_SIZE(lcd_cfg))
+			panel = &lcd_cfg[index];
+		else
+			return 0;
+	}
+
+	panel->frame_buffer = fb;
+	printf("Panel: %dx%d\n", panel_resolution[index].xres,
+		panel_resolution[index].yres);
+	panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
+		(panel_resolution[index].xres - 1);
+
+	gpio_request(LCD_PWR, "LCD Power");
+	gpio_request(LCD_PON_PIN, "LCD Pon");
+	gpio_direction_output(LCD_PWR, 0);
+	gpio_direction_output(LCD_PON_PIN, 1);
+
+
+	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+
+	omap3_dss_panel_config(panel);
+	omap3_dss_enable();
+
+	return 0;
+}
+#endif
diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h
index 9b2e43e..1cd7ec2 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.h
+++ b/board/teejet/mt_ventoux/mt_ventoux.h
@@ -142,7 +142,8 @@ const omap3_sysinfo sysinfo = {
 			/*GPIO_62: FPGA_RESET */ \
 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M4)) \
 	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/ \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) \
+			/* GPIO_64*/ \
 	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)) \
 	/* DSS */\
 	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
@@ -174,26 +175,6 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
 	/* CAMERA */\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
@@ -209,6 +190,7 @@ const omap3_sysinfo sysinfo = {
 			/* GPIO_126: CardDetect */\
 	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
 	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+			/*GPIO_128 */ \
 	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
 	\
 	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN | M0)) /*MMC2_CLK*/\
@@ -221,7 +203,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MMC2_DAT5),		(IDIS  | PTU | EN  | M4)) \
 	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | EN  | M4)) \
 			/* GPIO_138: LCD_ENVD */\
-	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTD | EN  | M4)) \
 			/* GPIO_139: LCD_PON */\
 	/* McBSP */\
 	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
@@ -241,16 +223,12 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MCBSP2_DX),		(IEN | PTD | EN | M4)) \
 			/* GPIO_119: FPGA_INIT */ \
 	\
-	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4)) \
-			/* GPIO_140: speaker #mute */\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4)) \
-			/* GPIO_141: Buzz Hi */\
 	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN | M4)) \
 	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN | M4)) \
 	\
 	MUX_VAL(CP(MCBSP4_CLKX),	(IEN | PTD | DIS | M4)) \
 			/*GPIO_152: Ignition Sense */ \
-	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) \
+	MUX_VAL(CP(MCBSP4_DR),		(IEN | PTD | DIS | M4)) \
 			/*GPIO_153: Power Button Sense */ \
 	MUX_VAL(CP(MCBSP4_DX),		(IEN | PTU | DIS | M4)) \
 			/* GPIO_154: FPGA_DONE */ \
@@ -264,10 +242,14 @@ const omap3_sysinfo sysinfo = {
 			/* GPIO_150: USB status 1 */\
 	\
 	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M2)) \
+			/* gpt9_pwm */\
+	MUX_VAL(CP(UART2_RTS),		(IEN | PTD | DIS | M2)) \
+			/* gpt10_pwm */\
+	MUX_VAL(CP(UART2_TX),		(IEN | PTD | DIS | M2)) \
+			/* gpt8_pwm */\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M2)) \
+			/* gpt11_pwm */\
 	\
 	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS  | PTD | DIS | M4)) \
 			/*GPIO_163 : TS_PENIRQ*/ \
@@ -299,22 +281,24 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
 	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) \
 	/* CCDC */\
-	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M4)) \
+			/* GPIO94 */\
 	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M4)) \
 			/* GPIO95: #Enable Output */\
-	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M4)) \
 	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M4)) \
 			/* GPIO 99: #SOM_PWR_OFF */\
-	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M4)) \
 	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M4)) \
 			/* GPIO_100: #power out */\
-	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M4)) \
+			/* GPIO_102 */\
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M4)) \
 	/* RMII */\
 	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
 	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
@@ -363,7 +347,8 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
 	\
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | DIS | M4)) \
+			/* gpio_10 */\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
 	/* JTAG */\
 	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
@@ -387,12 +372,15 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M3)) \
 	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)) \
 	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)) \
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | EN  | M4)) \
+					/* gpio_24 */\
 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M4)) \
+					/* gpio_26 */\
 	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) \
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) \
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
+					/* gpio_29 */\
 	/* Die to Die */\
 	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
 	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
diff --git a/boards.cfg b/boards.cfg
index b4e0d3c..091c79f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -59,7 +59,8 @@ integratorcp_cm920t          arm         arm920t     integrator          armltd
 a320evb                      arm         arm920t     -                   faraday        a320
 at91rm9200ek                 arm         arm920t     at91rm9200ek        atmel          at91        at91rm9200ek
 at91rm9200ek_ram             arm         arm920t     at91rm9200ek        atmel          at91        at91rm9200ek:RAMBOOT
-eb_cpux9k2                   arm         arm920t     -                   BuS            at91
+eb_cpux9k2                   arm         arm920t     eb_cpux9k2          BuS            at91        eb_cpux9k2
+eb_cpux9k2_ram               arm         arm920t     eb_cpux9k2          BuS            at91        eb_cpux9k2:RAMBOOT
 cpuat91                      arm         arm920t     cpuat91             eukrea         at91        cpuat91
 cpuat91_ram                  arm         arm920t     cpuat91             eukrea         at91        cpuat91:RAMBOOT
 mx1ads                       arm         arm920t     -                   -              imx
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 9c6dabe..e24ed7f 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 
 	last = off;
 
-	datbuf = malloc(nand->writesize);
-	oobbuf = malloc(nand->oobsize);
+	datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+	oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
 	if (!datbuf || !oobbuf) {
 		puts("No memory for page buffer\n");
 		return 1;
diff --git a/doc/README.kwbimage b/doc/README.kwbimage
index 6dd942f..e91c387 100644
--- a/doc/README.kwbimage
+++ b/doc/README.kwbimage
@@ -25,13 +25,24 @@ for ex.
 		-T kwbimage -a 0x00600000 -e 0x00600000 \
 		-d u-boot.bin u-boot.kwb
 
-kwimage support available with mkimage utility will generate kirkwood boot
-image that can be flashed on the board NAND/SPI flash
+
+kwbimage support available with mkimage utility will generate kirkwood boot
+image that can be flashed on the board NAND/SPI flash.  The make target
+which uses mkimage to produce such an image is "u-boot.kwb".  For example:
+
+  export BUILD_DIR=/tmp/build
+  make distclean
+  make yourboard_config
+  make $BUILD_DIR/u-boot.kwb
+
 
 Board specific configuration file specifications:
 ------------------------------------------------
-1. This file must present in the $(BOARDDIR) and the name should be
-	kwbimage.cfg (since this is used in Makefile)
+1. This file must present in the $(BOARDDIR).  The default name is
+	kwbimage.cfg.  The name can be set as part of the full path
+        to the file using CONFIG_SYS_KWD_CONFIG (probably in
+        include/configs/<yourboard>.h).   The path should look like:
+        $(SRCTREE)/$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
 2. This file can have empty lines and lines starting with "#" as first
 	character to put comments
 3. This file can have configuration command lines as mentioned below,
diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
new file mode 100644
index 0000000..86ae408
--- /dev/null
+++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
@@ -0,0 +1,53 @@
+NAND Flash
+----------
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot. There should not be Linux-specific or U-Boot specific binding, just
+a binding that describes this hardware. But agreeing a binding in Linux in
+the absence of a driver may be beyond my powers.)
+
+The device node for a NAND flash device is as follows:
+
+Required properties :
+ - compatible : Should be "manufacturer,device", "nand-flash"
+
+This node should sit inside its controller.
+
+
+Nvidia NAND Controller
+----------------------
+
+The device node for a NAND flash controller is as follows:
+
+Optional properties:
+
+nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
+		phandle, parameter, flags
+nvidia,nand-width : bus width of the NAND device in bits
+
+ - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
+	Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
+	TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
+
+	MAX_TRP_TREA is:
+		non-EDO mode: Max(tRP, tREA) + 6ns
+		EDO mode: tRP timing
+
+The 'reg' property should provide the chip select used by the flash chip.
+
+
+Example
+-------
+
+nand-controller@0x70008000 {
+	compatible = "nvidia,tegra20-nand";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+	nvidia,nand-width = <8>;
+	nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+	nand@0 {
+		reg = <0>;
+		compatible = "hynix,hy27uf4g2b", "nand-flash";
+	};
+};
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 8cfcf82..747f4cf 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -34,10 +34,10 @@
 #include <asm/gpio.h>
 
 enum {
-	TEGRA20_CMD_INFO,
-	TEGRA20_CMD_PORT,
-	TEGRA20_CMD_OUTPUT,
-	TEGRA20_CMD_INPUT,
+	TEGRA_CMD_INFO,
+	TEGRA_CMD_PORT,
+	TEGRA_CMD_OUTPUT,
+	TEGRA_CMD_INPUT,
 };
 
 static struct gpio_names {
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index b4eb491..e3be14e 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -262,7 +262,7 @@ exit:
 	return error;
 }
 
-static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len)
 {
 	int error;
 	struct i2c_trans_info trans_info;
@@ -275,12 +275,12 @@ static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
 
 	error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
 	if (error)
-		debug("tegra20_i2c_write_data: Error (%d) !!!\n", error);
+		debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
 
 	return error;
 }
 
-static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len)
 {
 	int error;
 	struct i2c_trans_info trans_info;
@@ -293,7 +293,7 @@ static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
 
 	error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
 	if (error)
-		debug("tegra20_i2c_read_data: Error (%d) !!!\n", error);
+		debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
 
 	return error;
 }
@@ -438,7 +438,7 @@ int i2c_write_data(uchar chip, uchar *buffer, int len)
 	debug("\n");
 
 	/* Shift 7-bit address over for lower-level i2c functions */
-	rc = tegra20_i2c_write_data(chip << 1, buffer, len);
+	rc = tegra_i2c_write_data(chip << 1, buffer, len);
 	if (rc)
 		debug("i2c_write_data(): rc=%d\n", rc);
 
@@ -452,7 +452,7 @@ int i2c_read_data(uchar chip, uchar *buffer, int len)
 
 	debug("inside i2c_read_data():\n");
 	/* Shift 7-bit address over for lower-level i2c functions */
-	rc = tegra20_i2c_read_data(chip << 1, buffer, len);
+	rc = tegra_i2c_read_data(chip << 1, buffer, len);
 	if (rc) {
 		debug("i2c_read_data(): rc=%d\n", rc);
 		return rc;
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 68c6a16..0805e86 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libinput.o
 
 COBJS-$(CONFIG_I8042_KBD) += i8042.o
-COBJS-$(CONFIG_TEGRA20_KEYBOARD) += tegra-kbc.o
+COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
 ifdef CONFIG_PS2KBD
 COBJS-y += keyboard.o pc_keyb.o
 COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 9a98c6b..c80b41b 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -119,6 +119,10 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
 			(uint32_t)(priv->desc->cmd.address + cache_data_count));
 	}
 
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
+			(uint32_t)(priv->desc->cmd.address + cache_data_count));
+
 	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 				(data_count << MXS_DMA_DESC_BYTES_OFFSET);
 
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index ddfa727..ca8fad8 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -25,7 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
-#include "tegra_mmc.h"
+#include <asm/arch/tegra_mmc.h>
 
 /* support 4 mmc hosts */
 struct mmc mmc_dev[4];
@@ -39,31 +39,31 @@ struct mmc_host mmc_host[4];
  * @param host		Structure to fill in (base, reg, mmc_id)
  * @param dev_index	Device index (0-3)
  */
-static void tegra20_get_setup(struct mmc_host *host, int dev_index)
+static void tegra_get_setup(struct mmc_host *host, int dev_index)
 {
-	debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index);
+	debug("tegra_get_setup: dev_index = %d\n", dev_index);
 
 	switch (dev_index) {
 	case 1:
-		host->base = TEGRA20_SDMMC3_BASE;
+		host->base = TEGRA_SDMMC3_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC3;
 		break;
 	case 2:
-		host->base = TEGRA20_SDMMC2_BASE;
+		host->base = TEGRA_SDMMC2_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC2;
 		break;
 	case 3:
-		host->base = TEGRA20_SDMMC1_BASE;
+		host->base = TEGRA_SDMMC1_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC1;
 		break;
 	case 0:
 	default:
-		host->base = TEGRA20_SDMMC4_BASE;
+		host->base = TEGRA_SDMMC4_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC4;
 		break;
 	}
 
-	host->reg = (struct tegra20_mmc *)host->base;
+	host->reg = (struct tegra_mmc *)host->base;
 }
 
 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
@@ -345,7 +345,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
 	debug(" mmc_change_clock called\n");
 
 	/*
-	 * Change Tegra20 SDMMCx clock divisor here. Source is 216MHz,
+	 * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
 	 * PLLP_OUT0
 	 */
 	if (clock == 0)
@@ -494,11 +494,11 @@ static int mmc_core_init(struct mmc *mmc)
 	return 0;
 }
 
-int tegra20_mmc_getcd(struct mmc *mmc)
+int tegra_mmc_getcd(struct mmc *mmc)
 {
 	struct mmc_host *host = (struct mmc_host *)mmc->priv;
 
-	debug("tegra20_mmc_getcd called\n");
+	debug("tegra_mmc_getcd called\n");
 
 	if (host->cd_gpio >= 0)
 		return !gpio_get_value(host->cd_gpio);
@@ -506,13 +506,13 @@ int tegra20_mmc_getcd(struct mmc *mmc)
 	return 1;
 }
 
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 {
 	struct mmc_host *host;
 	char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 	struct mmc *mmc;
 
-	debug(" tegra20_mmc_init: index %d, bus width %d "
+	debug(" tegra_mmc_init: index %d, bus width %d "
 		"pwr_gpio %d cd_gpio %d\n",
 		dev_index, bus_width, pwr_gpio, cd_gpio);
 
@@ -521,7 +521,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 	host->clock = 0;
 	host->pwr_gpio = pwr_gpio;
 	host->cd_gpio = cd_gpio;
-	tegra20_get_setup(host, dev_index);
+	tegra_get_setup(host, dev_index);
 
 	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 
@@ -539,12 +539,12 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
 	mmc = &mmc_dev[dev_index];
 
-	sprintf(mmc->name, "Tegra20 SD/MMC");
+	sprintf(mmc->name, "Tegra SD/MMC");
 	mmc->priv = host;
 	mmc->send_cmd = mmc_send_cmd;
 	mmc->set_ios = mmc_set_ios;
 	mmc->init = mmc_core_init;
-	mmc->getcd = tegra20_mmc_getcd;
+	mmc->getcd = tegra_mmc_getcd;
 
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	if (bus_width == 8)
@@ -559,7 +559,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 	 * max freq is highest HS eMMC clock as per the SD/MMC spec
 	 *  (actually 52MHz)
 	 * Both of these are the closest equivalents w/216MHz source
-	 *  clock and Tegra20 SDMMC divisors.
+	 *  clock and Tegra SDMMC divisors.
 	 */
 	mmc->f_min = 375000;
 	mmc->f_max = 48000000;
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 29dc20e..beb99ca 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -62,6 +62,7 @@ COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
 COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
+COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
 endif
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index bf9414f..4701be8 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -25,10 +25,10 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 
+#include <common.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/types.h>
-#include <common.h>
 #include <malloc.h>
 #include <asm/errno.h>
 #include <asm/io.h>
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 390ff90..71f5027 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2934,7 +2934,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 
 	if (!(chip->options & NAND_OWN_BUFFERS))
-		chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+		chip->buffers = memalign(ARCH_DMA_MINALIGN,
+					 sizeof(*chip->buffers));
 	if (!chip->buffers)
 		return -ENOMEM;
 
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
new file mode 100644
index 0000000..8c1de34
--- /dev/null
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -0,0 +1,1026 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/gpio.h>
+#include <asm/errno.h>
+#include <asm-generic/gpio.h>
+#include <fdtdec.h>
+#include "tegra_nand.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NAND_CMD_TIMEOUT_MS		10
+
+#define SKIPPED_SPARE_BYTES		4
+
+/* ECC bytes to be generated for tag data */
+#define TAG_ECC_BYTES			4
+
+/* 64 byte oob block info for large page (== 2KB) device
+ *
+ * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
+ *      Skipped bytes(4)
+ *      Main area Ecc(36)
+ *      Tag data(20)
+ *      Tag data Ecc(4)
+ *
+ * Yaffs2 will use 16 tag bytes.
+ */
+static struct nand_ecclayout eccoob = {
+	.eccbytes = 36,
+	.eccpos = {
+		4,  5,  6,  7,  8,  9,  10, 11, 12,
+		13, 14, 15, 16, 17, 18, 19, 20, 21,
+		22, 23, 24, 25, 26, 27, 28, 29, 30,
+		31, 32, 33, 34, 35, 36, 37, 38, 39,
+	},
+	.oobavail = 20,
+	.oobfree = {
+			{
+			.offset = 40,
+			.length = 20,
+			},
+	}
+};
+
+enum {
+	ECC_OK,
+	ECC_TAG_ERROR = 1 << 0,
+	ECC_DATA_ERROR = 1 << 1
+};
+
+/* Timing parameters */
+enum {
+	FDT_NAND_MAX_TRP_TREA,
+	FDT_NAND_TWB,
+	FDT_NAND_MAX_TCR_TAR_TRR,
+	FDT_NAND_TWHR,
+	FDT_NAND_MAX_TCS_TCH_TALS_TALH,
+	FDT_NAND_TWH,
+	FDT_NAND_TWP,
+	FDT_NAND_TRH,
+	FDT_NAND_TADL,
+
+	FDT_NAND_TIMING_COUNT
+};
+
+/* Information about an attached NAND chip */
+struct fdt_nand {
+	struct nand_ctlr *reg;
+	int enabled;		/* 1 to enable, 0 to disable */
+	struct fdt_gpio_state wp_gpio;	/* write-protect GPIO */
+	s32 width;		/* bit width, normally 8 */
+	u32 timing[FDT_NAND_TIMING_COUNT];
+};
+
+struct nand_drv {
+	struct nand_ctlr *reg;
+
+	/*
+	* When running in PIO mode to get READ ID bytes from register
+	* RESP_0, we need this variable as an index to know which byte in
+	* register RESP_0 should be read.
+	* Because common code in nand_base.c invokes read_byte function two
+	* times for NAND_CMD_READID.
+	* And our controller returns 4 bytes at once in register RESP_0.
+	*/
+	int pio_byte_index;
+	struct fdt_nand config;
+};
+
+static struct nand_drv nand_ctrl;
+static struct mtd_info *our_mtd;
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+#ifdef CONFIG_SYS_DCACHE_OFF
+static inline void dma_prepare(void *start, unsigned long length,
+			       int is_writing)
+{
+}
+#else
+/**
+ * Prepare for a DMA transaction
+ *
+ * For a write we flush out our data. For a read we invalidate, since we
+ * need to do this before we read from the buffer after the DMA has
+ * completed, so may as well do it now.
+ *
+ * @param start		Start address for DMA buffer (should be cache-aligned)
+ * @param length	Length of DMA buffer in bytes
+ * @param is_writing	0 if reading, non-zero if writing
+ */
+static void dma_prepare(void *start, unsigned long length, int is_writing)
+{
+	unsigned long addr = (unsigned long)start;
+
+	length = ALIGN(length, ARCH_DMA_MINALIGN);
+	if (is_writing)
+		flush_dcache_range(addr, addr + length);
+	else
+		invalidate_dcache_range(addr, addr + length);
+}
+#endif
+
+/**
+ * Wait for command completion
+ *
+ * @param reg	nand_ctlr structure
+ * @return
+ *	1 - Command completed
+ *	0 - Timeout
+ */
+static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
+{
+	u32 reg_val;
+	int running;
+	int i;
+
+	for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
+		if ((readl(&reg->command) & CMD_GO) ||
+				!(readl(&reg->status) & STATUS_RBSY0) ||
+				!(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
+			udelay(1);
+			continue;
+		}
+		reg_val = readl(&reg->dma_mst_ctrl);
+		/*
+		 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
+		 * is set, that means DMA engine is running.
+		 *
+		 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
+		 * is cleared, indicating DMA transfer completion.
+		 */
+		running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
+				DMA_MST_CTRL_EN_B_ENABLE);
+		if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
+			return 1;
+		udelay(1);
+	}
+	return 0;
+}
+
+/**
+ * Read one byte from the chip
+ *
+ * @param mtd	MTD device structure
+ * @return	data byte
+ *
+ * Read function for 8bit bus-width
+ */
+static uint8_t read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	u32 dword_read;
+	struct nand_drv *info;
+
+	info = (struct nand_drv *)chip->priv;
+
+	/* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
+	if (info->pio_byte_index > 3) {
+		info->pio_byte_index = 0;
+		writel(CMD_GO | CMD_PIO
+			| CMD_RX | CMD_CE0,
+			&info->reg->command);
+		if (!nand_waitfor_cmd_completion(info->reg))
+			printf("Command timeout\n");
+	}
+
+	dword_read = readl(&info->reg->resp);
+	dword_read = dword_read >> (8 * info->pio_byte_index);
+	info->pio_byte_index++;
+	return (uint8_t)dword_read;
+}
+
+/**
+ * Check NAND status to see if it is ready or not
+ *
+ * @param mtd	MTD device structure
+ * @return
+ *	1 - ready
+ *	0 - not ready
+ */
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	int reg_val;
+	struct nand_drv *info;
+
+	info = (struct nand_drv *)chip->priv;
+
+	reg_val = readl(&info->reg->status);
+	if (reg_val & STATUS_RBSY0)
+		return 1;
+	else
+		return 0;
+}
+
+/* Dummy implementation: we don't support multiple chips */
+static void nand_select_chip(struct mtd_info *mtd, int chipnr)
+{
+	switch (chipnr) {
+	case -1:
+	case 0:
+		break;
+
+	default:
+		BUG();
+	}
+}
+
+/**
+ * Clear all interrupt status bits
+ *
+ * @param reg	nand_ctlr structure
+ */
+static void nand_clear_interrupt_status(struct nand_ctlr *reg)
+{
+	u32 reg_val;
+
+	/* Clear interrupt status */
+	reg_val = readl(&reg->isr);
+	writel(reg_val, &reg->isr);
+}
+
+/**
+ * Send command to NAND device
+ *
+ * @param mtd		MTD device structure
+ * @param command	the command to be sent
+ * @param column	the column address for this command, -1 if none
+ * @param page_addr	the page address for this command, -1 if none
+ */
+static void nand_command(struct mtd_info *mtd, unsigned int command,
+	int column, int page_addr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct nand_drv *info;
+
+	info = (struct nand_drv *)chip->priv;
+
+	/*
+	 * Write out the command to the device.
+	 *
+	 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
+	 * here before mtd->writesize is initialized.
+	 */
+
+	/* Emulate NAND_CMD_READOOB */
+	if (command == NAND_CMD_READOOB) {
+		assert(mtd->writesize != 0);
+		column += mtd->writesize;
+		command = NAND_CMD_READ0;
+	}
+
+	/* Adjust columns for 16 bit bus-width */
+	if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
+		column >>= 1;
+
+	nand_clear_interrupt_status(info->reg);
+
+	/* Stop DMA engine, clear DMA completion status */
+	writel(DMA_MST_CTRL_EN_A_DISABLE
+		| DMA_MST_CTRL_EN_B_DISABLE
+		| DMA_MST_CTRL_IS_DMA_DONE,
+		&info->reg->dma_mst_ctrl);
+
+	/*
+	 * Program and erase have their own busy handlers
+	 * status and sequential in needs no delay
+	 */
+	switch (command) {
+	case NAND_CMD_READID:
+		writel(NAND_CMD_READID, &info->reg->cmd_reg1);
+		writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
+			| CMD_RX |
+			((4 - 1) << CMD_TRANS_SIZE_SHIFT)
+			| CMD_CE0,
+			&info->reg->command);
+		info->pio_byte_index = 0;
+		break;
+	case NAND_CMD_READ0:
+		writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
+		writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
+		writel((page_addr << 16) | (column & 0xFFFF),
+			&info->reg->addr_reg1);
+		writel(page_addr >> 16, &info->reg->addr_reg2);
+		return;
+	case NAND_CMD_SEQIN:
+		writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
+		writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
+		writel((page_addr << 16) | (column & 0xFFFF),
+			&info->reg->addr_reg1);
+		writel(page_addr >> 16,
+			&info->reg->addr_reg2);
+		return;
+	case NAND_CMD_PAGEPROG:
+		return;
+	case NAND_CMD_ERASE1:
+		writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
+		writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
+		writel(page_addr, &info->reg->addr_reg1);
+		writel(CMD_GO | CMD_CLE | CMD_ALE |
+			CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
+			&info->reg->command);
+		break;
+	case NAND_CMD_ERASE2:
+		return;
+	case NAND_CMD_STATUS:
+		writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
+		writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
+			| ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
+			| CMD_CE0,
+			&info->reg->command);
+		info->pio_byte_index = 0;
+		break;
+	case NAND_CMD_RESET:
+		writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
+		writel(CMD_GO | CMD_CLE | CMD_CE0,
+			&info->reg->command);
+		break;
+	case NAND_CMD_RNDOUT:
+	default:
+		printf("%s: Unsupported command %d\n", __func__, command);
+		return;
+	}
+	if (!nand_waitfor_cmd_completion(info->reg))
+		printf("Command 0x%02X timeout\n", command);
+}
+
+/**
+ * Check whether the pointed buffer are all 0xff (blank).
+ *
+ * @param buf	data buffer for blank check
+ * @param len	length of the buffer in byte
+ * @return
+ *	1 - blank
+ *	0 - non-blank
+ */
+static int blank_check(u8 *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != 0xFF)
+			return 0;
+	return 1;
+}
+
+/**
+ * After a DMA transfer for read, we call this function to see whether there
+ * is any uncorrectable error on the pointed data buffer or oob buffer.
+ *
+ * @param reg		nand_ctlr structure
+ * @param databuf	data buffer
+ * @param a_len		data buffer length
+ * @param oobbuf	oob buffer
+ * @param b_len		oob buffer length
+ * @return
+ *	ECC_OK - no ECC error or correctable ECC error
+ *	ECC_TAG_ERROR - uncorrectable tag ECC error
+ *	ECC_DATA_ERROR - uncorrectable data ECC error
+ *	ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
+ */
+static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
+	int a_len, u8 *oobbuf, int b_len)
+{
+	int return_val = ECC_OK;
+	u32 reg_val;
+
+	if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
+		return ECC_OK;
+
+	/*
+	 * Area A is used for the data block (databuf). Area B is used for
+	 * the spare block (oobbuf)
+	 */
+	reg_val = readl(&reg->dec_status);
+	if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
+		reg_val = readl(&reg->bch_dec_status_buf);
+		/*
+		 * If uncorrectable error occurs on data area, then see whether
+		 * they are all FF. If all are FF, it's a blank page.
+		 * Not error.
+		 */
+		if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
+				!blank_check(databuf, a_len))
+			return_val |= ECC_DATA_ERROR;
+	}
+
+	if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
+		reg_val = readl(&reg->bch_dec_status_buf);
+		/*
+		 * If uncorrectable error occurs on tag area, then see whether
+		 * they are all FF. If all are FF, it's a blank page.
+		 * Not error.
+		 */
+		if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
+				!blank_check(oobbuf, b_len))
+			return_val |= ECC_TAG_ERROR;
+	}
+
+	return return_val;
+}
+
+/**
+ * Set GO bit to send command to device
+ *
+ * @param reg	nand_ctlr structure
+ */
+static void start_command(struct nand_ctlr *reg)
+{
+	u32 reg_val;
+
+	reg_val = readl(&reg->command);
+	reg_val |= CMD_GO;
+	writel(reg_val, &reg->command);
+}
+
+/**
+ * Clear command GO bit, DMA GO bit, and DMA completion status
+ *
+ * @param reg	nand_ctlr structure
+ */
+static void stop_command(struct nand_ctlr *reg)
+{
+	/* Stop command */
+	writel(0, &reg->command);
+
+	/* Stop DMA engine and clear DMA completion status */
+	writel(DMA_MST_CTRL_GO_DISABLE
+		| DMA_MST_CTRL_IS_DMA_DONE,
+		&reg->dma_mst_ctrl);
+}
+
+/**
+ * Set up NAND bus width and page size
+ *
+ * @param info		nand_info structure
+ * @param *reg_val	address of reg_val
+ * @return 0 if ok, -1 on error
+ */
+static int set_bus_width_page_size(struct fdt_nand *config,
+	u32 *reg_val)
+{
+	if (config->width == 8)
+		*reg_val = CFG_BUS_WIDTH_8BIT;
+	else if (config->width == 16)
+		*reg_val = CFG_BUS_WIDTH_16BIT;
+	else {
+		debug("%s: Unsupported bus width %d\n", __func__,
+		      config->width);
+		return -1;
+	}
+
+	if (our_mtd->writesize == 512)
+		*reg_val |= CFG_PAGE_SIZE_512;
+	else if (our_mtd->writesize == 2048)
+		*reg_val |= CFG_PAGE_SIZE_2048;
+	else if (our_mtd->writesize == 4096)
+		*reg_val |= CFG_PAGE_SIZE_4096;
+	else {
+		debug("%s: Unsupported page size %d\n", __func__,
+		      our_mtd->writesize);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * Page read/write function
+ *
+ * @param mtd		mtd info structure
+ * @param chip		nand chip info structure
+ * @param buf		data buffer
+ * @param page		page number
+ * @param with_ecc	1 to enable ECC, 0 to disable ECC
+ * @param is_writing	0 for read, 1 for write
+ * @return	0 when successfully completed
+ *		-EIO when command timeout
+ */
+static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
+	uint8_t *buf, int page, int with_ecc, int is_writing)
+{
+	u32 reg_val;
+	int tag_size;
+	struct nand_oobfree *free = chip->ecc.layout->oobfree;
+	/* 4*128=512 (byte) is the value that our HW can support. */
+	ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
+	char *tag_ptr;
+	struct nand_drv *info;
+	struct fdt_nand *config;
+
+	if ((uintptr_t)buf & 0x03) {
+		printf("buf %p has to be 4-byte aligned\n", buf);
+		return -EINVAL;
+	}
+
+	info = (struct nand_drv *)chip->priv;
+	config = &info->config;
+	if (set_bus_width_page_size(config, &reg_val))
+		return -EINVAL;
+
+	/* Need to be 4-byte aligned */
+	tag_ptr = (char *)tag_buf;
+
+	stop_command(info->reg);
+
+	writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
+	writel(virt_to_phys(buf), &info->reg->data_block_ptr);
+
+	if (with_ecc) {
+		writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
+		if (is_writing)
+			memcpy(tag_ptr, chip->oob_poi + free->offset,
+				chip->ecc.layout->oobavail +
+				TAG_ECC_BYTES);
+	} else {
+		writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
+	}
+
+	/* Set ECC selection, configure ECC settings */
+	if (with_ecc) {
+		tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
+		reg_val |= (CFG_SKIP_SPARE_SEL_4
+			| CFG_SKIP_SPARE_ENABLE
+			| CFG_HW_ECC_CORRECTION_ENABLE
+			| CFG_ECC_EN_TAG_DISABLE
+			| CFG_HW_ECC_SEL_RS
+			| CFG_HW_ECC_ENABLE
+			| CFG_TVAL4
+			| (tag_size - 1));
+
+		if (!is_writing)
+			tag_size += SKIPPED_SPARE_BYTES;
+		dma_prepare(tag_ptr, tag_size, is_writing);
+	} else {
+		tag_size = mtd->oobsize;
+		reg_val |= (CFG_SKIP_SPARE_DISABLE
+			| CFG_HW_ECC_CORRECTION_DISABLE
+			| CFG_ECC_EN_TAG_DISABLE
+			| CFG_HW_ECC_DISABLE
+			| (tag_size - 1));
+		dma_prepare(chip->oob_poi, tag_size, is_writing);
+	}
+	writel(reg_val, &info->reg->config);
+
+	dma_prepare(buf, 1 << chip->page_shift, is_writing);
+
+	writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
+
+	writel(tag_size - 1, &info->reg->dma_cfg_b);
+
+	nand_clear_interrupt_status(info->reg);
+
+	reg_val = CMD_CLE | CMD_ALE
+		| CMD_SEC_CMD
+		| (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
+		| CMD_A_VALID
+		| CMD_B_VALID
+		| (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
+		| CMD_CE0;
+	if (!is_writing)
+		reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
+	else
+		reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
+	writel(reg_val, &info->reg->command);
+
+	/* Setup DMA engine */
+	reg_val = DMA_MST_CTRL_GO_ENABLE
+		| DMA_MST_CTRL_BURST_8WORDS
+		| DMA_MST_CTRL_EN_A_ENABLE
+		| DMA_MST_CTRL_EN_B_ENABLE;
+
+	if (!is_writing)
+		reg_val |= DMA_MST_CTRL_DIR_READ;
+	else
+		reg_val |= DMA_MST_CTRL_DIR_WRITE;
+
+	writel(reg_val, &info->reg->dma_mst_ctrl);
+
+	start_command(info->reg);
+
+	if (!nand_waitfor_cmd_completion(info->reg)) {
+		if (!is_writing)
+			printf("Read Page 0x%X timeout ", page);
+		else
+			printf("Write Page 0x%X timeout ", page);
+		if (with_ecc)
+			printf("with ECC");
+		else
+			printf("without ECC");
+		printf("\n");
+		return -EIO;
+	}
+
+	if (with_ecc && !is_writing) {
+		memcpy(chip->oob_poi, tag_ptr,
+			SKIPPED_SPARE_BYTES);
+		memcpy(chip->oob_poi + free->offset,
+			tag_ptr + SKIPPED_SPARE_BYTES,
+			chip->ecc.layout->oobavail);
+		reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
+			1 << chip->page_shift,
+			(u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
+			chip->ecc.layout->oobavail);
+		if (reg_val & ECC_TAG_ERROR)
+			printf("Read Page 0x%X tag ECC error\n", page);
+		if (reg_val & ECC_DATA_ERROR)
+			printf("Read Page 0x%X data ECC error\n",
+				page);
+		if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
+			return -EIO;
+	}
+	return 0;
+}
+
+/**
+ * Hardware ecc based page read function
+ *
+ * @param mtd	mtd info structure
+ * @param chip	nand chip info structure
+ * @param buf	buffer to store read data
+ * @param page	page number to read
+ * @return	0 when successfully completed
+ *		-EIO when command timeout
+ */
+static int nand_read_page_hwecc(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int page)
+{
+	return nand_rw_page(mtd, chip, buf, page, 1, 0);
+}
+
+/**
+ * Hardware ecc based page write function
+ *
+ * @param mtd	mtd info structure
+ * @param chip	nand chip info structure
+ * @param buf	data buffer
+ */
+static void nand_write_page_hwecc(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf)
+{
+	int page;
+	struct nand_drv *info;
+
+	info = (struct nand_drv *)chip->priv;
+
+	page = (readl(&info->reg->addr_reg1) >> 16) |
+		(readl(&info->reg->addr_reg2) << 16);
+
+	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
+}
+
+
+/**
+ * Read raw page data without ecc
+ *
+ * @param mtd	mtd info structure
+ * @param chip	nand chip info structure
+ * @param buf	buffer to store read data
+ * @param page	page number to read
+ * @return	0 when successfully completed
+ *		-EINVAL when chip->oob_poi is not double-word aligned
+ *		-EIO when command timeout
+ */
+static int nand_read_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int page)
+{
+	return nand_rw_page(mtd, chip, buf, page, 0, 0);
+}
+
+/**
+ * Raw page write function
+ *
+ * @param mtd	mtd info structure
+ * @param chip	nand chip info structure
+ * @param buf	data buffer
+ */
+static void nand_write_page_raw(struct mtd_info *mtd,
+		struct nand_chip *chip,	const uint8_t *buf)
+{
+	int page;
+	struct nand_drv *info;
+
+	info = (struct nand_drv *)chip->priv;
+	page = (readl(&info->reg->addr_reg1) >> 16) |
+		(readl(&info->reg->addr_reg2) << 16);
+
+	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
+}
+
+/**
+ * OOB data read/write function
+ *
+ * @param mtd		mtd info structure
+ * @param chip		nand chip info structure
+ * @param page		page number to read
+ * @param with_ecc	1 to enable ECC, 0 to disable ECC
+ * @param is_writing	0 for read, 1 for write
+ * @return	0 when successfully completed
+ *		-EINVAL when chip->oob_poi is not double-word aligned
+ *		-EIO when command timeout
+ */
+static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
+	int page, int with_ecc, int is_writing)
+{
+	u32 reg_val;
+	int tag_size;
+	struct nand_oobfree *free = chip->ecc.layout->oobfree;
+	struct nand_drv *info;
+
+	if (((int)chip->oob_poi) & 0x03)
+		return -EINVAL;
+	info = (struct nand_drv *)chip->priv;
+	if (set_bus_width_page_size(&info->config, &reg_val))
+		return -EINVAL;
+
+	stop_command(info->reg);
+
+	writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
+
+	/* Set ECC selection */
+	tag_size = mtd->oobsize;
+	if (with_ecc)
+		reg_val |= CFG_ECC_EN_TAG_ENABLE;
+	else
+		reg_val |= (CFG_ECC_EN_TAG_DISABLE);
+
+	reg_val |= ((tag_size - 1) |
+		CFG_SKIP_SPARE_DISABLE |
+		CFG_HW_ECC_CORRECTION_DISABLE |
+		CFG_HW_ECC_DISABLE);
+	writel(reg_val, &info->reg->config);
+
+	dma_prepare(chip->oob_poi, tag_size, is_writing);
+
+	writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
+
+	if (is_writing && with_ecc)
+		tag_size -= TAG_ECC_BYTES;
+
+	writel(tag_size - 1, &info->reg->dma_cfg_b);
+
+	nand_clear_interrupt_status(info->reg);
+
+	reg_val = CMD_CLE | CMD_ALE
+		| CMD_SEC_CMD
+		| (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
+		| CMD_B_VALID
+		| CMD_CE0;
+	if (!is_writing)
+		reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
+	else
+		reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
+	writel(reg_val, &info->reg->command);
+
+	/* Setup DMA engine */
+	reg_val = DMA_MST_CTRL_GO_ENABLE
+		| DMA_MST_CTRL_BURST_8WORDS
+		| DMA_MST_CTRL_EN_B_ENABLE;
+	if (!is_writing)
+		reg_val |= DMA_MST_CTRL_DIR_READ;
+	else
+		reg_val |= DMA_MST_CTRL_DIR_WRITE;
+
+	writel(reg_val, &info->reg->dma_mst_ctrl);
+
+	start_command(info->reg);
+
+	if (!nand_waitfor_cmd_completion(info->reg)) {
+		if (!is_writing)
+			printf("Read OOB of Page 0x%X timeout\n", page);
+		else
+			printf("Write OOB of Page 0x%X timeout\n", page);
+		return -EIO;
+	}
+
+	if (with_ecc && !is_writing) {
+		reg_val = (u32)check_ecc_error(info->reg, 0, 0,
+			(u8 *)(chip->oob_poi + free->offset),
+			chip->ecc.layout->oobavail);
+		if (reg_val & ECC_TAG_ERROR)
+			printf("Read OOB of Page 0x%X tag ECC error\n", page);
+	}
+	return 0;
+}
+
+/**
+ * OOB data read function
+ *
+ * @param mtd		mtd info structure
+ * @param chip		nand chip info structure
+ * @param page		page number to read
+ * @param sndcmd	flag whether to issue read command or not
+ * @return	1 - issue read command next time
+ *		0 - not to issue
+ */
+static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+	int page, int sndcmd)
+{
+	if (sndcmd) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		sndcmd = 0;
+	}
+	nand_rw_oob(mtd, chip, page, 0, 0);
+	return sndcmd;
+}
+
+/**
+ * OOB data write function
+ *
+ * @param mtd	mtd info structure
+ * @param chip	nand chip info structure
+ * @param page	page number to write
+ * @return	0 when successfully completed
+ *		-EINVAL when chip->oob_poi is not double-word aligned
+ *		-EIO when command timeout
+ */
+static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+	int page)
+{
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+	return nand_rw_oob(mtd, chip, page, 0, 1);
+}
+
+/**
+ * Set up NAND memory timings according to the provided parameters
+ *
+ * @param timing	Timing parameters
+ * @param reg		NAND controller register address
+ */
+static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
+			 struct nand_ctlr *reg)
+{
+	u32 reg_val, clk_rate, clk_period, time_val;
+
+	clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
+		CLOCK_ID_PERIPH) / 1000000;
+	clk_period = 1000 / clk_rate;
+	reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
+		TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
+	reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
+		TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
+	time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
+	if (time_val > 2)
+		reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
+			TIMING_TCR_TAR_TRR_CNT_MASK;
+	reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
+		TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
+	time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
+	if (time_val > 1)
+		reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
+			TIMING_TCS_CNT_MASK;
+	reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
+		TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
+	reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
+		TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
+	reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
+		TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
+	reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
+		TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
+	writel(reg_val, &reg->timing);
+
+	reg_val = 0;
+	time_val = timing[FDT_NAND_TADL] / clk_period;
+	if (time_val > 2)
+		reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
+	writel(reg_val, &reg->timing2);
+}
+
+/**
+ * Decode NAND parameters from the device tree
+ *
+ * @param blob	Device tree blob
+ * @param node	Node containing "nand-flash" compatble node
+ * @return 0 if ok, -ve on error (FDT_ERR_...)
+ */
+static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
+{
+	int err;
+
+	config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	config->enabled = fdtdec_get_is_enabled(blob, node);
+	config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
+	err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
+				 &config->wp_gpio);
+	if (err)
+		return err;
+	err = fdtdec_get_int_array(blob, node, "nvidia,timing",
+			config->timing, FDT_NAND_TIMING_COUNT);
+	if (err < 0)
+		return err;
+
+	/* Now look up the controller and decode that */
+	node = fdt_next_node(blob, node, NULL);
+	if (node < 0)
+		return node;
+
+	return 0;
+}
+
+/**
+ * Board-specific NAND initialization
+ *
+ * @param nand	nand chip info structure
+ * @return 0, after initialized, -1 on error
+ */
+int tegra_nand_init(struct nand_chip *nand, int devnum)
+{
+	struct nand_drv *info = &nand_ctrl;
+	struct fdt_nand *config = &info->config;
+	int node, ret;
+
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+				      COMPAT_NVIDIA_TEGRA20_NAND);
+	if (node < 0)
+		return -1;
+	if (fdt_decode_nand(gd->fdt_blob, node, config)) {
+		printf("Could not decode nand-flash in device tree\n");
+		return -1;
+	}
+	if (!config->enabled)
+		return -1;
+	info->reg = config->reg;
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.layout = &eccoob;
+
+	nand->options = LP_OPTIONS;
+	nand->cmdfunc = nand_command;
+	nand->read_byte = read_byte;
+	nand->ecc.read_page = nand_read_page_hwecc;
+	nand->ecc.write_page = nand_write_page_hwecc;
+	nand->ecc.read_page_raw = nand_read_page_raw;
+	nand->ecc.write_page_raw = nand_write_page_raw;
+	nand->ecc.read_oob = nand_read_oob;
+	nand->ecc.write_oob = nand_write_oob;
+	nand->select_chip = nand_select_chip;
+	nand->dev_ready  = nand_dev_ready;
+	nand->priv = &nand_ctrl;
+
+	/* Adjust controller clock rate */
+	clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
+
+	/* Adjust timing for NAND device */
+	setup_timing(config->timing, info->reg);
+
+	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
+	fdtdec_setup_gpio(&config->wp_gpio);
+	gpio_direction_output(config->wp_gpio.gpio, 1);
+
+	our_mtd = &nand_info[devnum];
+	our_mtd->priv = nand;
+	ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
+	if (ret)
+		return ret;
+
+	nand->ecc.size = our_mtd->writesize;
+	nand->ecc.bytes = our_mtd->oobsize;
+
+	ret = nand_scan_tail(our_mtd);
+	if (ret)
+		return ret;
+
+	ret = nand_register(devnum);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void board_nand_init(void)
+{
+	struct nand_chip *nand = &nand_chip[0];
+
+	if (tegra_nand_init(nand, 0))
+		puts("Tegra NAND init failed\n");
+}
diff --git a/drivers/mtd/nand/tegra_nand.h b/drivers/mtd/nand/tegra_nand.h
new file mode 100644
index 0000000..7e74be7
--- /dev/null
+++ b/drivers/mtd/nand/tegra_nand.h
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* register offset */
+#define COMMAND_0		0x00
+#define CMD_GO			(1 << 31)
+#define CMD_CLE			(1 << 30)
+#define CMD_ALE			(1 << 29)
+#define CMD_PIO			(1 << 28)
+#define CMD_TX			(1 << 27)
+#define CMD_RX			(1 << 26)
+#define CMD_SEC_CMD		(1 << 25)
+#define CMD_AFT_DAT_MASK	(1 << 24)
+#define CMD_AFT_DAT_DISABLE	0
+#define CMD_AFT_DAT_ENABLE	(1 << 24)
+#define CMD_TRANS_SIZE_SHIFT	20
+#define CMD_TRANS_SIZE_PAGE	8
+#define CMD_A_VALID		(1 << 19)
+#define CMD_B_VALID		(1 << 18)
+#define CMD_RD_STATUS_CHK	(1 << 17)
+#define CMD_R_BSY_CHK		(1 << 16)
+#define CMD_CE7			(1 << 15)
+#define CMD_CE6			(1 << 14)
+#define CMD_CE5			(1 << 13)
+#define CMD_CE4			(1 << 12)
+#define CMD_CE3			(1 << 11)
+#define CMD_CE2			(1 << 10)
+#define CMD_CE1			(1 << 9)
+#define CMD_CE0			(1 << 8)
+#define CMD_CLE_BYTE_SIZE_SHIFT	4
+enum {
+	CMD_CLE_BYTES1 = 0,
+	CMD_CLE_BYTES2,
+	CMD_CLE_BYTES3,
+	CMD_CLE_BYTES4,
+};
+#define CMD_ALE_BYTE_SIZE_SHIFT	0
+enum {
+	CMD_ALE_BYTES1 = 0,
+	CMD_ALE_BYTES2,
+	CMD_ALE_BYTES3,
+	CMD_ALE_BYTES4,
+	CMD_ALE_BYTES5,
+	CMD_ALE_BYTES6,
+	CMD_ALE_BYTES7,
+	CMD_ALE_BYTES8
+};
+
+#define STATUS_0			0x04
+#define STATUS_RBSY0			(1 << 8)
+
+#define ISR_0				0x08
+#define ISR_IS_CMD_DONE			(1 << 5)
+#define ISR_IS_ECC_ERR			(1 << 4)
+
+#define IER_0				0x0C
+
+#define CFG_0				0x10
+#define CFG_HW_ECC_MASK			(1 << 31)
+#define CFG_HW_ECC_DISABLE		0
+#define CFG_HW_ECC_ENABLE		(1 << 31)
+#define CFG_HW_ECC_SEL_MASK		(1 << 30)
+#define CFG_HW_ECC_SEL_HAMMING		0
+#define CFG_HW_ECC_SEL_RS		(1 << 30)
+#define CFG_HW_ECC_CORRECTION_MASK	(1 << 29)
+#define CFG_HW_ECC_CORRECTION_DISABLE	0
+#define CFG_HW_ECC_CORRECTION_ENABLE	(1 << 29)
+#define CFG_PIPELINE_EN_MASK		(1 << 28)
+#define CFG_PIPELINE_EN_DISABLE		0
+#define CFG_PIPELINE_EN_ENABLE		(1 << 28)
+#define CFG_ECC_EN_TAG_MASK		(1 << 27)
+#define CFG_ECC_EN_TAG_DISABLE		0
+#define CFG_ECC_EN_TAG_ENABLE		(1 << 27)
+#define CFG_TVALUE_MASK			(3 << 24)
+enum {
+	CFG_TVAL4 = 0 << 24,
+	CFG_TVAL6 = 1 << 24,
+	CFG_TVAL8 = 2 << 24
+};
+#define CFG_SKIP_SPARE_MASK		(1 << 23)
+#define CFG_SKIP_SPARE_DISABLE		0
+#define CFG_SKIP_SPARE_ENABLE		(1 << 23)
+#define CFG_COM_BSY_MASK		(1 << 22)
+#define CFG_COM_BSY_DISABLE		0
+#define CFG_COM_BSY_ENABLE		(1 << 22)
+#define CFG_BUS_WIDTH_MASK		(1 << 21)
+#define CFG_BUS_WIDTH_8BIT		0
+#define CFG_BUS_WIDTH_16BIT		(1 << 21)
+#define CFG_LPDDR1_MODE_MASK		(1 << 20)
+#define CFG_LPDDR1_MODE_DISABLE		0
+#define CFG_LPDDR1_MODE_ENABLE		(1 << 20)
+#define CFG_EDO_MODE_MASK		(1 << 19)
+#define CFG_EDO_MODE_DISABLE		0
+#define CFG_EDO_MODE_ENABLE		(1 << 19)
+#define CFG_PAGE_SIZE_SEL_MASK		(7 << 16)
+enum {
+	CFG_PAGE_SIZE_256	= 0 << 16,
+	CFG_PAGE_SIZE_512	= 1 << 16,
+	CFG_PAGE_SIZE_1024	= 2 << 16,
+	CFG_PAGE_SIZE_2048	= 3 << 16,
+	CFG_PAGE_SIZE_4096	= 4 << 16
+};
+#define CFG_SKIP_SPARE_SEL_MASK		(3 << 14)
+enum {
+	CFG_SKIP_SPARE_SEL_4	= 0 << 14,
+	CFG_SKIP_SPARE_SEL_8	= 1 << 14,
+	CFG_SKIP_SPARE_SEL_12	= 2 << 14,
+	CFG_SKIP_SPARE_SEL_16	= 3 << 14
+};
+#define CFG_TAG_BYTE_SIZE_MASK	0x1FF
+
+#define TIMING_0			0x14
+#define TIMING_TRP_RESP_CNT_SHIFT	28
+#define TIMING_TRP_RESP_CNT_MASK	(0xf << TIMING_TRP_RESP_CNT_SHIFT)
+#define TIMING_TWB_CNT_SHIFT		24
+#define TIMING_TWB_CNT_MASK		(0xf << TIMING_TWB_CNT_SHIFT)
+#define TIMING_TCR_TAR_TRR_CNT_SHIFT	20
+#define TIMING_TCR_TAR_TRR_CNT_MASK	(0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT)
+#define TIMING_TWHR_CNT_SHIFT		16
+#define TIMING_TWHR_CNT_MASK		(0xf << TIMING_TWHR_CNT_SHIFT)
+#define TIMING_TCS_CNT_SHIFT		14
+#define TIMING_TCS_CNT_MASK		(3 << TIMING_TCS_CNT_SHIFT)
+#define TIMING_TWH_CNT_SHIFT		12
+#define TIMING_TWH_CNT_MASK		(3 << TIMING_TWH_CNT_SHIFT)
+#define TIMING_TWP_CNT_SHIFT		8
+#define TIMING_TWP_CNT_MASK		(0xf << TIMING_TWP_CNT_SHIFT)
+#define TIMING_TRH_CNT_SHIFT		4
+#define TIMING_TRH_CNT_MASK		(3 << TIMING_TRH_CNT_SHIFT)
+#define TIMING_TRP_CNT_SHIFT		0
+#define TIMING_TRP_CNT_MASK		(0xf << TIMING_TRP_CNT_SHIFT)
+
+#define RESP_0				0x18
+
+#define TIMING2_0			0x1C
+#define TIMING2_TADL_CNT_SHIFT		0
+#define TIMING2_TADL_CNT_MASK		(0xf << TIMING2_TADL_CNT_SHIFT)
+
+#define CMD_REG1_0			0x20
+#define CMD_REG2_0			0x24
+#define ADDR_REG1_0			0x28
+#define ADDR_REG2_0			0x2C
+
+#define DMA_MST_CTRL_0			0x30
+#define DMA_MST_CTRL_GO_MASK		(1 << 31)
+#define DMA_MST_CTRL_GO_DISABLE		0
+#define DMA_MST_CTRL_GO_ENABLE		(1 << 31)
+#define DMA_MST_CTRL_DIR_MASK		(1 << 30)
+#define DMA_MST_CTRL_DIR_READ		0
+#define DMA_MST_CTRL_DIR_WRITE		(1 << 30)
+#define DMA_MST_CTRL_PERF_EN_MASK	(1 << 29)
+#define DMA_MST_CTRL_PERF_EN_DISABLE	0
+#define DMA_MST_CTRL_PERF_EN_ENABLE	(1 << 29)
+#define DMA_MST_CTRL_REUSE_BUFFER_MASK	(1 << 27)
+#define DMA_MST_CTRL_REUSE_BUFFER_DISABLE	0
+#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE	(1 << 27)
+#define DMA_MST_CTRL_BURST_SIZE_SHIFT	24
+#define DMA_MST_CTRL_BURST_SIZE_MASK	(7 << DMA_MST_CTRL_BURST_SIZE_SHIFT)
+enum {
+	DMA_MST_CTRL_BURST_1WORDS	= 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
+	DMA_MST_CTRL_BURST_4WORDS	= 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
+	DMA_MST_CTRL_BURST_8WORDS	= 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
+	DMA_MST_CTRL_BURST_16WORDS	= 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT
+};
+#define DMA_MST_CTRL_IS_DMA_DONE	(1 << 20)
+#define DMA_MST_CTRL_EN_A_MASK		(1 << 2)
+#define DMA_MST_CTRL_EN_A_DISABLE	0
+#define DMA_MST_CTRL_EN_A_ENABLE	(1 << 2)
+#define DMA_MST_CTRL_EN_B_MASK		(1 << 1)
+#define DMA_MST_CTRL_EN_B_DISABLE	0
+#define DMA_MST_CTRL_EN_B_ENABLE	(1 << 1)
+
+#define DMA_CFG_A_0			0x34
+#define DMA_CFG_B_0			0x38
+#define FIFO_CTRL_0			0x3C
+#define DATA_BLOCK_PTR_0		0x40
+#define TAG_PTR_0			0x44
+#define ECC_PTR_0			0x48
+
+#define DEC_STATUS_0			0x4C
+#define DEC_STATUS_A_ECC_FAIL		(1 << 1)
+#define DEC_STATUS_B_ECC_FAIL		(1 << 0)
+
+#define BCH_CONFIG_0			0xCC
+#define BCH_CONFIG_BCH_TVALUE_SHIFT	4
+#define BCH_CONFIG_BCH_TVALUE_MASK	(3 << BCH_CONFIG_BCH_TVALUE_SHIFT)
+enum {
+	BCH_CONFIG_BCH_TVAL4	= 0 << BCH_CONFIG_BCH_TVALUE_SHIFT,
+	BCH_CONFIG_BCH_TVAL8	= 1 << BCH_CONFIG_BCH_TVALUE_SHIFT,
+	BCH_CONFIG_BCH_TVAL14	= 2 << BCH_CONFIG_BCH_TVALUE_SHIFT,
+	BCH_CONFIG_BCH_TVAL16	= 3 << BCH_CONFIG_BCH_TVALUE_SHIFT
+};
+#define BCH_CONFIG_BCH_ECC_MASK		(1 << 0)
+#define BCH_CONFIG_BCH_ECC_DISABLE	0
+#define BCH_CONFIG_BCH_ECC_ENABLE	(1 << 0)
+
+#define BCH_DEC_RESULT_0			0xD0
+#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK	(1 << 8)
+#define BCH_DEC_RESULT_PAGE_COUNT_MASK		0xFF
+
+#define BCH_DEC_STATUS_BUF_0			0xD4
+#define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK	0xFF000000
+#define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK	0x00FF0000
+#define BCH_DEC_STATUS_FAIL_TAG_MASK		(1 << 14)
+#define BCH_DEC_STATUS_CORR_TAG_MASK		(1 << 13)
+#define BCH_DEC_STATUS_MAX_CORR_CNT_MASK	(0x1f << 8)
+#define BCH_DEC_STATUS_PAGE_NUMBER_MASK		0xFF
+
+#define LP_OPTIONS (NAND_NO_READRDY | NAND_NO_AUTOINCR)
+
+struct nand_ctlr {
+	u32	command;	/* offset 00h */
+	u32	status;		/* offset 04h */
+	u32	isr;		/* offset 08h */
+	u32	ier;		/* offset 0Ch */
+	u32	config;		/* offset 10h */
+	u32	timing;		/* offset 14h */
+	u32	resp;		/* offset 18h */
+	u32	timing2;	/* offset 1Ch */
+	u32	cmd_reg1;	/* offset 20h */
+	u32	cmd_reg2;	/* offset 24h */
+	u32	addr_reg1;	/* offset 28h */
+	u32	addr_reg2;	/* offset 2Ch */
+	u32	dma_mst_ctrl;	/* offset 30h */
+	u32	dma_cfg_a;	/* offset 34h */
+	u32	dma_cfg_b;	/* offset 38h */
+	u32	fifo_ctrl;	/* offset 3Ch */
+	u32	data_block_ptr;	/* offset 40h */
+	u32	tag_ptr;	/* offset 44h */
+	u32	resv1;		/* offset 48h */
+	u32	dec_status;	/* offset 4Ch */
+	u32	hwstatus_cmd;	/* offset 50h */
+	u32	hwstatus_mask;	/* offset 54h */
+	u32	resv2[29];
+	u32	bch_config;	/* offset CCh */
+	u32	bch_dec_result;	/* offset D0h */
+	u32	bch_dec_status_buf;
+				/* offset D4h */
+};
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index f4523a3..a7cda75 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -56,8 +56,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
 
 	/* calculate spi clock prescaller using max_hz */
-	data = ((CONFIG_SYS_TCLK / 2) / max_hz) & KWSPI_CLKPRESCL_MASK;
-	data |= 0x10;
+	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
+	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
 
 	/* program spi clock prescaller using max_hz */
 	writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 168dbe4..42e4c99 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -224,8 +224,10 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 	struct mxs_dma_desc *dp;
 	uint32_t ctrl0;
 	uint32_t cache_data_count;
+	const uint32_t dstart = (uint32_t)data;
 	int dmach;
 	int tl;
+	int ret = 0;
 
 	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 
@@ -239,17 +241,17 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 	if (!write)
 		ctrl0 |= SSP_CTRL0_READ;
 
-	writel(length, &ssp_regs->hw_ssp_xfer_size);
-
 	if (length % ARCH_DMA_MINALIGN)
 		cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
 	else
 		cache_data_count = length;
 
+	/* Flush data to DRAM so DMA can pick them up */
 	if (write)
-		/* Flush data to DRAM so DMA can pick them up */
-		flush_dcache_range((uint32_t)data,
-			(uint32_t)(data + cache_data_count));
+		flush_dcache_range(dstart, dstart + cache_data_count);
+
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range(dstart, dstart + cache_data_count);
 
 	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
 
@@ -281,41 +283,47 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 			tl = min(length, xfer_max_sz);
 
 		dp->cmd.data |=
-			(tl << MXS_DMA_DESC_BYTES_OFFSET) |
-			(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+			((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
+			(4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 			MXS_DMA_DESC_HALT_ON_TERMINATE |
 			MXS_DMA_DESC_TERMINATE_FLUSH;
-		dp->cmd.pio_words[0] = ctrl0;
 
 		data += tl;
 		length -= tl;
 
+		if (!length) {
+			dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
+
+			if (flags & SPI_XFER_END) {
+				ctrl0 &= ~SSP_CTRL0_LOCK_CS;
+				ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+			}
+		}
+
+		/*
+		 * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
+		 * essential that the XFER_SIZE register is written on
+		 * a per-descriptor basis with the same size as is the
+		 * descriptor!
+		 */
+		dp->cmd.pio_words[0] = ctrl0;
+		dp->cmd.pio_words[1] = 0;
+		dp->cmd.pio_words[2] = 0;
+		dp->cmd.pio_words[3] = tl;
+
 		mxs_dma_desc_append(dmach, dp);
 
 		dp++;
 	}
 
-	dp->address = (dma_addr_t)dp;
-	dp->cmd.address = (dma_addr_t)0;
-	dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER |
-			(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
-			MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
-	if (flags & SPI_XFER_END) {
-		ctrl0 &= ~SSP_CTRL0_LOCK_CS;
-		dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
-	}
-	mxs_dma_desc_append(dmach, dp);
-
 	if (mxs_dma_go(dmach))
-		return -EINVAL;
+		ret = -EINVAL;
 
 	/* The data arrived into DRAM, invalidate cache over them */
-	if (!write) {
-		invalidate_dcache_range((uint32_t)data,
-			(uint32_t)(data + cache_data_count));
-	}
+	if (!write)
+		invalidate_dcache_range(dstart, dstart + cache_data_count);
 
-	return 0;
+	return ret;
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
index 2355e02..18b00b2 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra_spi.c
@@ -72,9 +72,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		return NULL;
 	}
 
-	if (max_hz > TEGRA20_SPI_MAX_FREQ) {
+	if (max_hz > TEGRA_SPI_MAX_FREQ) {
 		printf("SPI error: unsupported frequency %d Hz. Max frequency"
-			" is %d Hz\n", max_hz, TEGRA20_SPI_MAX_FREQ);
+			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
 		return NULL;
 	}
 
@@ -86,7 +86,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	spi->slave.bus = bus;
 	spi->slave.cs = cs;
 	spi->freq = max_hz;
-	spi->regs = (struct spi_tegra *)TEGRA20_SPI_BASE;
+	spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
 	spi->mode = mode;
 
 	return &spi->slave;
diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
index 6686718..b1424bf 100644
--- a/drivers/video/omap3_dss.c
+++ b/drivers/video/omap3_dss.c
@@ -112,7 +112,7 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg)
 	writel(panel_cfg->pol_freq, &dispc->pol_freq);
 	writel(panel_cfg->divisor, &dispc->divisor);
 	writel(panel_cfg->lcd_size, &dispc->size_lcd);
-	writel(panel_cfg->load_mode << FRAME_MODE_SHIFT, &dispc->config);
+	writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
 	writel(panel_cfg->panel_type << TFTSTN_SHIFT |
 		panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
 	writel(panel_cfg->panel_color, &dispc->default_color0);
@@ -121,7 +121,6 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg)
 	if (!panel_cfg->frame_buffer)
 		return;
 
-	writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
 	writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes);
 	writel(1, &dispc->gfx_row_inc);
 	writel(1, &dispc->gfx_pixel_inc);
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index d4104de..9371ec3 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -44,7 +44,12 @@
 #define MACH_TYPE_EB_CPUX9K2		1977
 #define CONFIG_MACH_TYPE		MACH_TYPE_EB_CPUX9K2
 /*--------------------------------------------------------------------------*/
-#define CONFIG_SYS_TEXT_BASE 		0x00000000
+#ifndef CONFIG_RAMBOOT
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0x21f00000
+#endif
 #define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
 #define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index f0fb488..f2cfaf8 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -69,13 +69,18 @@
  * - GPIO16 is Power LED control (0 = on, 1 = off)
  * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
  * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- * - Last GPIO is 26, further bits are supposed to be 0.
+ * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
+ * - GPIO22 is SATA disk power status ()
+ * - GPIO23 is supply status for SATA disk ()
+ * - GPIO24 is supply control for board (write 1 to power off)
+ * Last GPIO is 25, further bits are supposed to be 0.
  * Enable mask has ones for INPUT, 0 for OUTPUT.
- * Default is LED ON.
+ * Default is LED ON, board ON :)
  */
 
-#define ORION5X_GPIO_OUT_ENABLE	0x03fcffff
-#define ORION5X_GPIO_OUT_VALUE	0x03fcffff
+#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
+#define ORION5X_GPIO_OUT_VALUE		0x00000000
+#define ORION5X_GPIO_IN_POLARITY	0x000000d0
 
 /*
  * NS16550 Configuration
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 027a5dc..46171b9 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -31,7 +31,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136	/* This is an arm1136 CPU core */
 #define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ	24000000
 
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE	32
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d0555c1..e407ff4 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -34,15 +34,15 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Harmony) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Harmony"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 
 /* UARTD: keyboard satellite board UART, default */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
 /* UARTA: debug board UART */
 #define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
 #endif
@@ -62,8 +62,15 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE	NV_PA_NAND_BASE
+
+/* Environment in NAND (which is 512M), aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(SZ_512M - SZ_128K) /* 128K sector size */
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
@@ -80,6 +87,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index 567061a..dbc59b9 100644
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -64,7 +64,6 @@
 /* Ethernet on FEC */
 #define CONFIG_NET_MULTI
 #define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
 
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE			FEC_BASE_ADDR
@@ -72,7 +71,7 @@
 #define CONFIG_PHY_ADDR			CONFIG_FEC_MXC_PHYADDR
 #define CONFIG_RESET_PHY_R
 #define CONFIG_FEC_MXC_NO_ANEG
-#define CONFIG_PRIME	"FEC0"
+#define CONFIG_ETHPRIME			"FEC0"
 
 /* SPI */
 #define CONFIG_HARD_SPI
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 8cca478..6ae764a 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -33,7 +33,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
 #define CONFIG_MX31		1    /* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
 
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index b21621c..f36ceea 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -33,7 +33,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
 
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
new file mode 100644
index 0000000..564b418
--- /dev/null
+++ b/include/configs/integrator-common.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2012
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Common ARM Integrator configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define CONFIG_INTEGRATOR
+
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0	/* default load address */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R		/* call misc_init_r during start up */
+
+/*
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ */
+#include "armcoremodule.h"
+
+/*
+ * Initialize and remap the core module, use SPD to detect memory size
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+ */
+#define CONFIG_CM_INIT
+#define CONFIG_CM_REMAP
+#define CONFIG_CM_SPD_DETECT
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+ */
+/* #define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+ */
+/* #define SKIP_CONFIG_RELOCATE_UBOOT */
+
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+				    CONFIG_SYS_INIT_RAM_SIZE - \
+				    GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 2770c82..c6907b5 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -31,32 +31,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_INTEGRATOR
+#include "integrator-common.h"
+
+/* Integrator/AP-specific configuration */
 #define CONFIG_ARCH_INTEGRATOR
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_TEXT_BASE		0x01000000
-#define CONFIG_SYS_MEMTEST_START	0x100000
-#define CONFIG_SYS_MEMTEST_END		0x10000000
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
-#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1		       */
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_CM_INIT		1
-#define CONFIG_CM_REMAP		1
-#define CONFIG_CM_SPD_DETECT
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
 
 /*
  * PL010 Configuration
@@ -90,29 +69,7 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP	/* undef to save memory	    */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
-				    CONFIG_SYS_INIT_RAM_SIZE - \
-				    GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_FLASH_BASE	0x24000000
 
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index d5043df..ca02a6f 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -31,32 +31,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Integrator-specific configuration */
-#define CONFIG_INTEGRATOR
-#define CONFIG_ARCH_CINTEGRATOR
-#define CONFIG_CM_INIT
-#define CONFIG_CM_REMAP
-#define CONFIG_CM_SPD_DETECT
+#include "integrator-common.h"
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_TEXT_BASE		0x01000000
-#define CONFIG_SYS_MEMTEST_START	0x100000
-#define CONFIG_SYS_MEMTEST_END		0x10000000
-#define CONFIG_SYS_HZ			1000
+/* Integrator CP-specific configuration */
+#define CONFIG_ARCH_CINTEGRATOR
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
-#define CONFIG_SYS_TIMERBASE		0x13000100
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
 /*
  * Hardware drivers
@@ -66,9 +45,7 @@
 #define CONFIG_SMC91111_BASE    0xC8000000
 #undef CONFIG_SMC91111_EXT_PHY
 
-/*
- * NS16550 Configuration
- */
+/* PL011 configuration */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK	14745600
 #define CONFIG_PL01x_PORTS	{ (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
@@ -77,16 +54,6 @@
 #define CONFIG_SYS_SERIAL0		0x16000000
 #define CONFIG_SYS_SERIAL1		0x17000000
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
  * Command line configuration.
  */
@@ -102,32 +69,10 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory */
 #define CONFIG_SYS_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size*/
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16			/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE		/* Boot Argument Buffer Size*/
 
-#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
-				    CONFIG_SYS_INIT_RAM_SIZE - \
-				    GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
+/*
  * FLASH and environment organization
-
  * Top varies according to amount fitted
  * Reserve top 4 blocks of flash
  * - ARM Boot Monitor
@@ -136,7 +81,6 @@
  * - U-Boot environment
  *
  * Base is always 0x24000000
-
  */
 #define CONFIG_SYS_FLASH_BASE		0x24000000
 #define CONFIG_SYS_FLASH_CFI		1
@@ -178,53 +122,4 @@
 #define CONFIG_ENV_SECT_SIZE	0x40000		/* 256KB */
 #define CONFIG_ENV_SIZE		8192		/* 8KB */
 
-/*
- * The ARM boot monitor initializes the board.
- * However, the default U-Boot code also performs the initialization.
- * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
- * - see documentation supplied with board for details of how to choose the
- * image to run at reset/power up
- * e.g. whether the ARM Boot Monitor runs before U-Boot
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
- */
-
-/*
- * The ARM boot monitor does not relocate U-Boot.
- * However, the default U-Boot code performs the relocation check,
- * and may relocate the code if the memory map is changed.
- * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
-
-#define SKIP_CONFIG_RELOCATE_UBOOT
-
- */
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. cp_926ejs_config
- */
-
-#include "armcoremodule.h"
-
-/*
- * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
- * the core module has a CM_INIT register
- * then the U-Boot initialisation code will
- * e.g. ARM Boot Monitor or pre-loader is repeated once
- * (to re-initialise any existing CM_INIT settings to safe values).
- *
- * This is usually not the desired behaviour since the platform
- * will either reboot into the ARM monitor (or pre-loader)
- * or continuously cycle thru it without U-Boot running,
- * depending upon the setting of Integrator/CP switch S2-4.
- *
- * However it may be needed if Integrator/CP switch S2-1
- * is set OFF to boot direct into U-Boot.
- * In that case comment out the line below.
-#undef	CONFIG_CM_INIT
- */
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 7ed9958..9983104 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -81,7 +81,6 @@
 
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
-#define CONFIG_SYS_BOARD_DRAM_INIT	/* Used board specific dram_init */
 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_MAX_I2C_BUS		1
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 27b77d3..44d5373 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -57,10 +57,14 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C		/* I2C bit-banged	*/
 
+/* SPI NOR Flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		8100000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		0
-#define CONFIG_ENV_SPI_MAX_HZ		5000000
+#define CONFIG_ENV_SPI_MAX_HZ		8100000
 #define CONFIG_ENV_SPI_MODE		SPI_MODE_3
 #endif
 
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index d0f2b48..9eb2a54 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -171,9 +171,9 @@
 #define	CONFIG_LZO
 #define	CONFIG_MTD_DEVICE
 #define	CONFIG_MTD_PARTITIONS
-#define	MTDIDS_DEFAULT			"nand0=gpmi-nand.0"
+#define	MTDIDS_DEFAULT			"nand0=gpmi-nand"
 #define	MTDPARTS_DEFAULT			\
-	"mtdparts=gpmi-nand.0:"			\
+	"mtdparts=gpmi-nand:"			\
 		"3m(bootloader)ro,"		\
 		"512k(environment),"		\
 		"512k(redundant-environment),"	\
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index bce03a4..678b36b 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -35,11 +35,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Medcom) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Avionic Design Medcom"
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Medcom"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -78,6 +78,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index 5db6d57..8d35943 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -2,6 +2,9 @@
  * Copyright (C) 2011
  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  *
+ *
+ * Configuration settings for the Teejet mt_ventoux board.
+ *
  * Copyright (C) 2009 TechNexion Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -24,6 +27,10 @@
 
 #include "tam3517-common.h"
 
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
+					6 * 1024 * 1024)
+
 #define MACH_TYPE_AM3517_MT_VENTOUX	3832
 #define CONFIG_MACH_TYPE	MACH_TYPE_AM3517_MT_VENTOUX
 
@@ -31,6 +38,7 @@
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_AUTO_COMPLETE
 
+#define CONFIG_OMAP3_GPIO_4
 #define CONFIG_HOSTNAME mt_ventoux
 
 /*
@@ -62,6 +70,15 @@
 #define CONFIG_FPGA_DELAY() udelay(1)
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
 #define	CONFIG_EXTRA_ENV_SETTINGS	CONFIG_TAM3517_SETTINGS \
 	"bootcmd=run net_nfs\0"
 
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 359a308..96c143e 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -17,7 +17,6 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_MX25_CLK32		32768	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x81200000
 
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 4e1e6bc..dffb744 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -184,6 +184,9 @@
 #define	CONFIG_EHCI_MXS_PORT 1
 #define	CONFIG_EHCI_IS_TDI
 #define	CONFIG_USB_STORAGE
+#define	CONFIG_USB_HOST_ETHER
+#define	CONFIG_USB_ETHER_ASIX
+#define	CONFIG_USB_ETHER_SMSC95XX
 #endif
 
 /* I2C */
@@ -199,6 +202,7 @@
 #ifdef CONFIG_CMD_SPI
 #define CONFIG_HARD_SPI
 #define CONFIG_MXS_SPI
+#define CONFIG_MXS_SPI_DMA_ENABLE
 #define CONFIG_SPI_HALF_DUPLEX
 #define CONFIG_DEFAULT_SPI_BUS		2
 #define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
@@ -235,7 +239,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE	"uImage"
-#define CONFIG_BOOTCOMMAND	"run bootcmd_net"
 #define CONFIG_LOADADDR	0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 #define CONFIG_OF_LIBFDT
@@ -244,13 +247,80 @@
  * Extra Environments
  */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"console_fsl=console=ttyAM0" \
-	"console_mainline=console=ttyAMA0" \
-	"netargs=setenv bootargs console=${console_mainline}" \
+	"update_nand_full_filename=u-boot.nand\0" \
+	"update_nand_firmware_filename=u-boot.sb\0"	\
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_nand_firmware_maxsz=0x100000\0"	\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */ \
+		"nand device 0 ; " \
+		"nand info ; " \
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_full="		    /* Update FCB, DBBT and FW */ \
+		"if tftp ${update_nand_full_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"nand scrub -y 0x0 ${filesize} ; " \
+		"nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0" \
+	"update_nand_firmware="		/* Update only firmware */ \
+		"if tftp ${update_nand_firmware_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; " \
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+		"fi\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console_fsl=ttyAM0\0" \
+	"console_mainline=ttyAMA0\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0"	\
+	"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0"	\
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; "	\
+		"bootm\0" \
+	"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
 		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
-	"bootcmd_net=echo Booting from net ...; " \
-		"run netargs; " \
-		"dhcp ${uimage}; bootm\0" \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; "	\
+		"dhcp ${uimage}; bootm\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
 
 #endif /* __MX28EVK_CONFIG_H__ */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 081fbf6..9d9f4a7 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -27,8 +27,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
 #define CONFIG_MX31		1		/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 17d3143..b272674 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -35,8 +35,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 5816152..69bd654 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -31,7 +31,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136	/* This is an arm1136 CPU core */
 #define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ	24000000
 
 #define CONFIG_DISPLAY_CPUINFO
 
@@ -111,6 +110,12 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
 #define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
@@ -237,6 +242,13 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
 /*
  * Default environment and default scripts
  * to update uboot and load kernel
@@ -278,8 +290,8 @@
 	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
 	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"		\
-	"update=protect off ${uboot_addr} +40000;"			\
-		"erase ${uboot_addr} +40000;"				\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
 		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
 	"upd=if run load;then echo Updating u-boot;if run update;"	\
 		"then echo U-Boot updated;"				\
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 99b8753..24cda48 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -27,11 +27,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Paz00) MOD # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Compal Paz00"
+#define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
+#define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
@@ -69,6 +69,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 42291d4..65b42ed 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -35,11 +35,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Plutux) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Avionic Design Plutux"
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Plutux"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -78,6 +78,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/qong.h b/include/configs/qong.h
index 485e1b1..c2bd097 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -28,8 +28,6 @@
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
 #define CONFIG_QONG
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 0ebdfb8..f5dc393 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -39,8 +39,6 @@
 #include <asm/arch/regs-base.h>
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_ARCH_MISC_INIT
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 8dc6d4b..de19e38 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -27,7 +27,7 @@
 #include <asm/sizes.h>
 
 /* LP0 suspend / resume */
-#define CONFIG_TEGRA20_LP0
+#define CONFIG_TEGRA_LP0
 #define CONFIG_AES
 #define CONFIG_TEGRA_PMU
 #define CONFIG_TPS6586X_POWER
@@ -42,11 +42,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (SeaBoard) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Seaboard"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
@@ -96,14 +96,23 @@
 #define CONFIG_CMD_DHCP
 
 /* Enable keyboard */
-#define CONFIG_TEGRA20_KEYBOARD
+#define CONFIG_TEGRA_KEYBOARD
 #define CONFIG_KEYBOARD
 
-#undef TEGRA20_DEVICE_SETTINGS
-#define TEGRA20_DEVICE_SETTINGS	"stdin=serial,tegra-kbc\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#undef TEGRA_DEVICE_SETTINGS
+#define TEGRA_DEVICE_SETTINGS	"stdin=serial,tegra-kbc\0" \
+				"stdout=serial\0" \
+				"stderr=serial\0"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Somewhat oddly, the NAND base address must be a config option */
+#define CONFIG_SYS_NAND_BASE	NV_PA_NAND_BASE
 #endif /* __CONFIG_H */
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index a2a0156..a881eef 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -59,6 +59,7 @@
 #define CONFIG_INITRD_TAG		/* pass initrd param to kernel */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_BOARD_EARLY_INIT_f	/* call board_early_init_f() */
+#define CONFIG_BOARD_POSTCLK_INIT	/* call board_postclk_init() */
 #define CONFIG_DISPLAY_CPUINFO		/* display CPU Info at startup */
 
 /* setting board specific options */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 375265d..a13fd93 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -124,6 +124,7 @@
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_EEPROM
 
 #undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
 #undef CONFIG_CMD_IMLS
@@ -134,6 +135,9 @@
 #define CONFIG_SYS_I2C_SLAVE		1
 #define CONFIG_SYS_I2C_BUS		0
 #define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CONFIG_DRIVER_OMAP34XX_I2C
 
 
@@ -347,4 +351,66 @@
 		"fi;"							\
 		"else echo U-Boot not downloaded..exiting;fi\0"		\
 
+
+/*
+ * this is common code for all TAM3517 boards.
+ * MAC address is stored from manufacturer in
+ * I2C EEPROM
+ */
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+
+/*
+ * The I2C EEPROM on the TAM3517 contains
+ * mac address and production data
+ */
+struct tam3517_module_info {
+	char customer[48];
+	char product[48];
+
+	/*
+	 * bit 0~47  : sequence number
+	 * bit 48~55 : week of year, from 0.
+	 * bit 56~63 : year
+	 */
+	unsigned long long sequence_number;
+
+	/*
+	 * bit 0~7   : revision fixed
+	 * bit 8~15  : revision major
+	 * bit 16~31 : TNxxx
+	 */
+	unsigned int revision;
+	unsigned char eth_addr[4][8];
+	unsigned char _rev[100];
+};
+
+#define TAM3517_READ_MAC_FROM_EEPROM	\
+do {					\
+	struct tam3517_module_info info;\
+	char buf[80], ethname[20];	\
+	int i;				\
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);	\
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
+			(void *)&info, sizeof(info)))		\
+		break;						\
+	memset(buf, 0, sizeof(buf));				\
+	for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) {	\
+		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
+			info.eth_addr[i][5],			\
+			info.eth_addr[i][4],			\
+			info.eth_addr[i][3],			\
+			info.eth_addr[i][2],			\
+			info.eth_addr[i][1],			\
+			info.eth_addr[i][0]);			\
+								\
+		if (i)						\
+			sprintf(ethname, "eth%daddr", i);	\
+		else						\
+			sprintf(ethname, "ethaddr");		\
+		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
+		setenv(ethname, buf);				\
+	}							\
+} while (0)
+#endif
+
 #endif /* __TAM3517_H */
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 9b3f88d..d5da3c7 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -35,24 +35,32 @@
 
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (TEC) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
 #define CONFIG_SYS_BOARD_ODMDATA	0x2b0d8011
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CONFIG_ENV_IS_NOWHERE
-
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NV_PA_NAND_BASE
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
@@ -79,6 +87,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra20-common-post.h b/include/configs/tegra-common-post.h
index 42f270f..168b64b 100644
--- a/include/configs/tegra20-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -21,8 +21,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __TEGRA20_COMMON_POST_H
-#define __TEGRA20_COMMON_POST_H
+#ifndef __TEGRA_COMMON_POST_H
+#define __TEGRA_COMMON_POST_H
 
 #ifdef CONFIG_BOOTCOMMAND
 
@@ -141,7 +141,7 @@
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	TEGRA20_DEVICE_SETTINGS \
+	TEGRA_DEVICE_SETTINGS \
 	"fdt_load=0x01000000\0" \
 	"fdt_high=01100000\0" \
 	BOOTCMDS_COMMON
@@ -174,8 +174,8 @@
 #ifdef CONFIG_GENERIC_MMC
 #undef CONFIG_GENERIC_MMC
 #endif
-#ifdef CONFIG_TEGRA20_MMC
-#undef CONFIG_TEGRA20_MMC
+#ifdef CONFIG_TEGRA_MMC
+#undef CONFIG_TEGRA_MMC
 #endif
 #ifdef CONFIG_CMD_MMC
 #undef CONFIG_CMD_MMC
@@ -211,4 +211,4 @@
 
 #endif /* CONFIG_SPL_BUILD */
 
-#endif /* __TEGRA20_COMMON_POST_H */
+#endif /* __TEGRA_COMMON_POST_H */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 4c02f20..098cdb4 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -54,7 +54,7 @@
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR			0x1C406000
 #define TEGRA_LP0_SIZE			0x2000
 #define TEGRA_LP0_VEC \
@@ -132,9 +132,9 @@
 /* Environment information, boards can override if required */
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define TEGRA20_DEVICE_SETTINGS	"stdin=serial\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#define TEGRA_DEVICE_SETTINGS	"stdin=serial\0" \
+				"stdout=serial\0" \
+				"stderr=serial\0"
 
 #define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
 #define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
@@ -157,7 +157,7 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START	(TEGRA20_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
 
 #define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
@@ -169,7 +169,7 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		TEGRA20_SDRC_CS0
+#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
 
 #define CONFIG_SYS_TEXT_BASE	0x0010c000
@@ -201,4 +201,6 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
 
+#define CONFIG_SYS_NAND_SELF_INIT
+
 #endif /* __TEGRA20_COMMON_H */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index b3c5249..a46890c 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -34,12 +34,12 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (TrimSlice) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Compulab Trimslice"
+#define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_GPU
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_GPU
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_TRIMSLICE
@@ -94,6 +94,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index cc68a42..f46efa5 100644
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -31,8 +31,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136
 #define CONFIG_MX31
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index f5e1bf8..7d3a54f 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -34,11 +34,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Ventana) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Ventana"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
@@ -76,6 +76,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 3235718..6c565ba 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -34,12 +34,12 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Whistler) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Whistler"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Whistler"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_UAA_UAB
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_UAA_UAB
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_WHISTLER
@@ -90,6 +90,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 072945a..447683a 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -28,7 +28,6 @@
 
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_MX25
-#define CONFIG_MX25_CLK32		32768	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0xA0000000
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a8f783f..474a4b9 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -63,6 +63,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
 	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
 	COMPAT_NVIDIA_TEGRA20_KBC,	/* Tegra20 Keyboard */
+	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 
 	COMPAT_COUNT,
 };
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index c06866b..f63e04b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -390,9 +390,10 @@ struct nand_ecc_ctrl {
  * consecutive order.
  */
 struct nand_buffers {
-	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
-	uint8_t	ecccode[NAND_MAX_OOBSIZE];
-	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];
 };
 
 /**
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index af17ac1..69c63db 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -42,6 +42,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
 	COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
 	COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
+	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)