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| author | Anton Staaf <robotboy@chromium.org> | 2011-10-17 16:46:07 -0700 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-23 20:50:42 +0200 |
| commit | 2482e3c836a9342a6aa1a9885331aa60dbd1f8f8 (patch) | |
| tree | 8267fd9aa99ee1aa61c4d1f02559deec78fcb02b | |
| parent | 0991701a27e7f1de983ff2250dbdb88a7c8c60ec (diff) | |
| download | u-boot-imx-2482e3c836a9342a6aa1a9885331aa60dbd1f8f8.zip u-boot-imx-2482e3c836a9342a6aa1a9885331aa60dbd1f8f8.tar.gz u-boot-imx-2482e3c836a9342a6aa1a9885331aa60dbd1f8f8.tar.bz2 | |
sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| -rw-r--r-- | arch/sh/include/asm/cache.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index 2cfc0a7..6ffab4d 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -6,6 +6,7 @@ int cache_control(unsigned int cmd); #define L1_CACHE_BYTES 32 + struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct *)(x)) @@ -30,6 +31,22 @@ void dcache_invalid_range(u32 start, u32 end) : "m" (__m(v))); } } +#else + +/* + * 32-bytes is the largest L1 data cache line size for SH the architecture. So + * it is a safe default for DMA alignment. + */ +#define ARCH_DMA_MINALIGN 32 + #endif /* CONFIG_SH4 || CONFIG_SH4A */ +/* + * Use the L1 data cache line size value for the minimum DMA buffer alignment + * on SH. + */ +#ifndef ARCH_DMA_MINALIGN +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#endif + #endif /* __ASM_SH_CACHE_H */ |