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authorYe.Li <B37916@freescale.com>2014-03-03 18:16:52 +0800
committerYe.Li <B37916@freescale.com>2014-03-05 16:53:44 +0800
commite2d49dc289a2c00a01d29f7d3eb044c00e504fe2 (patch)
tree81623b2f117d09bd245f7d20e0751d2c9a687d9a
parentd4db9bf2bf818d9af42685d9a952903e6932c1ad (diff)
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ENGR00301683 FEC: Modify enet driver TX polling bit
Change to check READY bit in BD, not check the TDAR. On iMX6SX, FEC will clear the TDAR prior than the READY bit of last BD. Since fec driver only prepare two BD for transmit, this cause the BD send failed at the third packet. On iMX6SX, we disabled DCACHE to workaround for this issue. Now change to enable the DCACHE. Signed-off-by: Ye.Li <B37916@freescale.com>
-rw-r--r--drivers/net/fec_mxc.c7
-rwxr-xr-xinclude/configs/mx6sx_arm2.h1
2 files changed, 2 insertions, 6 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 5b0172b..6c07084 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -758,17 +758,14 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
* barrier here.
*/
while (--timeout) {
- if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
+ invalidate_dcache_range(addr, addr + size);
+ if (!(readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY))
break;
}
if (!timeout)
ret = -EINVAL;
- invalidate_dcache_range(addr, addr + size);
- if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
- ret = -EINVAL;
-
debug("fec_send: status 0x%x index %d ret %i\n",
readw(&fec->tbd_base[fec->tbd_index].status),
fec->tbd_index, ret);
diff --git a/include/configs/mx6sx_arm2.h b/include/configs/mx6sx_arm2.h
index 2d8b33c..0e078d3 100755
--- a/include/configs/mx6sx_arm2.h
+++ b/include/configs/mx6sx_arm2.h
@@ -300,7 +300,6 @@
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
-#define CONFIG_SYS_DCACHE_OFF
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif