diff options
| author | Loren HUANG <b02279@freescale.com> | 2014-04-01 16:58:56 +0800 |
|---|---|---|
| committer | Loren HUANG <b02279@freescale.com> | 2014-04-01 17:04:54 +0800 |
| commit | d503c8268ff7bebddcc6d8041d404f2a5be38591 (patch) | |
| tree | baedcbbb49ded0e6dc1b680ca7418338d3ed3a90 | |
| parent | 3bae8eff74ec58df00b4b0f4fad681bc80f7f0c1 (diff) | |
| download | u-boot-imx-d503c8268ff7bebddcc6d8041d404f2a5be38591.zip u-boot-imx-d503c8268ff7bebddcc6d8041d404f2a5be38591.tar.gz u-boot-imx-d503c8268ff7bebddcc6d8041d404f2a5be38591.tar.bz2 | |
ENGR00306443 [MX6SX] Update the gc400t QoS value
Per SoC team recommandation, update the gc400t QoS value to write 2 and Read 8. It can improve gpu performance in most case.
3d fill: 165->172Mpixel/s
2d fill: 190->228Mpixel/s
Signed-off-by: Loren HUANG <b02279@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 528ed79..3608655 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -415,6 +415,15 @@ int arch_cpu_init(void) mxs_dma_init(); #endif +#ifdef CONFIG_MX6SX + /* Update the gpu QoS to Write 2, Read 8 */ + writel(0, QOSC_BASE_ADDR); /* Disable clkgate & soft_rst */ + writel(0, QOSC_BASE_ADDR+0x60); /* Enable all masters */ + writel(0, QOSC_BASE_ADDR+0x1400); /* Disable clkgate & soft_rst for gpu */ + writel(0x0f000222, QOSC_BASE_ADDR+0x14d0); /* Set Write QoS 2 */ + writel(0x0f020822, QOSC_BASE_ADDR+0x14e0); /* Set Read QoS 8 */ +#endif + return 0; } |