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| author | Nitin Garg <nitin.garg@freescale.com> | 2014-04-01 22:21:18 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-02 19:43:06 -0500 |
| commit | ca231b75f227dbbc364af871f37242db4739eac0 (patch) | |
| tree | b3134cec45f7046f8703239b790bd1ae53ab6244 | |
| parent | ff019a8c415296b9dad340a98f7bfead98404935 (diff) | |
| download | u-boot-imx-ca231b75f227dbbc364af871f37242db4739eac0.zip u-boot-imx-ca231b75f227dbbc364af871f37242db4739eac0.tar.gz u-boot-imx-ca231b75f227dbbc364af871f37242db4739eac0.tar.bz2 | |
ENGR00306276-2: ARM: Add workaround for Cortex-A9 errata 761320
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| -rw-r--r-- | README | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 5 |
2 files changed, 6 insertions, 0 deletions
@@ -490,6 +490,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 38b6021..ea85bf8 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -332,6 +332,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) |