ENGR00302525 QuadSPI: Update QSPI clock API to support two QSPI controllers

Modify the QSPI clock enablement with a parameter of QPSI ID. Update
the BSP of MX6SX 17x17 ARM2, 19x19 ARM2 and SabreSD to adapt the
change.

Signed-off-by: Ye.Li <B37916@freescale.com>

5 files changed, 39 insertions, 19 deletions

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 026174a..03db98b 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -412,27 +412,47 @@ int enable_fec_clock(int fec_id)
 
 
 #ifdef CONFIG_MX6SX
-void enable_qspi_clk(void)
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
 {
     u32 reg = 0;
 
     /* Enable QuadSPI clock */
-    reg = readl(&imx_ccm->CCGR4);
-    reg |= MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET;
-    writel(reg, &imx_ccm->CCGR4);
-
-    /* set 50M  : (50 = 396 / 2 / 4) */
-    reg = readl(&imx_ccm->cs2cdr);
-    reg &= ~(0xfff << 15);
-    reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
-    reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
-			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
-    writel(reg, &imx_ccm->cs2cdr);
+	switch (qspi_num) {
+	case 0:
+		reg = readl(&imx_ccm->CCGR3);
+	    reg |= MXC_CCM_CCGR3_QSPI1_OFFSET;
+	    writel(reg, &imx_ccm->CCGR3);
+
+		/* set 50M  : (50 = 396 / 2 / 4) */
+	    reg = readl(&imx_ccm->cscmr1);
+	    reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+			MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+	    reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+				(2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+	    writel(reg, &imx_ccm->cscmr1);
+		break;
+	case 1:
+	    reg = readl(&imx_ccm->CCGR4);
+	    reg |= MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET;
+	    writel(reg, &imx_ccm->CCGR4);
+
+	    /* set 50M  : (50 = 396 / 2 / 4) */
+	    reg = readl(&imx_ccm->cs2cdr);
+	    reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+				MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+				MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+	    reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+				MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+	    writel(reg, &imx_ccm->cs2cdr);
+		break;
+	default:
+		break;
+
+	}
 }
 #else
-void enable_qspi_clk(void) {}
+void enable_qspi_clk(int qspi_num) {}
 #endif
 
 static u32 get_usdhc_clk(u32 port)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 941ff14..15cdebb 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -69,5 +69,5 @@ int enable_fec_clock(int fec_id);
 int fec_set_rate(int fec_id, unsigned long rate);
 void enable_fec_25m_clock(void);
 void enable_ipu_clock(void);
-void enable_qspi_clk(void);
+void enable_qspi_clk(int qspi_num);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
index a0c248b..069f5c9 100644
--- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
+++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
@@ -196,7 +196,7 @@ int board_qspi_init(void)
 	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
 
 	/* Set the clock */
-	enable_qspi_clk();
+	enable_qspi_clk(1);
 
 	return 0;
 }
diff --git a/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c b/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c
index 932a69f..76f3948 100755
--- a/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c
+++ b/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c
@@ -162,7 +162,7 @@ int board_qspi_init(void)
 	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
 
 	/* Set the clock */
-	enable_qspi_clk();
+	enable_qspi_clk(1);
 
 	return 0;
 }
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 7d12d9b..299dee5 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -230,7 +230,7 @@ int board_qspi_init(void)
 	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
 
 	/* Set the clock */
-	enable_qspi_clk();
+	enable_qspi_clk(1);
 
 	return 0;
 }