ENGR00301803 qspi: fix build issue

1. remove unnecessary code to fix compile warning
2. enable_qspi_clk should be designed for mx6sx only.

Signed-off-by: Allen Xu <b45815@freescale.com>

2 files changed, 19 insertions, 20 deletions

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 89a0ef4..2feb61f 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -325,7 +325,25 @@ int enable_fec_clock(void)
 
 	return 0;
 }
+#else
+static u32 get_mmdc_ch0_clk(void)
+{
+	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+	return get_periph_clk() / (mmdc_ch0_podf + 1);
+}
+
+int enable_fec_clock(void)
+{
+	return 0;
+}
+
+#endif
 
+
+#ifdef CONFIG_MX6SX
 void enable_qspi_clk(void)
 {
     u32 reg = 0;
@@ -345,22 +363,7 @@ void enable_qspi_clk(void)
 			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
     writel(reg, &imx_ccm->cs2cdr);
 }
-
 #else
-static u32 get_mmdc_ch0_clk(void)
-{
-	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-	return get_periph_clk() / (mmdc_ch0_podf + 1);
-}
-
-int enable_fec_clock(void)
-{
-	return 0;
-}
-
 void enable_qspi_clk(void) {}
 #endif
 
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index d8673d4..a8901f3 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -713,7 +713,7 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
 static void fsl_qspi_read(struct fsl_qspi *q, unsigned int addr, int len, u8 *rxbuf)
 {
 	/* Read out the data directly from the AHB buffer.*/
-	memcpy(rxbuf, q->memmap_phy + q->chip_base_addr + addr, len);
+	memcpy(rxbuf, (u8 *)(q->memmap_phy + q->chip_base_addr + addr), len);
 }
 
 /* Read out the data from the QUADSPI_RBDR buffer registers. */
@@ -721,12 +721,8 @@ static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
 {
 	u32 tmp;
 	int i = 0;
-	u32 seqid;
 	struct previous_cmd *pcmd = &pre_cmd;
 
-	seqid = (readl(q->iobase + QUADSPI_IPCR) >> QUADSPI_IPCR_SEQID_SHIFT
-			& 0xF);
-
 	if (OPCODE_DDR_QUAD_READ == pcmd->cmd) {
 		fsl_qspi_read(q, pcmd->addr, len, rxbuf);
 		return;