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authorLiu Ying <Ying.Liu@freescale.com>2013-11-22 16:41:14 +0800
committerLiu Ying <Ying.Liu@freescale.com>2013-11-22 17:16:09 +0800
commit588849e191577d87596e28c21e0c80f911eb4990 (patch)
tree230e2e631cf563d7c873701db25fd3aee5e241b5
parentd97c525d98261ea3e83e5fbc30a7225b72dbe8a9 (diff)
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ENGR00288995 MX6 SabreSD: Correct IPU DI pix fmt for LDB
The DC mapping for LVDS666 is different from that for RGB666. Currently, we set IPU DI pixel format to be LVDS666 and set LDB data width to be 24bit. This happens to make the display work normally somehow. But, the two configurations are wrong and don't match with each other. This patch corrects the IPU DI output pixel format from LVDS666 to RGB666 and LDB data width from 24bit to 18bit. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
-rw-r--r--board/freescale/mx6qsabresd/mx6qsabresd.c17
1 files changed, 4 insertions, 13 deletions
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 1e198aa..cc36fb1 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -847,22 +847,12 @@ static void do_enable_hdmi(struct display_info_t const *dev)
imx_enable_hdmi_phy();
}
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
- IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
- writel(reg, &iomux->gpr[2]);
-}
-
static struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
- .pixfmt = IPU_PIX_FMT_LVDS666,
+ .pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
- .enable = enable_lvds,
+ .enable = NULL,
.mode = {
.name = "Hannstar-XGA",
.refresh = 60,
@@ -928,7 +918,8 @@ int board_video_skip(void)
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
- displays[i].enable(displays+i);
+ if (displays[i].enable)
+ displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,