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| author | Ye.Li <B37916@freescale.com> | 2014-02-26 17:04:25 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-03-05 16:09:14 +0800 |
| commit | 38bbdd1c3d21b8be662a5bdcc92fc1f63e4c6ede (patch) | |
| tree | d0aa081d79a65310b6f1304f41122d24b79ad11b | |
| parent | 8b1c016df5df9afae54dcee9d1a4cc2ded6ddcc4 (diff) | |
| download | u-boot-imx-38bbdd1c3d21b8be662a5bdcc92fc1f63e4c6ede.zip u-boot-imx-38bbdd1c3d21b8be662a5bdcc92fc1f63e4c6ede.tar.gz u-boot-imx-38bbdd1c3d21b8be662a5bdcc92fc1f63e4c6ede.tar.bz2 | |
ENGR00301444 SD/MMC: Update fsl_esdhc driver for iMX6SX
The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0
on iMX6SX. So the fsl_esdhc driver must update to set the register,
otherwise no state can be detected.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index eed09e1..08f8666 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -39,6 +39,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE) + struct fsl_esdhc { uint dsaddr; uint blkattr; @@ -505,8 +510,15 @@ static int esdhc_init(struct mmc *mmc) /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); +#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO + /* Enable the BRR and BWR bits in IRQSTAT */ + esdhc_clrbits32(®s->irqstaten, IRQSTATEN_DINT); + esdhc_setbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); +#else /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); + esdhc_setbits32(®s->irqstaten, IRQSTATEN_DINT); +#endif /* Put the PROCTL reg back to the default */ esdhc_write32(®s->proctl, PROCTL_INIT); @@ -563,6 +575,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); + writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); + mmc->priv = cfg; mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; |