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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:16 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:20 -0500 |
| commit | 379c5145ef8f3adbcfeb0a47503838627959cb67 (patch) | |
| tree | d3125ad2d838363ae8b4eb617a38620f19c6e12c | |
| parent | d1001e3f0ce0059a55a870c42bac8aba2e4befec (diff) | |
| download | u-boot-imx-379c5145ef8f3adbcfeb0a47503838627959cb67.zip u-boot-imx-379c5145ef8f3adbcfeb0a47503838627959cb67.tar.gz u-boot-imx-379c5145ef8f3adbcfeb0a47503838627959cb67.tar.bz2 | |
powerpc/corenet2: fix mismatch DDR sync bit from RCW
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 40cce1d..f493483 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -60,7 +60,8 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_DDR_CLK_FREQ) || \ + (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ @@ -68,8 +69,13 @@ int checkcpu (void) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET - u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + u32 ddr_sync ; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + ddr_sync = 0; /* only async mode is supported */ +#else + ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ |