Merge branch 'master' of git://git.denx.de/u-boot-mips

* 'master' of git://git.denx.de/u-boot-mips:
  README: update MIPS related informations
  MIPS: make cache operation mode configurable
  MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG
  MIPS: INCA-IP: rename inca-swap-bytes host tool

5 files changed, 56 insertions, 10 deletions

diff --git a/README b/README
index aec28e3..a325892 100644
--- a/README
+++ b/README
@@ -180,6 +180,7 @@ Directory Hierarchy:
     /lib		Architecture specific library files
   /mips			Files generic to MIPS architecture
     /cpu		CPU specific files
+      /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
@@ -382,6 +383,38 @@ The following options need to be configured:
 		2. The core frequency as calculated above is multiplied
 		by this value.
 
+- MIPS CPU options:
+		CONFIG_SYS_INIT_SP_OFFSET
+
+		Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
+		pointer. This is needed for the temporary stack before
+		relocation.
+
+		CONFIG_SYS_MIPS_CACHE_MODE
+
+		Cache operation mode for the MIPS CPU.
+		See also arch/mips/include/asm/mipsregs.h.
+		Possible values are:
+			CONF_CM_CACHABLE_NO_WA
+			CONF_CM_CACHABLE_WA
+			CONF_CM_UNCACHED
+			CONF_CM_CACHABLE_NONCOHERENT
+			CONF_CM_CACHABLE_CE
+			CONF_CM_CACHABLE_COW
+			CONF_CM_CACHABLE_CUW
+			CONF_CM_CACHABLE_ACCELERATED
+
+		CONFIG_SYS_XWAY_EBU_BOOTCFG
+
+		Special option for Lantiq XWAY SoCs for booting from NOR flash.
+		See also arch/mips/cpu/mips32/start.S.
+
+		CONFIG_XWAY_SWAP_BYTES
+
+		Enable compilation of tools/xway-swap-bytes needed for Lantiq
+		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
+		be swapped if a flash programmer is used.
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -3070,7 +3103,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM only] If this variable is defined, then certain
+		[ARM, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 5d7467d..9c1b2f7 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -27,6 +27,10 @@
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
 	/*
 	 * For the moment disable interrupts, mark the kernel mode and
 	 * set ST0_KX so that the CPU does not spit fire when using
@@ -64,9 +68,16 @@
 _start:
 	RVECENT(reset,0)			# U-boot entry point
 	RVECENT(reset,1)			# software reboot
-#ifdef CONFIG_INCA_IP
-	.word INFINEON_EBU_BOOTCFG		# EBU init code, fetched during
-	.word 0x00000000			# booting phase of the flash
+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+	/*
+	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+	 * access external NOR flashes. If the board boots from NOR flash the
+	 * internal BootROM does a blind read at address 0xB0000010 to read the
+	 * initial configuration for that EBU in order to access the flash
+	 * device with correct parameters. This config option is board-specific.
+	 */
+	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
+	.word 0x00000000
 #else
 	RVECENT(romReserved,2)
 #endif
@@ -242,7 +253,7 @@ reset:
 	 nop
 
 	/* ... and enable them */
-	li	t0, CONF_CM_CACHABLE_NONCOHERENT
+	li	t0, CONFIG_SYS_MIPS_CACHE_MODE
 	mtc0	t0, CP0_CONFIG
 #endif
 
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index f2950e8..0e5ad2b 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -31,6 +31,8 @@
 #define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
 #define CONFIG_INCA_IP		1	/* on a INCA-IP Board	*/
 
+#define CONFIG_XWAY_SWAP_BYTES
+
 /*
  * Clock for the MIPS core (MHz)
  * allowed values: 100000000, 133000000, and 150000000 (default)
@@ -39,7 +41,7 @@
 #define CONFIG_CPU_CLOCK_RATE	150000000
 #endif
 
-#define INFINEON_EBU_BOOTCFG	0x40C4	/* CMULT = 8 */
+#define CONFIG_SYS_XWAY_EBU_BOOTCFG	0x40C4	/* CMULT = 8 */
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
diff --git a/tools/Makefile b/tools/Makefile
index 9733db4..e813e1d 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -43,7 +43,7 @@ ifneq ($(HOST_TOOLS_ALL),)
 CONFIG_LCD_LOGO = y
 CONFIG_CMD_LOADS = y
 CONFIG_CMD_NET = y
-CONFIG_INCA_IP = y
+CONFIG_XWAY_SWAP_BYTES = y
 CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
 endif
@@ -65,7 +65,7 @@ BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
 BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
 BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
 BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-BIN_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes$(SFX)
+BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
 BIN_FILES-y += mkimage$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
@@ -85,7 +85,7 @@ OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
 NOPED_OBJ_FILES-y += fit_image.o
 OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
 OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
+OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += imximage.o
 NOPED_OBJ_FILES-y += mkimage.o
@@ -179,7 +179,7 @@ $(obj)img2srec$(SFX):	$(obj)img2srec.o
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
 	$(HOSTSTRIP) $@
 
-$(obj)inca-swap-bytes$(SFX):	$(obj)inca-swap-bytes.o
+$(obj)xway-swap-bytes$(SFX):	$(obj)xway-swap-bytes.o
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
 	$(HOSTSTRIP) $@
 
diff --git a/tools/inca-swap-bytes.c b/tools/xway-swap-bytes.c
index 3a6d82d..3a6d82d 100644
--- a/tools/inca-swap-bytes.c
+++ b/tools/xway-swap-bytes.c