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author | Pardeep Kumar Singla <b45784@freescale.com> | 2013-11-04 10:48:10 +0800 |
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committer | Jason Liu <r64343@freescale.com> | 2013-11-22 13:11:03 +0800 |
commit | 53cc4d3645875739eb85992083dadd7dd0fdf9e4 (patch) | |
tree | 2365a337bb466382dcd28585366dad1948a79c56 | |
parent | e968e5301c42d2c2071f9ef871cfee8200e58b11 (diff) | |
download | u-boot-imx-53cc4d3645875739eb85992083dadd7dd0fdf9e4.zip u-boot-imx-53cc4d3645875739eb85992083dadd7dd0fdf9e4.tar.gz u-boot-imx-53cc4d3645875739eb85992083dadd7dd0fdf9e4.tar.bz2 |
mx6qsabresd: Add splash screen support via HDMI
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
(cherry picked from commit 58cc97877713f46d2e7dfd515844c29c70c56d82)
Signed-off-by: Jason Liu <r64343@freescale.com>
-rw-r--r-- | board/freescale/mx6qsabresd/mx6qsabresd.c | 65 | ||||
-rw-r--r-- | include/configs/mx6qsabre_common.h | 3 | ||||
-rw-r--r-- | include/configs/mx6qsabresd.h | 16 |
3 files changed, 82 insertions, 2 deletions
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 9723ba9..d7c39e1 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -42,7 +42,12 @@ #include <lcd.h> #include <mxc_epdc_fb.h> #endif - +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ @@ -814,6 +819,60 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_VIDEO_IPUV3) +static struct fb_videomode const hdmi = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + +int board_video_skip(void) +{ + int ret; + + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); + + if (ret) + printf("HDMI cannot be configured: %d\n", ret); + + imx_enable_hdmi_phy(); + return ret; +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_eth_init(bd_t *bis) { int ret; @@ -831,6 +890,10 @@ int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + #ifdef CONFIG_SYS_USE_SPINOR setup_spinor(); #endif diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index f9fbbfb..1920968 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -36,6 +36,7 @@ /* #define CONFIG_SECURE_BOOT */ #include "mx6_common.h" +#include <asm/sizes.h> #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -48,7 +49,7 @@ #define CONFIG_REVISION_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h index c6314b7..16e4e92 100644 --- a/include/configs/mx6qsabresd.h +++ b/include/configs/mx6qsabresd.h @@ -23,6 +23,7 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" #include "mx6qsabre_common.h" +#include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h> #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -65,5 +66,20 @@ #endif #endif #endif /* CONFIG_SPLASH_SCREEN */ +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI #endif /* __MX6QSABRESD_CONFIG_H */ |