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| author | Ye.Li <B37916@freescale.com> | 2013-11-18 16:21:30 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2013-11-20 11:02:46 +0800 |
| commit | c6d4a5f9317102313188b58cd6e4ad39ac5e1724 (patch) | |
| tree | e5e925193caa64ef552c31345f95eaa4b3c52d9a | |
| parent | 4243a8363a481dd96ecb344501af64dac24bc217 (diff) | |
| download | u-boot-imx-c6d4a5f9317102313188b58cd6e4ad39ac5e1724.zip u-boot-imx-c6d4a5f9317102313188b58cd6e4ad39ac5e1724.tar.gz u-boot-imx-c6d4a5f9317102313188b58cd6e4ad39ac5e1724.tar.bz2 | |
ENGR00270355 Fix eMMC fast boot hang issue
When booting in eMMC fast boot, the uboot v2013.04 always hangs.
The root cause is that MMC host does not exit from boot mode after
bootrom loading image. So the first command 'CMD0' sent
in uboot will pull down the CMD line to low and cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Signed-off-by: Ye Li <b37916@freescale.com>
(cherry picked from commit fa9f30b03b65b253ba292020f3ebbe70220e3c29)
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 27 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 9 |
2 files changed, 33 insertions, 3 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e945c0a..b5f6d62 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc + * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc. * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -61,10 +61,22 @@ struct fsl_esdhc { uint mixctrl; char reserved1[4]; uint fevt; - char reserved2[168]; + uint admaerrstat; + uint admasysaddr; + char reserved2[4]; + uint dllctrl; + uint dllstat; + uint clktunectrlstatus; + char reserved3[84]; + uint vendorspec; + uint mmcboot; + uint vendorspec2; + char reserved4[48]; uint hostver; +#ifndef ARCH_MXC char reserved3[780]; uint scr; +#endif }; /* Return the XFERTYP flags for a given command and data packet */ @@ -477,6 +489,17 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000); +#if defined(CONFIG_FSL_USDHC) + /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ + esdhc_write32(®s->mmcboot, 0x0); + /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ + esdhc_write32(®s->mixctrl, 0x0); + esdhc_write32(®s->clktunectrlstatus, 0x0); + + /* Put VEND_SPEC to default value */ + esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); +#endif + #ifndef ARCH_MXC /* Enable cache snooping */ esdhc_write32(®s->scr, 0x00000040); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 67d6057..ff56462 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc + * Copyright 2007-2008, 2010-2013 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -42,6 +42,12 @@ #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 +#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809 + #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) #define IRQSTAT_AC12E (0x01000000) @@ -95,6 +101,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDSTB (0x00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) |