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| author | Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> | 2012-04-02 02:57:55 +0000 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2012-04-02 15:54:53 +0200 |
| commit | 979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba (patch) | |
| tree | 2de67c3bedf4eaf71e6c4ea2449e4f8deab4a5bb | |
| parent | 71919cf15337c62b9ab389875a6a0855f0ed4461 (diff) | |
| download | u-boot-imx-979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba.zip u-boot-imx-979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba.tar.gz u-boot-imx-979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba.tar.bz2 | |
MIPS: fix inconsistency in config option for cache operation mode
Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
use the new config option in dcache_enable().
Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| -rw-r--r-- | arch/mips/cpu/mips32/cache.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec4..e683e8b 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include <asm/addrspace.h> #include <asm/cacheops.h> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + #define RA t8 /* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0 t0, CP0_CONFIG ori t0, CONF_CM_CMASK xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG jr ra END(dcache_enable) |