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| author | Jason Liu <r64343@freescale.com> | 2013-11-15 11:46:06 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2013-11-15 11:46:06 +0800 |
| commit | a929825706b5e1508b29d8ae2a2afb2fcbb2de19 (patch) | |
| tree | 563d1b4f0342a8c492eead04f76f2063359ddbd0 | |
| parent | 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b (diff) | |
| download | u-boot-imx-a929825706b5e1508b29d8ae2a2afb2fcbb2de19.zip u-boot-imx-a929825706b5e1508b29d8ae2a2afb2fcbb2de19.tar.gz u-boot-imx-a929825706b5e1508b29d8ae2a2afb2fcbb2de19.tar.bz2 | |
ENGR00285890 imx6:plugin: update the ROM_API_TABLE_BASE_ADDR for plugin code
i.MX6DQ TO1.5 and i.MX6DL/SOLO change the ROM_API_TABLE_BASE_ADDR
from 0xc0 to 0xc4.Need update the plugin code to sync with this change.
The change as the following for the new TO with i.MX6DQ, i.MX6DL/SOLO:
For i.MX6DQ, if the TO >=1.5, will use the new ROM_API_TABLE_BASE_ADDR=0xc4
For i.MX6DL/S, if the TO >=1.2, will use the new ROM_API_TABLE_BASE_ADDR=0xc4
For the old TO, we will still use the 0xc0 to keep compatible.
Signed-off-by: Jason Liu <r64343@freescale.com>
| -rw-r--r-- | board/freescale/mx6q_arm2/flash_header.S | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S index 4b6a403..8a8fac8 100644 --- a/board/freescale/mx6q_arm2/flash_header.S +++ b/board/freescale/mx6q_arm2/flash_header.S @@ -928,8 +928,13 @@ MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) #else -#define ROM_API_TABLE_BASE_ADDR (0x000000C0) -#define ROM_API_HWCNFG_SETUP_OFFSET (0x08) +#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0 +#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4 +#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4 +#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 +#define ROM_VERSION_OFFSET 0x48 +#define ROM_VERSION_TO12 0x12 +#define ROM_VERSION_TO15 0x15 /*****************PLUGIN IN mode********************/ @@ -1483,7 +1488,12 @@ plugin_start: * pu_irom_hwcnfg_setup is in 0x1fb5 ERIC : < what is the address in Rigel > */ before_calling_rom___pu_irom_hwcnfg_setup: - ldr r3, =ROM_API_TABLE_BASE_ADDR + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] + ldr r3, =ROM_VERSION_TO12 + cmp r4, r3 + ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 + ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] blx r4 after_calling_rom___pu_irom_hwcnfg_setup: @@ -1510,7 +1520,7 @@ COPY_SIZE: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET BOOT_DATA: .word TEXT_BASE .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET .word 0 -#else +#else /* i.MX6Q PATH */ /*DDR clock:480MHz, ipg clock:40MHz, AHB clock:80MHz*/ #define CONFIG_IPG_40M_FR_PLL3 @@ -1774,7 +1784,12 @@ plugin_start: * check the _pu_irom_api_table for the address */ before_calling_rom___pu_irom_hwcnfg_setup: - ldr r3, =ROM_API_TABLE_BASE_ADDR + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] + ldr r3, =ROM_VERSION_TO15 + cmp r4, r3 + ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 + ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] blx r4 after_calling_rom___pu_irom_hwcnfg_setup: |