ENGR00181348 pfuze sabresd: pfuze support in u-boot

add pfuze and I2C support, support cpu internal LDO bypass which can be
enabled by CONFIG_MX6_INTER_LDO_BYPASS
Signed-off-by: Robin Gong <B38343@freescale.com>

2 files changed, 131 insertions, 2 deletions

diff --git a/board/freescale/mx6q_sabresd/mx6q_sabresd.c b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
index 8974167..065c1ed 100644
--- a/board/freescale/mx6q_sabresd/mx6q_sabresd.c
+++ b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
@@ -26,6 +26,7 @@
 #include <asm/arch/mx6_pins.h>
 #include <asm/arch/mx6dl_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/regs-anadig.h>
 #include <asm/errno.h>
 #ifdef CONFIG_MXC_FEC
 #include <miiphy.h>
@@ -42,6 +43,10 @@
 #include <imx_spi.h>
 #endif
 
+#if CONFIG_I2C_MXC
+#include <i2c.h>
+#endif
+
 #ifdef CONFIG_CMD_MMC
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -316,6 +321,125 @@ void setup_lvds_poweron(void)
 }
 #endif
 
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+	unsigned int reg;
+
+	switch (module_base) {
+	case I2C1_BASE_ADDR:
+#if defined CONFIG_MX6Q
+		/* i2c1 SDA */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT8__I2C1_SDA);
+
+		/* i2c1 SCL */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT9__I2C1_SCL);
+#elif defined CONFIG_MX6DL
+		/* i2c1 SDA */
+		mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT8__I2C1_SDA);
+		/* i2c1 SCL */
+		mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT9__I2C1_SCL);
+#endif
+
+		/* Enable i2c clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+		reg |= 0xC0;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+		break;
+	case I2C2_BASE_ADDR:
+#if defined CONFIG_MX6Q
+		/* i2c2 SDA */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA);
+
+		/* i2c2 SCL */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL);
+#elif defined CONFIG_MX6DL
+		/* i2c2 SDA */
+		mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW3__I2C2_SDA);
+
+		/* i2c2 SCL */
+		mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL3__I2C2_SCL);
+#endif
+
+		/* Enable i2c clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+		reg |= 0x300;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+		break;
+	case I2C3_BASE_ADDR:
+#if defined CONFIG_MX6Q
+		/* GPIO_3 for I2C3_SCL */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__I2C3_SCL);
+		/* GPIO_6 for I2C3_SDA */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_6__I2C3_SDA);
+
+#elif defined CONFIG_MX6DL
+		/* GPIO_3 for I2C3_SCL */
+		mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_3__I2C3_SCL);
+		/* GPIO_6 for I2C3_SDA */
+		mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_6__I2C3_SDA;
+#endif
+		/* Enable i2c clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+		reg |= 0xC00;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+		break;
+	default:
+		printf("Invalid I2C base: 0x%x\n", module_base);
+		break;
+	}
+}
+
+void setup_pmic_voltages(void)
+{
+	unsigned char value = 0 ;
+	unsigned int val = 0;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (!i2c_probe(0x8)) {
+		if (i2c_read(0x8, 0, 1, &value, 1))
+			printf("%s:i2c_read:error\n", __func__);
+		printf("Found PFUZE100! device id=%x\n", value);
+		#if CONFIG_MX6_INTER_LDO_BYPASS
+		/*VDDCORE 1.1V@800Mhz: SW1AB*/
+		value = 0x20;
+		i2c_write(0x8, 0x20, 1, &value, 1);
+
+		/*VDDSOC 1.2V : SW1C*/
+		value = 0x24;
+		i2c_write(0x8, 0x2e, 1, &value, 1);
+
+		/* Bypass the VDDSOC from Anatop */
+		val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
+		val &= ~BM_ANADIG_REG_CORE_REG2_TRG;
+		val |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f);
+		REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
+
+		/* Bypass the VDDCORE from Anatop */
+		val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
+		val &= ~BM_ANADIG_REG_CORE_REG0_TRG;
+		val |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f);
+		REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
+
+		/* Bypass the VDDPU from Anatop */
+		val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
+		val &= ~BM_ANADIG_REG_CORE_REG1_TRG;
+		val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
+		REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
+
+		/*clear PowerDown Enable bit of WDOG1_WMCR*/
+		writew(0, WDOG1_BASE_ADDR + 0x08);
+		printf("hw_anadig_reg_core=%x\n",
+			REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE));
+		#endif
+
+	}
+}
+#endif
+
 #ifdef CONFIG_IMX_ECSPI
 s32 spi_get_cfg(struct imx_spi_dev_t *dev)
 {
@@ -763,6 +887,9 @@ int board_init(void)
 	setup_sata();
 #endif
 
+#ifdef CONFIG_I2C_MXC
+	setup_i2c(CONFIG_SYS_I2C_PORT);
+#endif
 #ifdef CONFIG_VIDEO_MX5
 	/* Enable lvds power */
 	setup_lvds_poweron();
@@ -912,6 +1039,7 @@ int check_recovery_cmd_file(void)
 
 int board_late_init(void)
 {
+	setup_pmic_voltages();
 	return 0;
 }
 
diff --git a/include/configs/mx6q_sabresd.h b/include/configs/mx6q_sabresd.h
index b699287..a5d6363 100644
--- a/include/configs/mx6q_sabresd.h
+++ b/include/configs/mx6q_sabresd.h
@@ -189,9 +189,10 @@
 #ifdef CONFIG_CMD_I2C
 	#define CONFIG_HARD_I2C         1
 	#define CONFIG_I2C_MXC          1
-	#define CONFIG_SYS_I2C_PORT             I2C3_BASE_ADDR
+	#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
 	#define CONFIG_SYS_I2C_SPEED            100000
-	#define CONFIG_SYS_I2C_SLAVE            0x1f
+	#define CONFIG_SYS_I2C_SLAVE            0x8
+	#define CONFIG_MX6_INTER_LDO_BYPASS	0
 #endif
 
 /*