diff options
| author | Jason Liu <r64343@freescale.com> | 2012-12-05 14:16:20 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-12-06 15:47:45 +0800 |
| commit | 5ab58aae66f7a29dc82a3ac9004f4aa3a5eba0bc (patch) | |
| tree | 813c89394fc9eb2ac9cbbfe5aa430c98783cb5b5 | |
| parent | ecc69a1f2a2b5c294fe156a8f38982f8f5c89a0a (diff) | |
| download | u-boot-imx-5ab58aae66f7a29dc82a3ac9004f4aa3a5eba0bc.zip u-boot-imx-5ab58aae66f7a29dc82a3ac9004f4aa3a5eba0bc.tar.gz u-boot-imx-5ab58aae66f7a29dc82a3ac9004f4aa3a5eba0bc.tar.bz2 | |
ENGR000234991 MX6DL/ARD: Two boards met kernel dump during boot uprel_imx_3.0.35_3.0.0
The issue is caused by DDR script changed io pads to DDR differential mode
but forget to do the calibration data update.
This patch updated the DDR script on MX6DL ARD board based on
the commit on the ddr-scripts-rel:
53121e0 Updated MX6DL and MX6DQ ARD and SabreSD scripts with new
calibration values for IO pads set to differential mode;
Signed-off-by: Jason Liu <r64343@freescale.com>
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index 86e2255..24cb155 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -386,14 +386,14 @@ MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F) MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F) # DQS gating, read delay, write delay calibration values # based on calibration compare of 0x00ffff00 -MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42120218) -MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x02030203) -MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x4302031A) -MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x027B0249) -MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4A494C4A) -MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x3A373345) -MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3F36) -MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x48334736) +MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42190217) +MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x017B017B) +MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x4176017B) +MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x015F016C) +MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4C4C4D4C) +MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x4A4D4C48) +MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3F40) +MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x3538382E) # read data bit delay MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) |