ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCR

From IC spec:
---
The Power down Counter inside WDOG-1 will be enabled out of reset.
This counter has a fixed time-out value of 16 seconds, after which
it will drive the WDOG-1 signal low.

To prevent this, the software must disable this counter by clearing
the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR)
within 16 seconds of reset de-assertion. Once disabled, this counter
cannot be enabled again until the next system reset occurs. This
feature is provided to prevent the hanging up of cores after reset, as
WDOG-1 is not enabled out of reset.
---

NOTE for the last sentence:
This feature requires a dedicated WDOG_B pin for it. The fact that changing
the IOMUX configuration can alter the WDOG_B functionality (GPIO by default)
is not ideal as it defeats the purpose of this feature. But it still
takes effect when the muxed pin is configured as WDOG_B within 16 seconds.

Clear PDE bit to avoid WDOG_B (aka, WDOG-1) assertion.

Tested on MX6SL. May add this for other MX6x.

Signed-off-by: Robby Cai <R63905@freescale.com>

3 files changed, 45 insertions, 4 deletions

diff --git a/board/freescale/mx6sl_arm2/mx6sl_arm2.c b/board/freescale/mx6sl_arm2/mx6sl_arm2.c
index f14b2b6..8abfd4e 100644
--- a/board/freescale/mx6sl_arm2/mx6sl_arm2.c
+++ b/board/freescale/mx6sl_arm2/mx6sl_arm2.c
@@ -31,6 +31,7 @@
 #include <asm/arch/iomux-v3.h>
 #include <asm/arch/regs-anadig.h>
 #include <asm/errno.h>
+#include <imx_wdog.h>
 #ifdef CONFIG_MXC_FEC
 #include <miiphy.h>
 #endif
@@ -1004,8 +1005,6 @@ void setup_pmic_voltages(void)
 		val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
 		REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
 
-		/*clear PowerDown Enable bit of WDOG1_WMCR*/
-		writew(0, WDOG1_BASE_ADDR + 0x08);
 		printf("hw_anadig_reg_core=%x\n",
 			REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE));
 		#endif
@@ -1025,6 +1024,8 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	wdog_preconfig(WDOG1_BASE_ADDR);
+
 	setup_uart();
 
 #ifdef CONFIG_MXC_FEC
diff --git a/board/freescale/mx6sl_evk/mx6sl_evk.c b/board/freescale/mx6sl_evk/mx6sl_evk.c
index 63705ea..85c3b61 100644
--- a/board/freescale/mx6sl_evk/mx6sl_evk.c
+++ b/board/freescale/mx6sl_evk/mx6sl_evk.c
@@ -31,6 +31,7 @@
 #include <asm/arch/iomux-v3.h>
 #include <asm/arch/regs-anadig.h>
 #include <asm/errno.h>
+#include <imx_wdog.h>
 #ifdef CONFIG_MXC_FEC
 #include <miiphy.h>
 #endif
@@ -973,8 +974,6 @@ void setup_pmic_voltages(void)
 		val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
 		REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
 
-		/*clear PowerDown Enable bit of WDOG1_WMCR */
-		writew(0, WDOG1_BASE_ADDR + 0x08);
 		printf("hw_anadig_reg_core=%x\n",
 		       REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE));
 #endif
@@ -994,6 +993,8 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	wdog_preconfig(WDOG1_BASE_ADDR);
+
 	setup_uart();
 
 #ifdef CONFIG_MXC_FEC
diff --git a/include/imx_wdog.h b/include/imx_wdog.h
new file mode 100644
index 0000000..40920f7
--- /dev/null
+++ b/include/imx_wdog.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef	_IMX_WDOG_H
+#define	_IMX_WDOG_H
+
+#include <asm/io.h>
+
+#define WDOGx_WMCR	0x8
+static inline void wdog_preconfig(int base_addr)
+{
+	/*
+	 * From IC spec:
+	 * The Power down Counter inside WDOG-1 will be enabled out of reset.
+	 * This counter has a fixed time-out value of 16 seconds, after which
+	 * it will drive the WDOG-1 signal low.
+	 *
+	 * To prevent this, the software must disable this counter by clearing
+	 * the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR).
+	 */
+	writew(0, base_addr + WDOGx_WMCR);
+}
+
+#endif