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| author | Fugang Duan <B38611@freescale.com> | 2012-11-08 16:37:29 +0800 |
|---|---|---|
| committer | Fugang Duan <B38611@freescale.com> | 2012-11-08 17:12:09 +0800 |
| commit | 27cdce50f9a7fc30d7cff067b420a32e5f2c5959 (patch) | |
| tree | f164afa77793f96d954d794ae2cf71571225631e | |
| parent | 6be77a3831084293070bd95e57164a8b0d3ddd09 (diff) | |
| download | u-boot-imx-27cdce50f9a7fc30d7cff067b420a32e5f2c5959.zip u-boot-imx-27cdce50f9a7fc30d7cff067b420a32e5f2c5959.tar.gz u-boot-imx-27cdce50f9a7fc30d7cff067b420a32e5f2c5959.tar.bz2 | |
ENGR00230364 - imx6sl: FEC: fix cycle reboot fail in EVK platform for bootp.rel_imx_3.0.35_12.10.02imx_v2009.08_12.10.02
In some imx6sl evk boards, fec cannot work fine while doing
cycle reboot via to execute command "reboot" in kernel.
The root cause: phys clock source is closed when reboot system,
and LAN8720 status machine is in disorder. So it needs to do phy
hardware reset to make phy enter normal state machine.
Signed-off-by: Fugang Duan <B38611@freescale.com>
| -rw-r--r-- | board/freescale/mx6sl_evk/mx6sl_evk.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/board/freescale/mx6sl_evk/mx6sl_evk.c b/board/freescale/mx6sl_evk/mx6sl_evk.c index 089373e..cdc3644 100644 --- a/board/freescale/mx6sl_evk/mx6sl_evk.c +++ b/board/freescale/mx6sl_evk/mx6sl_evk.c @@ -626,9 +626,9 @@ void enet_board_init(void) writel(reg, GPIO4_BASE_ADDR + 0x4); /* phy power enable and reset: gpio4_21 */ - /* DR: High Level on: Power ON */ + /* DR: High Level off: Power Off */ reg = readl(GPIO4_BASE_ADDR + 0x0); - reg |= (1 << 21); + reg &= ~(1 << 21); writel(reg, GPIO4_BASE_ADDR + 0x0); /* DIR: output */ @@ -636,6 +636,13 @@ void enet_board_init(void) reg |= (1 << 21); writel(reg, GPIO4_BASE_ADDR + 0x4); + udelay(1000); + + /* DR: High Level on: Power On */ + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= (1 << 21); + writel(reg, GPIO4_BASE_ADDR + 0x0); + /* wait RC ms for hw reset */ udelay(500); } |