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| author | Anson Huang <b20788@freescale.com> | 2012-12-05 13:58:34 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2013-03-27 17:43:59 +0800 |
| commit | d26f29ac28fa628c9b0ac87d3cb7576bb0440e50 (patch) | |
| tree | 9bfc1da00558b19216b3bf32ae9ea117d3456f35 | |
| parent | c7c2b8011905d936923be200a5d1b411258f8569 (diff) | |
| download | u-boot-imx-d26f29ac28fa628c9b0ac87d3cb7576bb0440e50.zip u-boot-imx-d26f29ac28fa628c9b0ac87d3cb7576bb0440e50.tar.gz u-boot-imx-d26f29ac28fa628c9b0ac87d3cb7576bb0440e50.tar.bz2 | |
ENGR00235821 mx6: correct work flow of PFDs
PFDs need to be gate/ungate after PLL lock to reset
PFDs to right state. Otherwise PFDs may lose correct
state in state-machine, then no output clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396
already since the bus clock needs it.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | cpu/arm_cortexa8/mx6/generic.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index 6a98d04..c82f689 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -1007,6 +1007,37 @@ int arch_cpu_init(void) { int val; + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE, + ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET); + writel(BM_ANADIG_PFD_528_PFD3_CLKGATE | +#ifdef CONFIG_MX6Q + BM_ANADIG_PFD_528_PFD2_CLKGATE | +#endif + BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, + ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET); + + writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE, + ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR); + writel(BM_ANADIG_PFD_528_PFD3_CLKGATE | +#ifdef CONFIG_MX6Q + BM_ANADIG_PFD_528_PFD2_CLKGATE | +#endif + BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, + ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR); + icache_enable(); dcache_enable(); |