* Patch by liang a lei, 9 Jan 2004:

  Fix Intel 28F128J3 ID in include/flash.h

* Patch by Masami Komiya, 09 Jan 2004:
  add support for TB0229 board (NEC VR4131 MIPS processor)

* Patch by Leon Kukovec, 12 Dec 2003:
  changed extern __inline__ into static __inline__ in
  include/linux/byteorder/swab.h

15 files changed, 1918 insertions, 11 deletions

diff --git a/CHANGELOG b/CHANGELOG
index fa3bbfe..8e4fee6 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,16 @@
 Changes since U-Boot 1.0.1:
 ======================================================================
 
+* Patch by liang a lei, 9 Jan 2004:
+  Fix Intel 28F128J3 ID in include/flash.h
+
+* Patch by Masami Komiya, 09 Jan 2004:
+  add support for TB0229 board (NEC VR4131 MIPS processor)
+
+* Patch by Leon Kukovec, 12 Dec 2003:
+  changed extern __inline__ into static __inline__ in
+  include/linux/byteorder/swab.h
+
 * Patch by Travis Sawyer, 30 Dec 2003:
   Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
   select MDI port based on enabled EMAC device.
diff --git a/Makefile b/Makefile
index 5f4102e..e622e68 100644
--- a/Makefile
+++ b/Makefile
@@ -1027,6 +1027,9 @@ incaip_config: unconfig
 		}
 	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
 
+tb0229_config: unconfig
+	@./mkconfig $(@:_config=) mips mips tb0229
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
diff --git a/board/tb0229/Makefile b/board/tb0229/Makefile
new file mode 100644
index 0000000..e7bb8cb
--- /dev/null
+++ b/board/tb0229/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o vr4131-pci.o
+SOBJS	= memsetup.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/tb0229/config.mk b/board/tb0229/config.mk
new file mode 100644
index 0000000..9a50850
--- /dev/null
+++ b/board/tb0229/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# ROM version
+TEXT_BASE = 0xBFC00000
+
+# RAM version
+#TEXT_BASE = 0x80400000
diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c
new file mode 100644
index 0000000..5dea463
--- /dev/null
+++ b/board/tb0229/flash.c
@@ -0,0 +1,1198 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define	FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
+
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t * info, ulong dest, ushort data);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE,
+				&flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+#if 0				/* sand: */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM - monitor_flash_len +
+				      size_b0,
+				      FLASH_BASE0_PRELIM - 1 + size_b0,
+				      &flash_info[0]);
+#else
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CFG_MONITOR_BASE,
+				      CFG_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[0]);
+#endif
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	}
+#ifdef CFG_FLASH_BASE_2
+	/* 2 banks */
+	else {
+		size_b1 =
+			flash_get_size ((volatile FLASH_WORD_SIZE *)
+					CFG_FLASH_BASE_2, &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr (ebccfga, pb0cr);
+			pbcr = mfdcr (ebccfgd);
+			mtdcr (ebccfga, pb0cr);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr (ebccfgd, pbcr);
+			/*          printf("pb1cr = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr (ebccfga, pb1cr);
+			pbcr = mfdcr (ebccfgd);
+			mtdcr (ebccfga, pb1cr);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr (ebccfgd, pbcr);
+			/*            printf("pb0cr = %x\n", pbcr); */
+		}
+
+		size_b0 =
+			flash_get_size ((volatile FLASH_WORD_SIZE *) base_b0,
+					&flash_info[0]);
+
+		flash_get_offsets (base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+#if 0				/* sand: */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM - monitor_flash_len +
+				      size_b0,
+				      FLASH_BASE0_PRELIM - 1 + size_b0,
+				      &flash_info[0]);
+#else
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CFG_MONITOR_BASE,
+				      CFG_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[0]);
+#endif
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+				flash_get_size ((volatile FLASH_WORD_SIZE *)
+						base_b1, &flash_info[1]);
+
+			flash_get_offsets (base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void) flash_protect (FLAG_PROTECT_SET,
+					      base_b1 + size_b1 -
+					      monitor_flash_len,
+					      base_b1 + size_b1 - 1,
+					      &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void) flash_protect (FLAG_PROTECT_CLEAR,
+					      base_b0 + size_b0 -
+					      monitor_flash_len,
+					      base_b0 + size_b0 - 1,
+					      &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+#endif
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] =
+				base + (i * info->size / info->sector_count);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[] = ", bottom boot sect)\n";
+	uchar topboot[] = ", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	if (info->flash_id & 0x0001) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800B:
+		printf ("INTEL28F800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800T:
+		printf ("INTEL28F800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160B:
+		printf ("INTEL28F160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160T:
+		printf ("INTEL28F160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320B:
+		printf ("INTEL28F320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320T:
+		printf ("INTEL28F320T (32 Mbit%s", boottype);
+		break;
+
+#if 0				/* enable when devices are available */
+
+	case FLASH_INTEL640B:
+		printf ("INTEL28F640B (64 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL640T:
+		printf ("INTEL28F640T (64 Mbit%s", boottype);
+		break;
+#endif
+	case FLASH_28F320J3A:
+		printf ("INTEL28F320J3A (32 Mbit%s", boottype);
+		break;
+	case FLASH_28F640J3A:
+		printf ("INTEL28F640J3A (64 Mbit%s", boottype);
+		break;
+	case FLASH_28F128J3A:
+		printf ("INTEL28F128J3A (128 Mbit%s", boottype);
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
+{
+	short i;
+	ulong base = (ulong) addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CFG_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if (addr[0x0000] != 0x00890089) {
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if (addr[0x0000] != 0x0089) {
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+
+	}
+
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0				/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+#if 0				/* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+#endif
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;		/* => 32 MBit   */
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 64 MBit   */
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 128 MBit          */
+
+	default:
+		/* FIXME */
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	flash_get_offsets (base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
+#ifndef CFG_FLASH_16BIT
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+#else
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+#endif
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->
+								     start
+								     [sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
+
+
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
+#ifndef CFG_FLASH_16BIT
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00500050;
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
+				}
+#else
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0050;	/* clear status register */
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
+#endif
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+#ifndef CFG_FLASH_16BIT
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+#else
+			addr[0] = (0x00FF & FLASH_ID_MASK);	/* reset bank */
+#endif
+		}
+
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+
+/*int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+										ulong b_end = info->start[0] + info->size;*//* bank end addr */
+/*		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+*//* finally write data to flash */
+/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+#ifndef CFG_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CFG_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i = 0; i < 2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_short (info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+#if defined (__MIPSEL__)
+	data = cpu_to_be32 (data);
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+
+	*((vu_long *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+
+		while ((*((vu_long *) dest) & 0x00800080) !=
+		       (data & 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				printf ("timeout\n");
+				return (1);
+			}
+		}
+
+	} else {
+
+		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				printf ("timeout\n");
+				return (1);
+			}
+		}
+
+		if (addr[0] & 0x003A003A) {	/* check for error */
+			barf = addr[0] & 0x003A0000;
+			if (barf) {
+				barf >>= 16;
+			} else {
+				barf = addr[0] & 0x0000003A;
+			}
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+
+
+	}
+
+	return (0);
+}
+
+#else
+
+static int write_short (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+#if defined (__MIPSEL__)
+	data = cpu_to_be16 (data);
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+		/* intel stuff */
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		if (addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		*addr = 0x00FF;
+
+	}
+
+	return (0);
+
+}
+#endif
diff --git a/board/tb0229/memsetup.S b/board/tb0229/memsetup.S
new file mode 100644
index 0000000..0eaf45d
--- /dev/null
+++ b/board/tb0229/memsetup.S
@@ -0,0 +1,71 @@
+/*
+ *  Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ *  Copyright (c) 2003  Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+	.globl  memsetup
+memsetup:
+
+	/* BCUCNTREG1 = 0x0040 */
+	la	t0, 0xaf000000
+	li	t1, 0x0040
+	sh	t1, 0(t0)
+
+	/* ROMSIZEREG = 0x3333 */
+	la	t0, 0xaf000004
+	li	t1, 0x3333
+	sh	t1, 0(t0)
+
+	/* ROMSPEEDREG = 0x3003 */
+	la	t0, 0xaf000006
+	li	t1, 0x3003
+	sh	t1, 0(t0)
+
+	/* BCUCNTREG3 = 0 */
+	la	t0, 0xaf000016
+	li	t1, 0x0000
+	sh	t1, 0(t0)
+
+	/* CMUCLKMSK */
+	la	t0, 0xaf000060
+	li	t1, 0x39a2
+	sh	t1, 0(t0)
+
+	/* PMUCNTREG */
+	la	t0, 0xaf0000c2
+	li	t1, 0x0006
+	sh	t1, 0(t0)
+
+	/* SDRAMMODEREG = 0x8029 */
+	la	t0, 0xaf000400
+	li	t1, 0x8029
+	sh	t1, 0(t0)
+
+	/* SDRAMCNTREG = 0x2322 */
+	la	t0, 0xaf000402
+	li	t1, 0x2322
+	sh	t1, 0(t0)
+
+	/* BCURFCNTREG = 0x0106 */
+	la	t0, 0xaf000404
+	li	t1, 0x0106
+	sh	t1, 0(t0)
+
+	/* RAMSZEREG = 0x5555 (64MB Bank) */
+	la	t0, 0xaf000408
+	li	t1, 0x5555
+	sh	t1, 0(t0)
+
+	j       ra
+	nop
diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
new file mode 100644
index 0000000..e7914bd
--- /dev/null
+++ b/board/tb0229/tb0229.c
@@ -0,0 +1,42 @@
+/*
+ * Board initialize code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/inca-ip.h>
+#include <pci.h>
+
+unsigned long mips_io_port_base = 0;
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+
+void pci_init_board (void)
+{
+	init_vr4131_pci(&hose);
+}
+#endif
+
+
+long int initdram(int board_type)
+{
+	return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
+}
+
+
+int checkboard (void)
+{
+	printf("Board: TANBAC TB0229 ");
+	printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+
+	return 0;
+}
diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds
new file mode 100644
index 0000000..a6429b6
--- /dev/null
+++ b/board/tb0229/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
new file mode 100644
index 0000000..0ee4bf3
--- /dev/null
+++ b/board/tb0229/vr4131-pci.c
@@ -0,0 +1,254 @@
+/*
+ * VR4131 PCIU support code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/addrspace.h>
+
+#define VR4131_PCIMMAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG	(volatile unsigned int*)(KSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG	(volatile unsigned int*)(KSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG	(volatile unsigned int*)(KSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG	(volatile unsigned int*)(KSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG	(volatile unsigned int*)(KSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG	(volatile unsigned int*)(KSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG		(volatile unsigned int*)(KSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG	(volatile unsigned int*)(KSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG	(volatile unsigned int*)(KSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG	(volatile unsigned int*)(KSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_REVREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG	(volatile unsigned int*)(KSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG	(volatile unsigned int*)(KSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG	(volatile unsigned int*)(KSEG1 + 0x0f000d18)
+
+/*#define VR41XX_PCIIRQ_OFFSET    (VR41XX_IRQ_MAX + 1)	*/
+/*#define VR41XX_PCIIRQ_MAX       (VR41XX_IRQ_MAX + 12)	*/
+/*#define VR4122_PCI_HOST_BASE    0xa0000000		*/
+
+volatile unsigned int *pciconfigaddr;
+volatile unsigned int *pciconfigdata;
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+/*
+ *	Access PCI Configuration Register for VR4131
+ */
+
+static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
+				     u32 * data)
+{
+	u32 bus;
+	u32 device;
+
+	bus = ((dev & 0xff0000) >> 16);
+	device = ((dev & 0xf800) >> 11);
+
+	if (bus == 0) {
+		/* Type 0 Configuration */
+		*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
+	} else {
+		/* Type 1 Configuration */
+		*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
+	}
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		*VR4131_PCICONFDREG = *data;
+	} else {
+		*data = *VR4131_PCICONFDREG;
+	}
+
+	return (0);
+}
+
+static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+{
+	u32 data;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+{
+	u32 data;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xffff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
+					 u32 * val)
+{
+	u32 data = 0;
+
+	if (reg & 3)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = data;
+
+	return (0);
+}
+
+static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+{
+	u32 data = 0;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
+						       ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+
+static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+{
+	u32 data = 0;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
+							 ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+{
+	u32 data;
+
+	if (reg & 3) {
+		return -1;
+	}
+
+	data = val;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return (0);
+}
+
+
+/*
+ *	Initialize VR4131 PCIU
+ */
+
+vr4131_pciu_init ()
+{
+	/* PCI clock */
+	*VR4131_PCICLKSELREG = 0x00000002;
+
+	/* PCI memory and I/O space */
+	*VR4131_PCIMMAW1REG = 0x100F9010;
+	*VR4131_PCIMMAW2REG = 0x140FD014;
+	*VR4131_PCIMIOAWREG = 0x160FD000;
+
+	/* Target memory window */
+	*VR4131_PCITAW1REG = 0x00081000;	/* 64MB */
+	*VR4131_PCITAW2REG = 0x00000000;
+
+	*VR4131_MAILBAREG = 0UL;
+	*VR4131_PCIMBA1REG = 0UL;
+
+	*VR4131_PCITRDYREG = 0x00008004;
+
+	*VR4131_PCIENREG = 0x00000004;	/* PCI enable */
+	*VR4131_COMMANDREG = 0x02000007;
+}
+
+/*
+ *	Initialize Module
+ */
+
+void init_vr4131_pci (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	vr4131_pciu_init ();	/* Initialize VR4131 PCIU */
+
+	/* PCI memory space #1 */
+	pci_set_region (hose->regions + 0,
+			0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
+
+	/* PCI memory space #2 */
+	pci_set_region (hose->regions + 1,
+			0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
+
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 2,
+			0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region (hose->regions + 3,
+			0x00000000,
+			0x80000000,
+			0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	hose->read_byte = vr4131_pci_read_config_byte;
+	hose->read_word = vr4131_pci_read_config_word;
+	hose->read_dword = vr4131_pci_read_config_dword;
+	hose->write_byte = vr4131_pci_write_config_byte;
+	hose->write_word = vr4131_pci_write_config_word;
+	hose->write_dword = vr4131_pci_write_config_dword;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+
+	return;
+}
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index e73d138..f48675e 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -30,7 +30,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 #if defined(CONFIG_INCA_IP)
 	*INCA_IP_WDT_RST_REQ = 0x3f;
-#elif defined(CONFIG_PURPLE)
+#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
 	void (*f)(void) = (void *) 0xbfc00000;
 
 	f();
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index 59c6acf..45a90a8 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -214,7 +214,11 @@ reset:
 	mtc0	zero, CP0_WATCHHI
 
 	/* STATUS register */
+#ifdef  CONFIG_TB0229
+	li	k0, ST0_CU0
+#else
 	mfc0	k0, CP0_STATUS
+#endif
 	li	k1, ~ST0_IE
 	and	k0, k1
 	mtc0	k0, CP0_STATUS
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 845dd7c..b8214b1 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -44,7 +44,7 @@
  * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
-#ifdef CONFIG_AU1X00
+#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
 /* We use a 36 bit physical address map here and
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
new file mode 100644
index 0000000..53fafdd
--- /dev/null
+++ b/include/configs/tb0229.h
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2003
+ * Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for TANBAC TB0229 board using an VR4131 CPU module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
+#define CONFIG_TB0229		1	/* on a TB0229 Board	*/
+
+#ifndef CPU_CLOCK_RATE
+#define CPU_CLOCK_RATE	200000000	/* 200 MHz clock for the MIPS core */
+#endif
+#define CPU_TCLOCK_RATE 16588800	/* 16.5888 MHz for TClock */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \
+	"echo Type \"run netboot_initrd\" for the network boot with initrd;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \"run flash_local\" to mount local root filesystem;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netboot=dhcp;tftp;run netargs; bootm\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0"		\
+	"localargs=setenv bootargs root=1F02 ip=dhcp\0"			\
+	"addmisc=setenv bootargs $(bootargs) "				\
+		"console=ttyS0,$(baudrate) "				\
+		"read-only=readonly\0"					\
+	"netargs=run nfsargs addmisc\0"					\
+	"flash_nfs=run nfsargs addmisc;"				\
+		"bootm $(kernel_addr)\0"				\
+	"flash_local=run localargs addmisc;"				\
+		"bootm $(kernel_addr)\0"				\
+	"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;"		\
+		"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
+		"run addmisc;"						\
+		"bootm 80400000 80600000\0"				\
+	"rootpath=/export/miniroot-mipsel\0"				\
+	"autoload=no\0"							\
+	"kernel_addr=BFC60000\0"					\
+	"ramdisk_addr=B0100000\0"					\
+	"u-boot=u-boot.bin\0"						\
+	"bootfile=uImage\0"						\
+	"load=dhcp;tftp 80400000 $(u-boot)\0"				\
+	"load_kernel=dhcp;tftp 80400000 $(bootfile)\0"			\
+	"update_uboot=run load;"					\
+		"protect off BFC00000 BFC3FFFF;"			\
+		"erase BFC00000 BFC3FFFF;"				\
+		"cp.b 80400000 BFC00000 $(filesize)\0"			\
+	"update_kernel=run load_kernel;"				\
+		"erase BFC60000 BFD5FFFF;"				\
+		"cp.b 80400000 BFC60000 $(filesize)\0"			\
+	"initenv=erase bfc40000 bfc5ffff\0"				\
+	""
+//#define CONFIG_BOOTCOMMAND	"run flash_local"
+#define CONFIG_BOOTCOMMAND	"run netboot"
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_PCI	| \
+				 CFG_CMD_ELF	)
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	     */
+#define CFG_PROMPT		"# "		/* Monitor Command Prompt    */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args*/
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+#define CFG_HZ			(CPU_TCLOCK_RATE/4)
+
+#define CFG_SDRAM_BASE		0x80000000
+
+#define CFG_LOAD_ADDR		0x80400000	/* default load address */
+
+#define CFG_MEMTEST_START	0x80000000
+#define CFG_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xbfc00000 /* Flash Bank #1 */
+
+/* The following #defines are needed to get flash environment right */
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)
+
+#define CFG_INIT_SP_OFFSET	0x400000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xBFC40000
+#define CFG_ENV_SIZE		0x20000
+
+#define CFG_DIRECT_FLASH_TFTP
+
+#define CONFIG_NR_DRAM_BANKS	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_ICACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	 1
+#define CFG_NS16550_CLK		 18432000
+#define CFG_NS16550_COM1	 0xaf000800
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+
+#define CONFIG_RTL8139
+
+#endif	/* __CONFIG_H */
diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h
index 755a821..03468f7 100644
--- a/include/linux/byteorder/swab.h
+++ b/include/linux/byteorder/swab.h
@@ -96,34 +96,34 @@
 #endif /* OPTIMIZE */
 
 
-extern __inline__ __const__ __u16 __fswab16(__u16 x)
+static __inline__ __const__ __u16 __fswab16(__u16 x)
 {
 	return __arch__swab16(x);
 }
-extern __inline__ __u16 __swab16p(__u16 *x)
+static __inline__ __u16 __swab16p(__u16 *x)
 {
 	return __arch__swab16p(x);
 }
-extern __inline__ void __swab16s(__u16 *addr)
+static __inline__ void __swab16s(__u16 *addr)
 {
 	__arch__swab16s(addr);
 }
 
-extern __inline__ __const__ __u32 __fswab32(__u32 x)
+static __inline__ __const__ __u32 __fswab32(__u32 x)
 {
 	return __arch__swab32(x);
 }
-extern __inline__ __u32 __swab32p(__u32 *x)
+static __inline__ __u32 __swab32p(__u32 *x)
 {
 	return __arch__swab32p(x);
 }
-extern __inline__ void __swab32s(__u32 *addr)
+static __inline__ void __swab32s(__u32 *addr)
 {
 	__arch__swab32s(addr);
 }
 
 #ifdef __BYTEORDER_HAS_U64__
-extern __inline__ __const__ __u64 __fswab64(__u64 x)
+static __inline__ __const__ __u64 __fswab64(__u64 x)
 {
 #  ifdef __SWAB_64_THRU_32__
 	__u32 h = x >> 32;
@@ -133,11 +133,11 @@ extern __inline__ __const__ __u64 __fswab64(__u64 x)
 	return __arch__swab64(x);
 #  endif
 }
-extern __inline__ __u64 __swab64p(__u64 *x)
+static __inline__ __u64 __swab64p(__u64 *x)
 {
 	return __arch__swab64p(x);
 }
-extern __inline__ void __swab64s(__u64 *addr)
+static __inline__ void __swab64s(__u64 *addr)
 {
 	__arch__swab64s(addr);
 }
diff --git a/lib_mips/board.c b/lib_mips/board.c
index 0727095..65a0bc3 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -393,6 +393,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* IP Address */
 	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
 
+#if defined(CONFIG_PCI)
+	/*
+	 * Do pci configuration
+	 */
+	pci_init();
+#endif
+
 /** leave this here (after malloc(), environment and PCI are working) **/
 	/* Initialize devices */
 	devices_init ();