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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-05-29 01:21:24 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-06-09 13:31:20 -0500 |
| commit | ee1e35bede91debc8bff9b02f75574486033b652 (patch) | |
| tree | ed995b8f3cc010641304958076f893f90d412336 | |
| parent | 3b9519fc50802436e417c839e69df7b2016cade5 (diff) | |
| download | u-boot-imx-ee1e35bede91debc8bff9b02f75574486033b652.zip u-boot-imx-ee1e35bede91debc8bff9b02f75574486033b652.tar.gz u-boot-imx-ee1e35bede91debc8bff9b02f75574486033b652.tar.bz2 | |
85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 9873383..58d23f4 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -75,8 +75,12 @@ int checkcpu (void) uint ver; uint major, minor; int i; - u32 ddr_ratio; +#ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; +#else + u32 ddr_ratio = 0; +#endif svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -118,7 +122,7 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", |