Merge with /home/wd/git/u-boot/jon_loeliger

117 files changed, 10939 insertions, 484 deletions

diff --git a/CHANGELOG b/CHANGELOG
index d98b56f..f1484ee 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,51 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Jon Loeliger
+  Fix style issues primarily in 85xx and 83xx boards.
+    - C++ comments
+    - Trailing white space
+    - Indentation not by TAB
+    - Excessive amount of empty lines
+    - Trailing empty lines
+
+* Patch by Ron Alder, 11 Jul 2005
+    Add Xianghua Xiao and Lunsheng Wang's support for the
+    GDA MPC8540 EVAL board.
+
+* Patch by Eran Liberty
+  Add support for the Freescale MPC8349ADS board.
+
+* Patch by Jon Loeliger, 25 Jul 2005
+  Move the TSEC driver out of cpu/mpc85xx as it will be shared
+  by the upcoming mpc83xx family as well.
+
+* Patch by Jon Loeliger, 05 May 2005
+  Implemented support for MPC8548CDS board.
+  Added DDR II support based on SPD values for MPC85xx boards.
+  This roll-up patch also includes bugfies for the previously
+  published patches:
+    DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
+
+* Patch by Jon Loeliger, 10 Feb 2005
+  Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
+
+* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
+  For MPC85xxCDS:
+    Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
+    for faster flash parts.
+    Add documentation for BR/OR for FLASH.
+
+* Patch by Jon Loeliger 08 Feb 2005
+  Determine L2 Cache size dynamically on 85XX boards.
+
+* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
+  - Convert the CPM2 based functionality to use new CONFIG_CPM2
+    option rather than a myriad of CONFIG_MPC8560-like variants.
+    Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
+    Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
+    new CONFIG_CPM2 option to each 8260 board.
+
 * Add support for MicroSys PM856 board
   Patch by Josef Wagner, 03 Aug 2005
 
diff --git a/MAKEALL b/MAKEALL
index f934091..2d0c096 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -108,13 +108,22 @@ LIST_8260="	\
 "
 
 #########################################################################
+## MPC83xx Systems (includes 8349, etc.)
+#########################################################################
+
+LIST_83xx="	\
+	MPC8349ADS	\
+"
+
+
+#########################################################################
 ## MPC85xx Systems (includes 8540, 8560 etc.)
 #########################################################################
 
 LIST_85xx="	\
-	MPC8540ADS	MPC8541CDS	MPC8555CDS	MPC8560ADS	\
-	PM854		PM856		sbc8540		sbc8560		\
-	stxgp3		TQM8540						\
+	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8548CDS	\
+	MPC8555CDS	MPC8560ADS	PM854		PM856		\
+	sbc8540		sbc8560		stxgp3		TQM8540		\
 "
 
 #########################################################################
@@ -133,6 +142,7 @@ LIST_7xx="	\
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
 	  ${LIST_8xx}				\
 	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+	  ${LIST_83xx}				\
 	  ${LIST_85xx}				\
 	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"
@@ -250,7 +260,7 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
+	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
 	arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
 	microblaze| \
 	mips| \
diff --git a/Makefile b/Makefile
index a372fe9..8fb600d 100644
--- a/Makefile
+++ b/Makefile
@@ -54,7 +54,7 @@ ifeq ($(HOSTARCH),ppc)
 CROSS_COMPILE =
 else
 ifeq ($(ARCH),ppc)
-CROSS_COMPILE = ppc_8xx-
+CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
 CROSS_COMPILE = arm-linux-
@@ -97,6 +97,9 @@ endif
 ifeq ($(CPU),ppc4xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
+ifeq ($(CPU),mpc83xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif
 ifeq ($(CPU),mpc85xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
@@ -1193,18 +1196,48 @@ TASREG_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd
 
 #########################################################################
+## MPC83xx Systems
+#########################################################################
+
+MPC8349ADS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
+
+#########################################################################
 ## MPC85xx Systems
 #########################################################################
 
 MPC8540ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
 
+MPC8540EVAL_config \
+MPC8540EVAL_33_config \
+MPC8540EVAL_66_config \
+MPC8540EVAL_33_slave_config \
+MPC8540EVAL_66_slave_config:      unconfig
+	@echo "" >include/config.h ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		echo -n "... 33 MHz PCI" ; \
+	else \
+		echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \
+		echo -n "... 66 MHz PCI" ; \
+	fi ; \
+	if [ "$(findstring _slave_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \
+		echo " slave" ; \
+	else \
+		echo " host" ; \
+	fi
+	@./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval
+
 MPC8560ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
 
 MPC8541CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
 
+MPC8548CDS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds
+
 MPC8555CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
 
diff --git a/README b/README
index 6327f64..9283c5e 100644
--- a/README
+++ b/README
@@ -287,17 +287,17 @@ The following options need to be configured:
 		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_SXNI855T
 		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM823L
 		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM8260
-		CONFIG_ep8260		CONFIG_MPC8560ADS	CONFIG_TQM850L
-		CONFIG_ERIC		CONFIG_MUSENKI		CONFIG_TQM855L
-		CONFIG_ESTEEM192E	CONFIG_MVS1		CONFIG_TQM860L
-		CONFIG_ETX094		CONFIG_NETPHONE		CONFIG_TTTech
-		CONFIG_EVB64260		CONFIG_NETTA		CONFIG_UTX8245
-		CONFIG_FADS823		CONFIG_NETVIA		CONFIG_V37
-		CONFIG_FADS850SAR	CONFIG_NX823		CONFIG_W7OLMC
-		CONFIG_FADS860T		CONFIG_OCRTC		CONFIG_W7OLMG
-		CONFIG_FLAGADM		CONFIG_ORSG		CONFIG_WALNUT
-		CONFIG_FPS850L		CONFIG_OXC		CONFIG_ZPC1900
-		CONFIG_FPS860L					CONFIG_ZUMA
+		CONFIG_ep8260		CONFIG_MPC8540EVAL	CONFIG_TQM850L
+		CONFIG_ERIC		CONFIG_MPC8560ADS	CONFIG_TQM855L
+		CONFIG_ESTEEM192E	CONFIG_MUSENKI		CONFIG_TQM860L
+		CONFIG_ETX094		CONFIG_MVS1		CONFIG_TTTech
+		CONFIG_EVB64260		CONFIG_NETPHONE		CONFIG_UTX8245
+		CONFIG_FADS823		CONFIG_NETTA		CONFIG_V37
+		CONFIG_FADS850SAR	CONFIG_NETVIA		CONFIG_W7OLMC
+		CONFIG_FADS860T		CONFIG_NX823		CONFIG_W7OLMG
+		CONFIG_FLAGADM		CONFIG_OCRTC		CONFIG_WALNUT
+		CONFIG_FPS850L		CONFIG_ORSG		CONFIG_ZPC1900
+		CONFIG_FPS860L		CONFIG_OXC		CONFIG_ZUMA
 
 		ARM based boards:
 		-----------------
@@ -2186,14 +2186,14 @@ configurations; the following names are supported:
 	DUET_ADS_config		MBX_config		sbc8560_66_config
 	EBONY_config		MPC8260ADS_config	SM850_config
 	ELPT860_config		MPC8540ADS_config	SPD823TS_config
-	ESTEEM192E_config	MPC8560ADS_config	stxgp3_config
-	ETX094_config		NETVIA_config		SXNI855T_config
-	FADS823_config		omap1510inn_config	TQM823L_config
-	FADS850SAR_config	omap1610h2_config	TQM850L_config
-	FADS860T_config		omap1610inn_config	TQM855L_config
-	FPS850L_config		omap5912osk_config	TQM860L_config
-				omap2420h4_config	walnut_config
-							Yukon8220_config
+	ESTEEM192E_config	MPC8540EVAL_config	stxgp3_config
+	ETX094_config		MPC8560ADS_config	SXNI855T_config
+	FADS823_config		NETVIA_config		TQM823L_config
+	FADS850SAR_config	omap1510inn_config	TQM850L_config
+	FADS860T_config		omap1610h2_config	TQM855L_config
+	FPS850L_config		omap1610inn_config	TQM860L_config
+				omap5912osk_config	walnut_config
+				omap2420h4_config	Yukon8220_config
 							ZPC1900_config
 
 Note: for some board special configuration names may exist; check if
diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c
index c75a4df..6b8aa68 100644
--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/cds/mpc8541cds/mpc8541cds.c
@@ -32,7 +32,7 @@
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
@@ -271,7 +271,7 @@ initdram(int board_type)
 #endif
 	dram_size = spd_sdram();
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */
diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/cds/mpc8541cds/u-boot.lds
index f8cee53..bd697d8 100644
--- a/board/cds/mpc8541cds/u-boot.lds
+++ b/board/cds/mpc8541cds/u-boot.lds
@@ -69,7 +69,6 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile
new file mode 100644
index 0000000..0d4abbd
--- /dev/null
+++ b/board/cds/mpc8548cds/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk
new file mode 100644
index 0000000..242a676
--- /dev/null
+++ b/board/cds/mpc8548cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8548cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
new file mode 100644
index 0000000..53dcd0d
--- /dev/null
+++ b/board/cds/mpc8548cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
new file mode 100644
index 0000000..5bc0890
--- /dev/null
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8548 uses "new" 15-16 style addressing.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds
new file mode 100644
index 0000000..36d2407
--- /dev/null
+++ b/board/cds/mpc8548cds/u-boot.lds
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8548cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8548cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c
index a40de21..18adf5b 100644
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/cds/mpc8555cds/mpc8555cds.c
@@ -30,7 +30,7 @@
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
@@ -269,7 +269,7 @@ initdram(int board_type)
 #endif
 	dram_size = spd_sdram();
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */
diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/cds/mpc8555cds/u-boot.lds
index d14cb9c..5d45d38 100644
--- a/board/cds/mpc8555cds/u-boot.lds
+++ b/board/cds/mpc8555cds/u-boot.lds
@@ -69,7 +69,6 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile
new file mode 100644
index 0000000..4327b0d
--- /dev/null
+++ b/board/mpc8349ads/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk
new file mode 100644
index 0000000..4602169
--- /dev/null
+++ b/board/mpc8349ads/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC83xxADS
+#
+
+TEXT_BASE  =   0xFE700000
diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c
new file mode 100644
index 0000000..da8d3d7
--- /dev/null
+++ b/board/mpc8349ads/mpc8349ads.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+
+	/* Enable flash write */
+	bcsr[1] &= ~0x01;
+
+	return 0;
+}
+
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram(NULL);
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+	puts("   DDR RAM: ");
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+
+	im->ddr.csbnds[0].csbnds = 0x00100017;
+	im->ddr.csbnds[1].csbnds = 0x0018001f;
+	im->ddr.csbnds[2].csbnds = 0x00000007;
+	im->ddr.csbnds[3].csbnds = 0x0008000f;
+	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[3] = CFG_DDR_CONFIG;
+	im->ddr.timing_cfg_1 =
+		3 << TIMING_CFG1_PRETOACT_SHIFT |
+		7 << TIMING_CFG1_ACTTOPRE_SHIFT |
+		3 << TIMING_CFG1_ACTTORW_SHIFT  |
+		4 << TIMING_CFG1_CASLAT_SHIFT   |
+		3 << TIMING_CFG1_REFREC_SHIFT   |
+		3 << TIMING_CFG1_WRREC_SHIFT    |
+		2 << TIMING_CFG1_ACTTOACT_SHIFT |
+		1 << TIMING_CFG1_WRTORD_SHIFT;
+	im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+	im->ddr.sdram_mode =
+		0x2000 << SDRAM_MODE_ESD_SHIFT |
+		0x0162 << SDRAM_MODE_SD_SHIFT;
+
+	im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
+		0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	puts("Board: Freescale MPC8349ADS\n");
+	return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxads_config_table[] = {
+	{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
+	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				    PCI_ENET0_MEMADDR,
+				    PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
+	} },
+	{}
+}
+#endif
+
+
+volatile static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc83xxads_config_table,
+#endif
+	},
+	{
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc83xxads_config_table,
+#endif
+	}
+};
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+	pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/*
+ * if MPC8349ADS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM)  \
+	&& defined(CFG_OR2_PRELIM) \
+	&& defined(CFG_LBLAWBAR2_PRELIM) \
+	&& defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile lbus8349_t *lbc= &immap->lbus;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/*setup mtrpt, lsrt and lbcr for LB bus*/
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
+
+	lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733;mode register write operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void
+sdram_init(void)
+{
+	put("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds
new file mode 100644
index 0000000..12c2d6f
--- /dev/null
+++ b/board/mpc8349ads/u-boot.lds
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c
index 01b0386..d0eb690 100644
--- a/board/mpc8540ads/mpc8540ads.c
+++ b/board/mpc8540ads/mpc8540ads.c
@@ -31,7 +31,7 @@
 #include <asm/immap_85xx.h>
 #include <spd.h>
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
@@ -96,7 +96,7 @@ initdram(int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */
diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds
index 56dd457..85852d5 100644
--- a/board/mpc8540ads/u-boot.lds
+++ b/board/mpc8540ads/u-boot.lds
@@ -70,7 +70,6 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile
new file mode 100644
index 0000000..6f1995e
--- /dev/null
+++ b/board/mpc8540eval/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+#OBJS	:= $(BOARD).o flash.o $(BOARD)_slave.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8540eval/config.mk b/board/mpc8540eval/config.mk
new file mode 100644
index 0000000..68271bd
--- /dev/null
+++ b/board/mpc8540eval/config.mk
@@ -0,0 +1,34 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# gda8540 board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+#TEXT_BASE = 0x1000000
+TEXT_BASE = 0xfff80000
+
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c
new file mode 100644
index 0000000..7300a04
--- /dev/null
+++ b/board/mpc8540eval/flash.c
@@ -0,0 +1,892 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*
+ * The variable should be in the flash info structure. Since it
+ * is only used in this board specific file it is declared here.
+ * In the future I think an endian flag should be part of the
+ * flash_info_t structure. (Ron Alder)
+ */
+static ulong big_endian = 0;
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt);
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(flash_info_t *info, vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	case FLASH_28F640J3A:   printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+ /* only deal with 16 bit and 32 bit port width, 16bit chip */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value,va,vb,vc,vd;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+#ifndef CFG_FLASH_CFI
+	printf("Not define CFG_FLASH_CFI\n");
+	return (0);
+#else
+	value = addr[0];
+	va=(value & 0xFF000000)>>24;
+	vb=(value & 0x00FF0000)>>16;
+	vc=(value & 0x0000FF00)>>8;
+	vd=(value & 0x000000FF);
+	if ((va==0) && (vb==0)) {
+		printf("cannot identify Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+	else if ((va==0) && (vb!=0)) {
+		big_endian = 1;
+		info->chipwidth = FLASH_CFI_BY16;
+		if(vb == vd) info->portwidth = FLASH_CFI_32BIT;
+		else info->portwidth = FLASH_CFI_16BIT;
+	}
+	else if ((va!=0) && (vb==0)) {
+		big_endian = 0;
+		info->chipwidth = FLASH_CFI_BY16;
+		if(va == vc) info->portwidth = FLASH_CFI_32BIT;
+		else info->portwidth = FLASH_CFI_16BIT;
+	}
+	else if ((va!=0) && (vb!=0)) {
+		big_endian = 1;		/* no meaning for 8bit chip */
+		info->chipwidth = FLASH_CFI_BY8;
+		if(va == vb) info->portwidth = FLASH_CFI_16BIT;
+		else info->portwidth = FLASH_CFI_8BIT;
+	}
+#ifdef DEBUG
+	switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			printf("port width is 8 bit.\n");
+			break;
+		case FLASH_CFI_16BIT:
+			printf("port width is 16 bit, ");
+			break;
+		case FLASH_CFI_32BIT:
+			printf("port width is 32 bit, ");
+			break;
+	}
+	switch (info->chipwidth) {
+		case FLASH_CFI_BY16:
+			printf("chip width is 16 bit, ");
+			switch (big_endian) {
+				case 0:
+					printf("Little Endian.\n");
+					break;
+				case 1:
+					printf("Big Endian.\n");
+					break;
+			}
+			break;
+	}
+#endif
+#endif		/*#ifdef CFG_FLASH_CFI*/
+
+	if (big_endian==0) value = (addr[0] & 0xFF000000) >>8;
+	else value = (addr[0] & 0x00FF0000);
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)(value>>16));
+#endif
+	switch (value) {
+	case MT_MANUFACT & 0xFFFF0000:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU & 0xFFFF0000:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	if (info->portwidth==FLASH_CFI_16BIT) {
+		switch (big_endian) {
+			case 0:
+				value = (addr[0] & 0x0000FF00)>>8;
+				break;
+			case 1:
+				value = (addr[0] & 0x000000FF);
+				break;
+		}
+	}
+	else if (info->portwidth == FLASH_CFI_32BIT) {
+		switch (big_endian) {
+			case 0:
+				value = (addr[1] & 0x0000FF00)>>8;
+				break;
+			case 1:
+				value = (addr[1] & 0x000000FF);
+				break;
+		}
+	}
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case (INTEL_ID_28F016S & 0x0000FFFF):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		sector_offset = 0x10000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F160S3 & 0x0000FFFF):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		sector_offset = 0x10000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F320S3 & 0x0000FFFF):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		sector_offset = 0x10000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F640J3A & 0x0000FFFF):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		sector_offset = 0x20000;
+		break;                          /* => 8 MB             */
+
+	case SHARP_ID_28F016SCL & 0x0000FFFF:
+	case SHARP_ID_28F016SCZ & 0x0000FFFF:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		sector_offset = 0x10000;
+		break;				/* => 2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	sector_offset = sector_offset * (info->portwidth / info->chipwidth);
+	info->size = info->sector_count * sector_offset;
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last, ready, erase_err_status;
+
+	if (big_endian == 1) {
+		ready = 0x0080;
+		erase_err_status = 0x00a0;
+	}
+	else {
+		ready = 0x8000;
+		erase_err_status = 0xa000;
+	}
+	if ((info->portwidth / info->chipwidth)==2) {
+		ready += (ready <<16);
+		erase_err_status += (erase_err_status <<16);
+	}
+
+#ifdef DEBUG
+	printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr16 = (vu_short *)(info->start[sect]);
+			vu_long *addr   = (vu_long *)(info->start[sect]);
+			printf(".");
+			switch (info->portwidth) {
+				case FLASH_CFI_16BIT:
+					asm("sync");
+					last = start = get_timer (0);
+					/* Disable interrupts which might cause a timeout here */
+					flag = disable_interrupts();
+					/* Reset Array */
+					*addr16 = 0xffff;
+					asm("sync");
+					/* Clear Status Register */
+					*addr16 = 0x5050;
+					asm("sync");
+					/* Single Block Erase Command */
+					*addr16 = 0x2020;
+					asm("sync");
+					/* Confirm */
+					*addr16 = 0xD0D0;
+					asm("sync");
+					if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+					    /* Resume Command, as per errata update */
+					    *addr16 = 0xD0D0;
+					    asm("sync");
+					}
+					/* re-enable interrupts if necessary */
+					if (flag)
+						enable_interrupts();
+					/* wait at least 80us - let's wait 1 ms */
+					*addr16 = 0x7070;
+					udelay (1000);
+					while ((*addr16 & ready) != ready) {
+						if((*addr16 & erase_err_status)== erase_err_status){
+							printf("Error in Block Erase - Lock Bit may be set!\n");
+							printf("Status Register = 0x%X\n", (uint)*addr16);
+							*addr16 = 0xFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+							printf ("Timeout\n");
+							*addr16 = 0xFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						/* show that we're waiting */
+						if ((now - last) > 1000) {	/* every second */
+							putc ('.');
+							last = now;
+						}
+					}
+					/* reset to read mode */
+					*addr16 = 0xFFFF;
+					asm("sync");
+					break;
+				case FLASH_CFI_32BIT:
+					asm("sync");
+					last = start = get_timer (0);
+					/* Disable interrupts which might cause a timeout here */
+					flag = disable_interrupts();
+					/* Reset Array */
+					*addr = 0xffffffff;
+					asm("sync");
+					/* Clear Status Register */
+					*addr = 0x50505050;
+					asm("sync");
+					/* Single Block Erase Command */
+					*addr = 0x20202020;
+					asm("sync");
+					/* Confirm */
+					*addr = 0xD0D0D0D0;
+					asm("sync");
+					if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+					    /* Resume Command, as per errata update */
+					    *addr = 0xD0D0D0D0;
+					    asm("sync");
+					}
+					/* re-enable interrupts if necessary */
+					if (flag)
+						enable_interrupts();
+					/* wait at least 80us - let's wait 1 ms */
+					*addr = 0x70707070;
+					udelay (1000);
+					while ((*addr & ready) != ready) {
+						if((*addr & erase_err_status)==erase_err_status){
+							printf("Error in Block Erase - Lock Bit may be set!\n");
+							printf("Status Register = 0x%X\n", (uint)*addr);
+							*addr = 0xFFFFFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+							printf ("Timeout\n");
+							*addr = 0xFFFFFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						/* show that we're waiting */
+						if ((now - last) > 1000) {	/* every second */
+							putc ('.');
+							last = now;
+						}
+					}
+					/* reset to read mode */
+					*addr = 0xFFFFFFFF;
+					asm("sync");
+					break;
+			}	/* end switch */
+		}		/* end if */
+	}			/* end for */
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+#define FLASH_BLOCK_SIZE 32
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data, count, temp;
+/*	ulong temp[FLASH_BLOCK_SIZE/4];*/
+	int i, l, rc;
+
+	count = cnt;
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	cp = wp;
+	/* handle unaligned block bytes , flash block size = 16bytes */
+	wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1);
+	if ((wp-cp)>=cnt) {
+		if ((rc = write_block(info,src,cp,wp-cp)) !=0)
+			return (rc);
+		src += wp-cp;
+		cnt -= wp-cp;
+	}
+	/* handle aligned block bytes */
+	temp = 0;
+	printf("\n");
+	while ( cnt >= FLASH_BLOCK_SIZE) {
+		if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) {
+			return (rc);
+		}
+		src += FLASH_BLOCK_SIZE;
+		cp += FLASH_BLOCK_SIZE;
+		cnt -= FLASH_BLOCK_SIZE;
+		if (((count-cnt)>>10)>temp) {
+			temp=(count-cnt)>>10;
+			printf("\r%d KB",temp);
+		}
+	}
+	printf("\n");
+	wp = cp;
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+#undef FLASH_BLOCK_SIZE
+
+/*-----------------------------------------------------------------------
+ * Write block to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * -1  Error
+ */
+static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt)
+{
+	vu_short *baddr, *addr = (vu_short *)dest;
+	ushort data;
+	ulong start, now, xsr,csr, ready;
+	int flag;
+
+	if (cnt==0) return 0;
+	else if(cnt != (cnt& ~1)) return -1;
+
+	/* Check if Flash is (sufficiently) erased */
+	data = * src;
+	data = (data<<8) | *(src+1);
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	if (big_endian == 1) {
+		ready = 0x0080;
+	}
+	else {
+		ready = 0x8000;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+		do {
+			/* Write Command */
+			*addr = 0xe8e8;
+			asm("sync");
+			xsr = *addr;
+			asm("sync");
+		} while (!(xsr & ready));	/*wait until read */
+		/*write count=BLOCK SIZE -1 */
+		data=(cnt>>1)-1;
+		data=(data<<8)|data;
+		*addr = data;		/* word mode, cnt/2 */
+		asm("sync");
+		baddr = addr;
+		while(cnt) {
+			data = * src++;
+			data = (data<<8) | *src++;
+			asm("sync");
+			*baddr = data;
+			asm("sync");
+			++baddr;
+			cnt = cnt -2;
+		}
+		*addr = 0xd0d0;			/* confirm write */
+		start = get_timer(0);
+		asm("sync");
+		if (flag)
+			enable_interrupts();
+		/* data polling for D7 */
+		flag  = 0;
+		while (((csr = *addr) & ready) != ready) {
+			if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+		}
+		if (csr & 0x4040) {
+			printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr);
+			flag = 1;
+		}
+		/* Clear Status Registers Command */
+		*addr = 0x5050;
+		asm("sync");
+		/* Reset to read array mode */
+		*addr = 0xFFFF;
+		asm("sync");
+	return (flag);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a short word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *)dest;
+	ulong start, now, csr, ready;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+		/* Write Command */
+		*addr = 0x1010;
+		start = get_timer (0);
+		asm("sync");
+		/* Write Data */
+		*addr = data;
+		asm("sync");
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+		if (big_endian == 1) {
+			ready = 0x0080;
+		}
+		else {
+			ready = 0x8000;
+		}
+		/* data polling for D7 */
+		flag  = 0;
+		while (((csr = *addr) & ready) != ready) {
+			if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+		}
+		if (csr & 0x4040) {
+			printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr);
+			flag = 1;
+		}
+		/* Clear Status Registers Command */
+		*addr = 0x5050;
+		asm("sync");
+		/* Reset to read array mode */
+		*addr = 0xFFFF;
+		asm("sync");
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr, ready;
+	int flag=0;
+
+	switch (info->portwidth) {
+	case FLASH_CFI_32BIT:
+		/* Check if Flash is (sufficiently) erased */
+		if ((*addr & data) != data) {
+			return (2);
+		}
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		if (big_endian == 1) {
+			ready = 0x0080;
+		}
+		else {
+			ready = 0x8000;
+		}
+		if ((info->portwidth / info->chipwidth)==2) {
+			ready += (ready <<16);
+		}
+		else {
+			ready = ready << 16;
+		}
+		/* Write Command */
+		*addr = 0x10101010;
+		asm("sync");
+		/* Write Data */
+		*addr = data;
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+		/* data polling for D7 */
+		start = get_timer (0);
+		flag  = 0;
+		while (((csr = *addr) & ready) != ready) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+		}
+		if (csr & 0x40404040) {
+			printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+			flag = 1;
+		}
+		/* Clear Status Registers Command */
+		*addr = 0x50505050;
+		asm("sync");
+		/* Reset to read array mode */
+		*addr = 0xFFFFFFFF;
+		asm("sync");
+		break;
+	case FLASH_CFI_16BIT:
+		flag = write_short (info, dest,  (unsigned short) (data>>16));
+		if (flag == 0)
+			flag = write_short (info, dest+2,  (unsigned short) (data));
+		break;
+	}
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(flash_info_t * info, vu_long  * addr)
+{
+	ulong start, now, ready;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+
+	if (big_endian == 1) {
+		ready = 0x0080;
+	}
+	else {
+		ready = 0x8000;
+	}
+	if ((info->portwidth / info->chipwidth)==2) {
+		ready += (ready <<16);
+	}
+	else {
+		ready = ready << 16;
+	}
+#ifdef DEBUG
+	printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready);
+#endif
+	*addr = 0x70707070;	/* read status */
+	start = get_timer (0);
+	while((*addr & ready) != ready){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S
new file mode 100644
index 0000000..8c2ca65
--- /dev/null
+++ b/board/mpc8540eval/init.S
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if defined(CFG_FLASH_PORT_WIDTH_16)
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+  #if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+  #if defined(CONFIG_RAM_AS_FLASH)
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+  #else
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+  #ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+  #else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,8,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,9,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+	entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
new file mode 100644
index 0000000..3b3c8ed
--- /dev/null
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+extern long int spd_sdram (void);
+
+long int fixed_sdram (void);
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+	pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Freescale MPC8540EVAL Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n",
+			sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if defined(CFG_RAMBOOT)
+	return dram_size;
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+#if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+#endif
+	asm("sync;isync;msync");
+	udelay(500);
+#if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+#else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+#endif
+	asm("sync; isync; msync");
+	udelay(500);
+#endif
+	return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds
new file mode 100644
index 0000000..2479af1
--- /dev/null
+++ b/board/mpc8540eval/u-boot.lds
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Assumes that the size of u-boot is less than 512K and the
+ * start address is aligned on a 512K block.
+ * Boot page and reset vector is put at that end of the 512K block. */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8540eval/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+
+  . = (. & 0xFFF80000) + 0x0007F000;
+  .bootpg   :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8540eval/init.o (.bootpg)
+  } = 0xffff
+
+  . = (. & 0xFFF80000) + 0x0007FFFC;
+  .resetvec  :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+}
diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk
index 53e3edb..9aef2bb 100644
--- a/board/mpc8560ads/config.mk
+++ b/board/mpc8560ads/config.mk
@@ -29,5 +29,4 @@
 TEXT_BASE = 0xfff80000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
 PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c
index 1990e54..9accc5c 100644
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -33,7 +33,7 @@
 #include <spd.h>
 #include <miiphy.h>
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
@@ -293,7 +293,7 @@ initdram(int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */
diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds
index 4c6c7db..c307d63 100644
--- a/board/mpc8560ads/u-boot.lds
+++ b/board/mpc8560ads/u-boot.lds
@@ -73,7 +73,6 @@ SECTIONS
     cpu/mpc85xx/ether_fcc.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/i2c.o (.text)
     cpu/mpc85xx/spd_sdram.o (.text)
diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds
index 5f24f76..4db6b34 100644
--- a/board/pm854/u-boot.lds
+++ b/board/pm854/u-boot.lds
@@ -70,7 +70,6 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
diff --git a/board/sbc8560/config.mk b/board/sbc8560/config.mk
index 3c8cfbe..6d9ae45 100644
--- a/board/sbc8560/config.mk
+++ b/board/sbc8560/config.mk
@@ -30,5 +30,4 @@
 TEXT_BASE = 0xfffc0000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
 PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/stxgp3/config.mk b/board/stxgp3/config.mk
index 14c1f01..2427818 100644
--- a/board/stxgp3/config.mk
+++ b/board/stxgp3/config.mk
@@ -29,5 +29,4 @@
 TEXT_BASE = 0xfff80000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
 PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds
index 5879946..dae5acb 100644
--- a/board/stxgp3/u-boot.lds
+++ b/board/stxgp3/u-boot.lds
@@ -78,7 +78,6 @@ SECTIONS
     cpu/mpc85xx/ether_fcc.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/i2c.o (.text)
     cpu/mpc85xx/spd_sdram.o (.text)
diff --git a/board/tqm8540/u-boot.lds b/board/tqm8540/u-boot.lds
index eb84aeb..ffd7562 100644
--- a/board/tqm8540/u-boot.lds
+++ b/board/tqm8540/u-boot.lds
@@ -70,7 +70,6 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
diff --git a/board/tqm8560/u-boot.lds b/board/tqm8560/u-boot.lds
index 19b77be..ebe2240 100644
--- a/board/tqm8560/u-boot.lds
+++ b/board/tqm8560/u-boot.lds
@@ -70,7 +70,6 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6f29e2f..4914ac5 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -70,13 +70,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_str ("pci_busfreq",   strmhz(buf, bd->bi_pci_busfreq));
 #endif
 #else	/* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	print_str ("vco",	    strmhz(buf, bd->bi_vco));
 	print_str ("sccfreq",	    strmhz(buf, bd->bi_sccfreq));
 	print_str ("brgfreq",	    strmhz(buf, bd->bi_brgfreq));
 #endif
 	print_str ("intfreq",	    strmhz(buf, bd->bi_intfreq));
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	print_str ("cpmfreq",	    strmhz(buf, bd->bi_cpmfreq));
 #endif
 	print_str ("busfreq",	    strmhz(buf, bd->bi_busfreq));
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index a90735f..c200fd8 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -580,12 +580,12 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 	kbd->bi_flbfreq /= 1000000L;
 	kbd->bi_vcofreq /= 1000000L;
 #endif
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 		kbd->bi_cpmfreq /= 1000000L;
 		kbd->bi_brgfreq /= 1000000L;
 		kbd->bi_sccfreq /= 1000000L;
 		kbd->bi_vco     /= 1000000L;
-#endif /* CONFIG_8260 */
+#endif
 #if defined(CONFIG_MPC5xxx)
 		kbd->bi_ipbfreq /= 1000000L;
 		kbd->bi_pcifreq /= 1000000L;
diff --git a/config.mk b/config.mk
index 75bbac5..ff83091 100644
--- a/config.mk
+++ b/config.mk
@@ -161,6 +161,10 @@ BFD_ROOT_DIR =		/opt/powerpc
 endif
 endif
 
+ifeq ($(PCI_CLOCK),PCI_66M)
+CFLAGS := $(CFLAGS) -DPCI_66M
+endif
+
 #########################################################################
 
 export	CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \
diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk
index 3b28924..dd7a71f 100644
--- a/cpu/mpc8260/config.mk
+++ b/cpu/mpc8260/config.mk
@@ -23,5 +23,5 @@
 
 PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -ffixed-r2 -ffixed-r29 \
+PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \
 		     -mstring -mcpu=603e -mmultiple
diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
new file mode 100644
index 0000000..14574f4
--- /dev/null
+++ b/cpu/mpc83xx/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o \
+	resetvec.o
+
+COBJS	= traps.o \
+	  cpu.o \
+	  cpu_init.o \
+	  speed.o \
+	  interrupts.o \
+	  pci.o \
+	  i2c.o \
+	  spd_sdram.o
+
+OBJS	= $(COBJS)
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk
new file mode 100644
index 0000000..8b4ff92
--- /dev/null
+++ b/cpu/mpc83xx/config.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
+			-ffixed-r2 -ffixed-r29 -msoft-float
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
new file mode 100644
index 0000000..c84aeb4
--- /dev/null
+++ b/cpu/mpc83xx/cpu.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *	     Initial file creating (porting from 85XX & 8260)
+ */
+
+/*
+ * CPU specific code for the MPC83xx family.
+ *
+ * Derived from the MPC8260 and MPC85xx.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc83xx.h>
+#include <asm/processor.h>
+
+
+int checkcpu(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong clock = gd->cpu_clk;
+	u32 pvr = get_pvr();
+	char buf[32];
+
+	if ((pvr & 0xFFFF0000) != PVR_83xx) {
+		puts("Not MPC83xx Family!!!\n");
+		return -1;
+	}
+
+	puts("CPU: MPC83xx, ");
+	switch(pvr) {
+	case PVR_8349_REV10:
+		break;
+	case PVR_8349_REV11:
+		break;
+	default:
+		puts("Rev: Unknown\n");
+		return -1;	/* Not sure what this is */
+	}
+	printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock));
+	return 0;
+}
+
+
+void upmconfig (uint upm, uint *table, uint size)
+{
+	hang();		/* FIXME: upconfig() needed? */
+}
+
+
+int
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong msr;
+#ifndef MPC83xx_RESET
+	ulong addr;
+#endif
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+
+#ifdef MPC83xx_RESET
+	/* Interrupts and MMU off */
+	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
+
+	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
+	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+
+	/* enable Reset Control Reg */
+	immap->reset.rpr = 0x52535445;
+
+	/* confirm Reset Control Reg is enabled */
+	while(!((immap->reset.rcer) & RCER_CRE));
+
+	printf("Resetting the board.");
+	printf("\n");
+
+	udelay(200);
+
+	/* perform reset, only one bit */
+	immap->reset.rcr = RCR_SWHR;
+
+#else	/* ! MPC83xx_RESET */
+
+	immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
+
+	/* Interrupts and MMU off */
+	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
+
+	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
+	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+
+	/*
+	 * Trying to execute the next instruction at a non-existing address
+	 * should cause a machine check, resulting in reset
+	 */
+	addr = CFG_RESET_ADDRESS;
+
+	printf("resetting the board.");
+	printf("\n");
+	((void (*)(void)) addr) ();
+#endif	/* MPC83xx_RESET */
+
+	return 1;
+}
+
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ */
+
+unsigned long get_tbclk(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	ulong tbclk;
+
+	tbclk = (gd->bus_clk + 3L) / 4L;
+
+	return tbclk;
+}
+
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+	hang();		/* FIXME: implement watchdog_reset()? */
+}
+#endif /* CONFIG_WATCHDOG */
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
new file mode 100644
index 0000000..dcb3445
--- /dev/null
+++ b/cpu/mpc83xx/cpu_init.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <ioports.h>
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f (volatile immap_t * im)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	memset ((void *) gd, 0, sizeof (gd_t));
+
+	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
+	gd->reset_status = im->reset.rsr;
+	im->reset.rsr = ~(RSR_RES);
+
+	/*
+	 * RMR - Reset Mode Register
+	 * contains checkstop reset enable (4.6.1.4)
+	 */
+	im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
+
+	/* LCRR - Clock Ratio Register (10.3.1.16) */
+	im->lbus.lcrr = CFG_LCRR;
+
+	/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
+	im->sysconf.spcr |= SPCR_TBEN;
+
+	/* System General Purpose Register */
+	im->sysconf.sicrh = SICRH_TSOBI1;
+	im->sysconf.sicrl = SICRL_LDP_A;
+
+	/*
+	 * Memory Controller:
+	 */
+
+	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+	 * addresses - these have to be modified later when FLASH size
+	 * has been determined
+	 */
+
+#if defined(CFG_BR0_PRELIM)  \
+	&& defined(CFG_OR0_PRELIM) \
+	&& defined(CFG_LBLAWBAR0_PRELIM) \
+	&& defined(CFG_LBLAWAR0_PRELIM)
+	im->lbus.bank[0].br = CFG_BR0_PRELIM;
+	im->lbus.bank[0].or = CFG_OR0_PRELIM;
+	im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
+	im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
+#else
+#error 	CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
+#endif
+
+#if defined(CFG_BR1_PRELIM)  \
+	&& defined(CFG_OR1_PRELIM) \
+	&& defined(CFG_LBLAWBAR1_PRELIM) \
+	&& defined(CFG_LBLAWAR1_PRELIM)
+	im->lbus.bank[1].br = CFG_BR1_PRELIM;
+	im->lbus.bank[1].or = CFG_OR1_PRELIM;
+	im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
+	im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
+#endif
+#if defined(CFG_BR2_PRELIM)  \
+	&& defined(CFG_OR2_PRELIM) \
+	&& defined(CFG_LBLAWBAR2_PRELIM) \
+	&& defined(CFG_LBLAWAR2_PRELIM)
+	im->lbus.bank[2].br = CFG_BR2_PRELIM;
+	im->lbus.bank[2].or = CFG_OR2_PRELIM;
+	im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
+	im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
+#endif
+#if defined(CFG_BR3_PRELIM)  \
+	&& defined(CFG_OR3_PRELIM) \
+	&& defined(CFG_LBLAWBAR3_PRELIM) \
+	&& defined(CFG_LBLAWAR3_PRELIM)
+	im->lbus.bank[3].br = CFG_BR3_PRELIM;
+	im->lbus.bank[3].or = CFG_OR3_PRELIM;
+	im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
+	im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
+#endif
+#if defined(CFG_BR4_PRELIM)  \
+	&& defined(CFG_OR4_PRELIM) \
+	&& defined(CFG_LBLAWBAR4_PRELIM) \
+	&& defined(CFG_LBLAWAR4_PRELIM)
+	im->lbus.bank[4].br = CFG_BR4_PRELIM;
+	im->lbus.bank[4].or = CFG_OR4_PRELIM;
+	im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
+	im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
+#endif
+#if defined(CFG_BR5_PRELIM)  \
+	&& defined(CFG_OR5_PRELIM) \
+	&& defined(CFG_LBLAWBAR5_PRELIM) \
+	&& defined(CFG_LBLAWAR5_PRELIM)
+	im->lbus.bank[5].br = CFG_BR5_PRELIM;
+	im->lbus.bank[5].or = CFG_OR5_PRELIM;
+	im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
+	im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
+#endif
+#if defined(CFG_BR6_PRELIM)  \
+	&& defined(CFG_OR6_PRELIM) \
+	&& defined(CFG_LBLAWBAR6_PRELIM) \
+	&& defined(CFG_LBLAWAR6_PRELIM)
+	im->lbus.bank[6].br = CFG_BR6_PRELIM;
+	im->lbus.bank[6].or = CFG_OR6_PRELIM;
+	im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
+	im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
+#endif
+#if defined(CFG_BR7_PRELIM)  \
+	&& defined(CFG_OR7_PRELIM) \
+	&& defined(CFG_LBLAWBAR7_PRELIM) \
+	&& defined(CFG_LBLAWAR7_PRELIM)
+	im->lbus.bank[7].br = CFG_BR7_PRELIM;
+	im->lbus.bank[7].or = CFG_OR7_PRELIM;
+	im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
+	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
+#endif
+}
+
+
+/*
+ * Initialize higher level parts of CPU like time base and timers.
+ */
+
+int cpu_init_r (void)
+{
+	return 0;
+}
diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c
new file mode 100644
index 0000000..3db7d2c
--- /dev/null
+++ b/cpu/mpc83xx/i2c.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao <x.xiao@motorola.com>
+ * Adapted for Motorola 85xx chip.
+ *
+ * (C) Copyright 2003
+ * Gleb Natapov <gnatapov@mrv.com>
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
+ *
+ * Hardware I2C driver for MPC107 PCI bridge.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_HARD_I2C
+#include <i2c.h>
+#include <asm/i2c.h>
+
+#ifdef CONFIG_MPC8349ADS
+i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
+#endif
+
+void
+i2c_init(int speed, int slaveadd)
+{
+	/* stop I2C controller */
+	writeb(0x00 , &I2C->cr);
+
+	/* set clock */
+	writeb(0x3f, &I2C->fdr);
+
+	/* set default filter */
+	writeb(0x10,&I2C->dfsrr);
+
+	/* write slave address */
+	writeb(slaveadd, &I2C->adr);
+
+	/* clear status register */
+	writeb(0x00, &I2C->sr);
+
+	/* start I2C controller */
+	writeb(I2C_CR_MEN, &I2C->cr);
+}
+
+static __inline__ int
+i2c_wait4bus (void)
+{
+	ulong timeval = get_timer (0);
+	while (readb(&I2C->sr) & I2C_SR_MBB) {
+		if (get_timer (timeval) > I2C_TIMEOUT) {
+			return -1;
+		}
+	}
+	return 0;
+}
+
+static __inline__ int
+i2c_wait (int write)
+{
+	u32 csr;
+	ulong timeval = get_timer(0);
+	do {
+		csr = readb(&I2C->sr);
+
+		if (!(csr & I2C_SR_MIF))
+			continue;
+
+		writeb(0x0, &I2C->sr);
+
+		if (csr & I2C_SR_MAL) {
+			debug("i2c_wait: MAL\n");
+			return -1;
+		}
+
+		if (!(csr & I2C_SR_MCF))	{
+			debug("i2c_wait: unfinished\n");
+			return -1;
+		}
+
+		if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
+			debug("i2c_wait: No RXACK\n");
+			return -1;
+		}
+
+		return 0;
+	} while (get_timer (timeval) < I2C_TIMEOUT);
+	debug("i2c_wait: timed out\n");
+}
+
+static __inline__ int
+i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
+	       (rsta?I2C_CR_RSTA:0),
+	       &I2C->cr);
+
+	writeb((dev << 1) | dir, &I2C->dr);
+
+	if (i2c_wait (I2C_WRITE) < 0)
+		return 0;
+	return 1;
+}
+
+static __inline__ int
+__i2c_write (u8 *data, int length)
+{
+	int i;
+
+	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
+	       &I2C->cr);
+
+	for (i=0; i < length; i++) {
+		writeb(data[i], &I2C->dr);
+
+		if (i2c_wait (I2C_WRITE) < 0)
+			break;
+	}
+	return i;
+}
+
+static __inline__ int
+__i2c_read (u8 *data, int length)
+{
+	int i;
+
+	writeb(I2C_CR_MEN | I2C_CR_MSTA |
+	       ((length == 1) ? I2C_CR_TXAK : 0),
+	       &I2C->cr);
+
+	/* dummy read */
+	readb(&I2C->dr);
+
+	for (i=0; i < length; i++) {
+		if (i2c_wait (I2C_READ) < 0)
+			break;
+
+		/* Generate ack on last next to last byte */
+		if (i == length - 2)
+			writeb(I2C_CR_MEN | I2C_CR_MSTA |
+			       I2C_CR_TXAK,
+			       &I2C->cr);
+
+		/* Generate stop on last byte */
+		if (i == length - 1)
+			writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+
+		data[i] = readb(&I2C->dr);
+	}
+	return i;
+}
+
+int
+i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+	int i = 0;
+	u8 *a = (u8*)&addr;
+
+	if (i2c_wait4bus () < 0)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+		goto exit;
+
+	if (__i2c_write (&a[4 - alen], alen) != alen)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_READ, 1) == 0)
+		goto exit;
+
+	i = __i2c_read (data, length);
+
+ exit:
+	writeb(I2C_CR_MEN, &I2C->cr);
+	return !(i == length);
+}
+
+int
+i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+	int i = 0;
+	u8 *a = (u8*)&addr;
+
+	if (i2c_wait4bus () < 0)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+		goto exit;
+
+	if (__i2c_write (&a[4 - alen], alen) != alen)
+		goto exit;
+
+	i = __i2c_write (data, length);
+
+ exit:
+	writeb(I2C_CR_MEN, &I2C->cr);
+	return !(i == length);
+}
+
+int i2c_probe (uchar chip)
+{
+	int tmp;
+
+	/*
+	 * Try to read the first location of the chip.  The underlying
+	 * driver doesn't appear to support sending just the chip address
+	 * and looking for an <ACK> back.
+	 */
+	udelay(10000);
+	return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+}
+
+uchar i2c_reg_read (uchar i2c_addr, uchar reg)
+{
+	char buf[1];
+
+	i2c_read (i2c_addr, reg, 1, buf, 1);
+
+	return (buf[0]);
+}
+
+void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write (i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
new file mode 100644
index 0000000..53474f6
--- /dev/null
+++ b/cpu/mpc83xx/interrupts.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc83xx.h>
+#include <asm/processor.h>
+
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	ulong count;
+};
+
+int interrupt_init_cpu (unsigned *decrementer_count)
+{
+	return 0;
+}
+
+
+/*
+ * Handle external interrupts
+ */
+
+void external_interrupt (struct pt_regs *regs)
+{
+}
+
+
+/*
+ * Install and free an interrupt handler.
+ */
+
+void
+irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
+{
+}
+
+
+void irq_free_handler (int irq)
+{
+}
+
+
+void timer_interrupt_cpu (struct pt_regs *regs)
+{
+	/* nothing to do here */
+	return;
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+
+/* ripped this out of ppc4xx/interrupts.c */
+
+/*
+ * irqinfo - print information about PCI devices
+ */
+
+void
+do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+}
+
+#endif		/* CONFIG_COMMANDS & CFG_CMD_IRQ */
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
new file mode 100644
index 0000000..d5fa811
--- /dev/null
+++ b/cpu/mpc83xx/pci.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+/*
+ * PCI Configuration space access support for MPC85xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_MPC8349ADS
+#include <asm/i2c.h>
+#endif
+
+#if defined(CONFIG_PCI)
+
+void
+pci_mpc83xx_init(volatile struct pci_controller *hose)
+{
+	volatile immap_t *	immr;
+	volatile clk8349_t *	clk;
+	volatile law8349_t *	pci_law;
+	volatile pot8349_t *	pci_pot;
+	volatile pcictrl8349_t *	pci_ctrl;
+	volatile pciconf8349_t *	pci_conf;
+
+	u8 val8,tmp8,ret;
+	u16 reg16,tmp16;
+	u32 val32,tmp32;
+
+	immr = (immap_t *)CFG_IMMRBAR;
+	clk = (clk8349_t *)&immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+	 */
+	val32 = clk->occr;
+	udelay(2000);
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
+
+	/* mapped to PCI1 IO space 0x0 to local 0xe2000000  */
+	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
+
+	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
+
+	/* mapped to PCI2 IO space 0x0 to local 0xe3000000  */
+	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
+
+	pci_ctrl[1].pitar1 = 0x0;
+	pci_ctrl[1].pibar1 = 0x0;
+	pci_ctrl[1].piebar1 = 0x0;
+	pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
+	/*
+	 * Assign PIB PMC slot to desired PCI bus
+	 */
+#ifdef CONFIG_MPC8349ADS
+	mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
+	i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
+#endif
+	val8 = 0;
+	ret = i2c_write(0x23,0x6,1,&val8,1);
+	ret = i2c_write(0x23,0x7,1,&val8,1);
+	val8 = 0xff;
+	ret = i2c_write(0x23,0x2,1,&val8,1);
+	ret = i2c_write(0x23,0x3,1,&val8,1);
+
+	val8 = 0;
+	ret = i2c_write(0x26,0x6,1,&val8,1);
+	val8 = 0x34;
+	ret = i2c_write(0x26,0x7,1,&val8,1);
+#if defined(PCI_64BIT)
+	val8 = 0xf4;	/* PMC2<->PCI1  64bit */
+#elif defined(PCI_ALL_PCI1)
+	val8 = 0xf3;	/* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1  32bit */
+#elif defined(PCI_ONE_PCI1)
+	val8 = 0xf9;	/* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2  32bit */
+#elif defined(PCI_TWO_PCI1)
+	val8 = 0xf5;	/* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
+#else
+	val8 = 0xf5;
+#endif
+	ret = i2c_write(0x26,0x2,1,&val8,1);
+	val8 = 0xff;
+	ret = i2c_write(0x26,0x3,1,&val8,1);
+	val8 = 0;
+	ret = i2c_write(0x27,0x6,1,&val8,1);
+	ret = i2c_write(0x27,0x7,1,&val8,1);
+	val8 = 0xff;
+	ret = i2c_write(0x27,0x2,1,&val8,1);
+	val8 = 0xef;
+	ret = i2c_write(0x27,0x3,1,&val8,1);
+	asm("eieio");
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+#ifndef PCI_64BIT
+	pci_ctrl[1].gcr = 1;
+#endif
+	udelay(2000);
+
+	hose[0].first_busno = 0;
+	hose[0].last_busno = 0xff;
+
+	pci_set_region(hose[0].regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	pci_set_region(hose[0].regions + 1,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS,
+		       CFG_PCI1_IO_SIZE,
+		       PCI_REGION_IO);
+
+	hose[0].region_count = 2;
+
+	pci_setup_indirect(&hose[0],
+			   (CFG_IMMRBAR+0x8300),
+			   (CFG_IMMRBAR+0x8304));
+#define PCI_CLASS_BRIDGE	0x06
+	reg16 = 0xff;
+	tmp32 = 0xffff;
+	pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
+
+	pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+#ifndef PCI_64BIT
+	hose[1].first_busno = 0;
+	hose[1].last_busno = 0xff;
+
+	pci_set_region(hose[1].regions + 0,
+		       CFG_PCI2_MEM_BASE,
+		       CFG_PCI2_MEM_PHYS,
+		       CFG_PCI2_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	pci_set_region(hose[1].regions + 1,
+		       CFG_PCI2_IO_BASE,
+		       CFG_PCI2_IO_PHYS,
+		       CFG_PCI2_IO_SIZE,
+		       PCI_REGION_IO);
+
+	hose[1].region_count = 2;
+
+	pci_setup_indirect(&hose[1],
+			   (CFG_IMMRBAR+0x8380),
+			   (CFG_IMMRBAR+0x8384));
+
+	pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
+	pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+#endif
+
+#if defined(PCI_64BIT)
+	printf("PCI1 64bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+	printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+	printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
+#else
+	printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
+#endif
+
+#if 1
+	/*
+	 * Hose scan.
+	 */
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+#endif
+}
+
+#endif /* CONFIG_PCI */
diff --git a/cpu/mpc83xx/resetvec.S b/cpu/mpc83xx/resetvec.S
new file mode 100644
index 0000000..3dfcd0d
--- /dev/null
+++ b/cpu/mpc83xx/resetvec.S
@@ -0,0 +1,6 @@
+	.section .resetvec,"ax"
+#ifndef FIXME
+#if 0
+	b _start_e500
+#endif
+#endif
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
new file mode 100644
index 0000000..63dcd66
--- /dev/null
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+
+#ifdef CONFIG_SPD_EEPROM
+
+#if defined(CONFIG_DDR_ECC)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+#endif
+
+#ifndef	CFG_READ_SPD
+#define CFG_READ_SPD	i2c_read
+#endif
+
+/*
+ * Convert picoseconds into clock cycles (rounding up if needed).
+ */
+
+int
+picos_to_clk(int picos)
+{
+	int clks;
+
+	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
+	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+	clks++;
+	}
+
+	return clks;
+}
+
+unsigned int
+banksize(unsigned char row_dens)
+{
+	return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+}
+
+long int spd_sdram(int(read_spd)(uint addr))
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile ddr8349_t *ddr = &immap->ddr;
+	volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
+	spd_eeprom_t spd;
+	unsigned tmp, tmp1;
+	unsigned int memsize;
+	unsigned int law_size;
+	unsigned char caslat;
+	unsigned int trfc, trfc_clk, trfc_low;
+
+#warning Current spd_sdram does not fit its usage... adjust implementation or API...
+
+	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+
+	if (spd.nrows > 2) {
+		puts("DDR:Only two chip selects are supported on ADS.\n");
+		return 0;
+	}
+
+	if (spd.nrow_addr < 12
+	    || spd.nrow_addr > 14
+	    || spd.ncol_addr < 8
+	    || spd.ncol_addr > 11) {
+		puts("DDR:Row or Col number unsupported.\n");
+		return 0;
+	}
+
+	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+	ddr->cs_config[2] = ( 1 << 31
+			    | (spd.nrow_addr - 12) << 8
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
+	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
+
+	if (spd.nrows == 2) {
+		ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
+				  | ((banksize(spd.row_dens) >> 23) - 1) );
+		ddr->cs_config[3] = ( 1<<31
+				    | (spd.nrow_addr-12) << 8
+				    | (spd.ncol_addr-8) );
+		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
+		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
+	}
+
+	if (spd.mem_type != 0x07) {
+		puts("No DDR module found!\n");
+		return 0;
+	}
+
+	/*
+	 * Figure out memory size in Megabytes.
+	 */
+	memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
+
+	/*
+	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
+	 */
+	law_size = 19 + __ilog2(memsize);
+
+	/*
+	 * Set up LAWBAR for all of DDR.
+	 */
+	ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
+	debug("DDR:bar=0x%08x\n", ecm->bar);
+	debug("DDR:ar=0x%08x\n", ecm->ar);
+
+	/*
+	 * find the largest CAS
+	 */
+	if(spd.cas_lat & 0x40) {
+		caslat = 7;
+	} else if (spd.cas_lat & 0x20) {
+		caslat = 6;
+	} else if (spd.cas_lat & 0x10) {
+		caslat = 5;
+	} else if (spd.cas_lat & 0x08) {
+		caslat = 4;
+	} else if (spd.cas_lat & 0x04) {
+		caslat = 3;
+	} else if (spd.cas_lat & 0x02) {
+		caslat = 2;
+	} else if (spd.cas_lat & 0x01) {
+		caslat = 1;
+	} else {
+		puts("DDR:no valid CAS Latency information.\n");
+		return 0;
+	}
+
+	tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+		       + (spd.clk_cycle & 0x0f));
+	debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
+
+	tmp1 = get_bus_freq(0) / 1000000;
+	if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
+		/* 90~230 range, treated as DDR 200 */
+		if (spd.clk_cycle3 == 0xa0)
+			caslat -= 2;
+		else if(spd.clk_cycle2 == 0xa0)
+			caslat--;
+	} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
+		/* 230-280 range, treated as DDR 266 */
+		if (spd.clk_cycle3 == 0x75)
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x75)
+			caslat--;
+	} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
+		/* 280~350 range, treated as DDR 333 */
+		if (spd.clk_cycle3 == 0x60)
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x60)
+			caslat--;
+	} else if (tmp1 < 90 || tmp1 >= 350) {
+		/* DDR rate out-of-range */
+		puts("DDR:platform frequency is not fit for DDR rate\n");
+		return 0;
+	}
+
+	/*
+	 * note: caslat must also be programmed into ddr->sdram_mode
+	 * register.
+	 *
+	 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+	 * use conservative value here.
+	 */
+	trfc = spd.trfc * 1000;         /* up to ps */
+	trfc_clk = picos_to_clk(trfc);
+	trfc_low = (trfc_clk - 8) & 0xf;
+
+	ddr->timing_cfg_1 =
+	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
+	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
+	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
+	     ((caslat & 0x07) << 16 ) |
+	     (trfc_low << 12 ) |
+	     ( 0x300 ) |
+	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
+
+	ddr->timing_cfg_2 = 0x00000800;
+
+	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
+	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
+
+	/*
+	 * Only DDR I is supported
+	 * DDR I and II have different mode-register-set definition
+	 */
+
+	/* burst length is always 4 */
+	switch(caslat) {
+	case 2:
+		ddr->sdram_mode = 0x52; /* 1.5 */
+		break;
+	case 3:
+		ddr->sdram_mode = 0x22; /* 2.0 */
+		break;
+	case 4:
+		ddr->sdram_mode = 0x62; /* 2.5 */
+		break;
+	case 5:
+		ddr->sdram_mode = 0x32; /* 3.0 */
+		break;
+	default:
+		puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
+		return 0;
+	}
+	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
+
+	switch(spd.refresh) {
+	case 0x00:
+	case 0x80:
+		tmp = picos_to_clk(15625000);
+		break;
+	case 0x01:
+	case 0x81:
+		tmp = picos_to_clk(3900000);
+		break;
+	case 0x02:
+	case 0x82:
+		tmp = picos_to_clk(7800000);
+		break;
+	case 0x03:
+	case 0x83:
+		tmp = picos_to_clk(31300000);
+		break;
+	case 0x04:
+	case 0x84:
+		tmp = picos_to_clk(62500000);
+		break;
+	case 0x05:
+	case 0x85:
+		tmp = picos_to_clk(125000000);
+		break;
+	default:
+		tmp = 0x512;
+		break;
+	}
+
+	/*
+	 * Set BSTOPRE to 0x100 for page mode
+	 * If auto-charge is used, set BSTOPRE = 0
+	 */
+	ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
+	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
+
+	/*
+	 * Is this an ECC DDR chip?
+	 */
+#if defined(CONFIG_DDR_ECC)
+	if (spd.config == 0x02) {
+		ddr->err_disable = 0x0000000d;
+		ddr->err_sbe = 0x00ff0000;
+	}
+	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
+	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
+#endif
+	asm("sync;isync");
+
+	udelay(500);
+
+	/*
+	 * SS_EN=1,
+	 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
+	 * clock cycle after address/command
+	 */
+	ddr->sdram_clk_cntl = 0x82000000;
+
+	/*
+	 * Figure out the settings for the sdram_cfg register.  Build up
+	 * the entire register in 'tmp' before writing since the write into
+	 * the register will actually enable the memory controller, and all
+	 * settings must be done before enabling.
+	 *
+	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
+	 * sdram_cfg[1]   = 1 (self-refresh-enable)
+	 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+	 */
+	tmp = 0xc2000000;
+
+	/*
+	 * sdram_cfg[3] = RD_EN - registered DIMM enable
+	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
+	 */
+	if (spd.mod_attr == 0x26) {
+		tmp |= 0x10000000;
+	}
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * If the user wanted ECC (enabled via sdram_cfg[2])
+	 */
+	if (spd.config == 0x02) {
+		tmp |= 0x20000000;
+	}
+#endif
+
+#if defined(CONFIG_DDR_2T_TIMING)
+	/*
+	 * Enable 2T timing by setting sdram_cfg[16].
+	 */
+	tmp |= SDRAM_CFG_2T_EN;
+#endif
+
+	ddr->sdram_cfg = tmp;
+	asm("sync;isync");
+	udelay(500);
+
+	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
+
+	return memsize;/*in MBytes*/
+}
+#endif /* CONFIG_SPD_EEPROM */
+
+
+#if defined(CONFIG_DDR_ECC)
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+#ifndef FIXME
+	uint *p = 0;
+	uint i = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	dma_init();
+
+	for (*p = 0; p < (uint *)(8 * 1024); p++) {
+		if (((unsigned int)p & 0x1f) == 0) {
+			ppcDcbz((unsigned long) p);
+		}
+		*p = (unsigned int)0xdeadbeef;
+		if (((unsigned int)p & 0x1c) == 0x1c) {
+			ppcDcbf((unsigned long) p);
+		}
+	}
+
+	/* 8K */
+	dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
+	/* 16K */
+	dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
+	/* 32K */
+	dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
+	/* 64K */
+	dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
+	/* 128k */
+	dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
+	/* 256k */
+	dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
+	/* 512k */
+	dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
+	/* 1M */
+	dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
+	/* 2M */
+	dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
+	/* 4M */
+	dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+
+	for (i = 1; i < dram_size / 0x800000; i++) {
+		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+	}
+
+	/*
+	 * Enable errors for ECC.
+	 */
+	ddr->err_disable = 0x00000000;
+	asm("sync;isync");
+#endif
+}
+
+#endif	/* CONFIG_DDR_ECC */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
new file mode 100644
index 0000000..260137d
--- /dev/null
+++ b/cpu/mpc83xx/speed.c
@@ -0,0 +1,421 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <asm/processor.h>
+
+/* ----------------------------------------------------------------- */
+
+typedef enum {
+	_unk,
+	_off,
+	_byp,
+	_x8,
+	_x4,
+	_x2,
+	_x1,
+	_1x,
+	_1_5x,
+	_2x,
+	_2_5x,
+	_3x
+} mult_t;
+
+typedef struct {
+	mult_t core_csb_ratio;
+	mult_t  vco_divider;
+} corecnf_t;
+
+corecnf_t corecnf_tab[] = {
+	{ _byp, _byp},	/* 0x00 */
+	{ _byp, _byp},	/* 0x01 */
+	{ _byp, _byp},	/* 0x02 */
+	{ _byp, _byp},	/* 0x03 */
+	{ _byp, _byp},	/* 0x04 */
+	{ _byp, _byp},	/* 0x05 */
+	{ _byp, _byp},	/* 0x06 */
+	{ _byp, _byp},	/* 0x07 */
+	{  _1x,  _x2},	/* 0x08 */
+	{  _1x,  _x4},	/* 0x09 */
+	{  _1x,  _x8},	/* 0x0A */
+	{  _1x,  _x8},	/* 0x0B */
+	{_1_5x,  _x2},	/* 0x0C */
+	{_1_5x,  _x4},	/* 0x0D */
+	{_1_5x,  _x8},	/* 0x0E */
+	{_1_5x,  _x8},	/* 0x0F */
+	{  _2x,  _x2},	/* 0x10 */
+	{  _2x,  _x4},	/* 0x11 */
+	{  _2x,  _x8},	/* 0x12 */
+	{  _2x,  _x8},	/* 0x13 */
+	{_2_5x,  _x2},	/* 0x14 */
+	{_2_5x,  _x4},	/* 0x15 */
+	{_2_5x,  _x8},	/* 0x16 */
+	{_2_5x,  _x8},	/* 0x17 */
+	{  _3x,  _x2},	/* 0x18 */
+	{  _3x,  _x4},	/* 0x19 */
+	{  _3x,  _x8},	/* 0x1A */
+	{  _3x,  _x8},	/* 0x1B */
+};
+
+/* ----------------------------------------------------------------- */
+
+/*
+ *
+ */
+int get_clocks (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 pci_sync_in;
+	u8  spmf;
+	u8  clkin_div;
+	u32 sccr;
+	u32 corecnf_tab_index;
+	u8  corepll;
+	u32 lcrr;
+
+	u32 csb_clk;
+	u32 tsec1_clk;
+	u32 tsec2_clk;
+	u32 core_clk;
+	u32 usbmph_clk;
+	u32 usbdr_clk;
+	u32 i2c_clk;
+	u32 enc_clk;
+	u32 lbiu_clk;
+	u32 lclk_clk;
+	u32 ddr_clk;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+#ifndef CFG_HRCW_HIGH
+# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
+#endif /* CFG_HCWD_HIGH */
+
+#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
+# ifndef CONFIG_83XX_CLKIN
+#  error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
+# endif /* CONFIG_83XX_CLKIN */
+# ifdef CONFIG_83XX_PCICLK
+#  warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
+# endif /* CONFIG_83XX_PCICLK */
+/* PCI Host Mode */
+	if (!(im->reset.rcwh & RCWH_PCIHOST)) {
+		/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
+		/* FIXME: findout if there is a way to issue some warning */
+		return -2;
+	}
+	if (im->clk.spmr & SPMR_CKID) {
+		pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
+	}
+	else {
+		pci_sync_in = CONFIG_83XX_CLKIN;
+	}
+#else
+# ifdef CONFIG_83XX_CLKIN
+#  warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
+# endif /* CONFIG_83XX_CLKIN */
+# ifndef CONFIG_83XX_PCICLK
+#  error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
+# endif /* CONFIG_83XX_PCICLK */
+/* PCI Agent Mode */
+	if (im->reset.rcwh & RCWH_PCIHOST) {
+		/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
+		return -3;
+	}
+	pci_sync_in = CONFIG_83XX_PCICLK;
+#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
+
+	/* we have up to date pci_sync_in */
+	spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
+	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
+
+	if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
+		csb_clk	= (pci_sync_in * spmf * (1 + clkin_div)) / 2;
+	}
+	else {
+		csb_clk = pci_sync_in * spmf * (1 + clkin_div);
+	}
+
+	sccr = im->clk.sccr;
+	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
+	case 0:
+		tsec1_clk = 0;
+		break;
+	case 1:
+		tsec1_clk = csb_clk;
+		break;
+	case 2:
+		tsec1_clk = csb_clk / 2;
+		break;
+	case 3:
+		tsec1_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_TSEC1CM value */
+		return -4;
+	}
+
+	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
+	case 0:
+		tsec2_clk = 0;
+		break;
+	case 1:
+		tsec2_clk = csb_clk;
+		break;
+	case 2:
+		tsec2_clk = csb_clk / 2;
+		break;
+	case 3:
+		tsec2_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_TSEC2CM value */
+		return -5;
+	}
+	i2c_clk = tsec2_clk;
+
+	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
+	case 0:
+		enc_clk = 0;
+		break;
+	case 1:
+		enc_clk = csb_clk;
+		break;
+	case 2:
+		enc_clk = csb_clk / 2;
+		break;
+	case 3:
+		enc_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_ENCCM value */
+		return -6;
+	}
+
+	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
+	case 0:
+		usbmph_clk = 0;
+		break;
+	case 1:
+		usbmph_clk = csb_clk;
+		break;
+	case 2:
+		usbmph_clk = csb_clk / 2;
+		break;
+	case 3:
+		usbmph_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_USBMPHCM value */
+		return -7;
+	}
+
+	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
+	case 0:
+		usbdr_clk = 0;
+		break;
+	case 1:
+		usbdr_clk = csb_clk;
+		break;
+	case 2:
+		usbdr_clk = csb_clk / 2;
+		break;
+	case 3:
+		usbdr_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_USBDRCM value */
+		return -8;
+	}
+
+	if (usbmph_clk != 0
+		&& usbdr_clk != 0
+		&& usbmph_clk != usbdr_clk ) {
+		/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
+		return -9;
+	}
+
+	lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
+	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+	switch (lcrr) {
+	case 2:
+	case 4:
+	case 8:
+		lclk_clk = lbiu_clk / lcrr;
+		break;
+	default:
+		/* unknown lcrr */
+		return -10;
+	}
+
+	ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
+
+	corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
+	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
+	if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
+		/* corecnf_tab_index is too high, possibly worng value */
+		return -11;
+	}
+	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
+	case _byp:
+	case _x1:
+	case _1x:
+		core_clk = csb_clk;
+		break;
+	case _1_5x:
+		core_clk = (3 * csb_clk) / 2;
+		break;
+	case _2x:
+		core_clk = 2 * csb_clk;
+		break;
+	case _2_5x:
+		core_clk = ( 5 * csb_clk) / 2;
+		break;
+	case _3x:
+		core_clk = 3 * csb_clk;
+		break;
+	default:
+		/* unkown core to csb ratio */
+		return -12;
+	}
+
+	gd->csb_clk    = csb_clk   ;
+	gd->tsec1_clk  = tsec1_clk ;
+	gd->tsec2_clk  = tsec2_clk ;
+	gd->core_clk   = core_clk  ;
+	gd->usbmph_clk = usbmph_clk;
+	gd->usbdr_clk  = usbdr_clk ;
+	gd->i2c_clk    = i2c_clk   ;
+	gd->enc_clk    = enc_clk   ;
+	gd->lbiu_clk   = lbiu_clk  ;
+	gd->lclk_clk   = lclk_clk  ;
+	gd->ddr_clk    = ddr_clk   ;
+
+	gd->cpu_clk = gd->core_clk;
+	gd->bus_clk = gd->lbiu_clk;
+	return 0;
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->csb_clk;
+}
+
+int print_clock_conf (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	printf("Clock configuration:\n");
+	printf("  Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
+	printf("  Core:                %4d MHz\n",gd->core_clk/1000000);
+	printf("  Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
+	printf("  Local Bus:           %4d MHz\n",gd->lclk_clk/1000000);
+	printf("  DDR:                 %4d MHz\n",gd->ddr_clk/1000000);
+	printf("  I2C:                 %4d MHz\n",gd->i2c_clk/1000000);
+	printf("  TSEC1:               %4d MHz\n",gd->tsec1_clk/1000000);
+	printf("  TSEC2:               %4d MHz\n",gd->tsec2_clk/1000000);
+	printf("  USB MPH:             %4d MHz\n",gd->usbmph_clk/1000000);
+	printf("  USB DR:              %4d MHz\n",gd->usbdr_clk/1000000);
+
+#if 0
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	ulong sccr, dfbrg;
+	ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+	corecnf_t *cp;
+
+	sccr = immap->im_clkrst.car_sccr;
+	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+
+	scmr = immap->im_clkrst.car_scmr;
+	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
+	busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
+	cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
+	plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
+	pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+
+	cp = &corecnf_tab[corecnf];
+
+	puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
+
+	switch (cp->b2c_mult) {
+	case _byp:
+		puts ("BYPASS");
+		break;
+
+	case _off:
+		puts ("OFF");
+		break;
+
+	case _unk:
+		puts ("UNKNOWN");
+		break;
+
+	default:
+		printf ("%d%sx",
+			cp->b2c_mult / 2,
+			(cp->b2c_mult % 2) ? ".5" : "");
+		break;
+	}
+
+	printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
+			cp->vco_div, cp->freq_60x, cp->freq_core);
+
+	printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
+			"plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
+			pllmf);
+
+	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
+			gd->vco_out, gd->scc_clk, gd->brg_clk);
+
+	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
+			gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+
+	if (sccr & SCCR_PCI_MODE) {
+		uint pci_div;
+
+		pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+			( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+
+		printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
+	}
+	putc ('\n');
+#endif
+	return 0;
+}
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
new file mode 100644
index 0000000..fb001a6
--- /dev/null
+++ b/cpu/mpc83xx/start.S
@@ -0,0 +1,1093 @@
+/*
+ * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *  U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
+ */
+
+#include <config.h>
+#include <mpc83xx.h>
+#include <version.h>
+
+#define CONFIG_83XX	1		/* needed for Linux kernel header files*/
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef  CONFIG_IDENT_STRING
+#define  CONFIG_IDENT_STRING "MPC83XX"
+#endif
+
+/* We don't want the  MMU yet.
+ */
+#undef	MSR_KERNEL
+
+/*
+ * Floating Point enable, Machine Check and Recoverable Interr.
+ */
+#ifdef DEBUG
+#define MSR_KERNEL (MSR_FP|MSR_RI)
+#else
+#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
+#endif
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(_FIXUP_TABLE_)
+
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+
+	GOT_ENTRY(__init_end)
+	GOT_ENTRY(_end)
+	GOT_ENTRY(__bss_start)
+	END_GOT
+
+/*
+ * Version string - must be in data segment because MPC83xx uses the
+ * first 256 bytes for the Hard Reset Configuration Word table (see
+ * below).  Similarly, can't have the U-Boot Magic Number as the first
+ * thing in the image - don't know how this will affect the image tools,
+ * but I guess I'll find out soon.
+ */
+	.data
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii " ", CONFIG_IDENT_STRING, "\0"
+
+	.text
+#define _HRCW_TABLE_ENTRY(w)		\
+	.fill	8,1,(((w)>>24)&0xff);	\
+	.fill	8,1,(((w)>>16)&0xff);	\
+	.fill	8,1,(((w)>> 8)&0xff);	\
+	.fill	8,1,(((w)    )&0xff)
+
+	_HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
+	_HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
+
+
+#ifndef CONFIG_DEFAULT_IMMR
+#error CONFIG_DEFAULT_IMMR must be defined
+#endif /* CFG_DEFAULT_IMMR */
+#ifndef CFG_IMMRBAR
+#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR
+#endif /* CFG_IMMRBAR */
+
+/*
+ * After configuration, a system reset exception is executed using the
+ * vector at offset 0x100 relative to the base set by MSR[IP]. If
+ * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
+ * base address is 0xfff00000. In the case of a Power On Reset or Hard
+ * Reset, the value of MSR[IP] is determined by the CIP field in the
+ * HRCW.
+ *
+ * Other bits in the HRCW set up the Base Address and Port Size in BR0.
+ * This determines the location of the boot ROM (flash or EPROM) in the
+ * processor's address space at boot time. As long as the HRCW is set up
+ * so that we eventually end up executing the code below when the
+ * processor executes the reset exception, the actual values used should
+ * not matter.
+ *
+ * Once we have got here, the address mask in OR0 is cleared so that the
+ * bottom 32K of the boot ROM is effectively repeated all throughout the
+ * processor's address space, after which we can jump to the absolute
+ * address at which the boot ROM was linked at compile time, and proceed
+ * to initialise the memory controller without worrying if the rug will
+ * be pulled out from under us, so to speak (it will be fine as long as
+ * we configure BR0 with the same boot ROM link address).
+ */
+	. = EXC_OFF_SYS_RESET
+
+	.globl	_start
+_start: /* time t 0 */
+	li	r21, BOOTFLAG_COLD  /* Normal Power-On: Boot from FLASH*/
+	nop
+	b	boot_cold
+
+	. = EXC_OFF_SYS_RESET + 0x10
+
+	.globl	_start_warm
+_start_warm:
+	li	r21, BOOTFLAG_WARM	/* Software reboot	*/
+	b	boot_warm
+
+
+boot_cold: /* time t 3 */
+	lis	r4, CONFIG_DEFAULT_IMMR@h
+	nop
+boot_warm: /* time t 5 */
+	mfmsr	r5			/* save msr contents	*/
+	lis	r3, CFG_IMMRBAR@h
+	ori	r3, r3, CFG_IMMRBAR@l
+	stw	r3, IMMRBAR(r4)
+
+	/* Initialise the E300 processor core		*/
+	/*------------------------------------------*/
+
+	bl	init_e300_core
+
+#ifndef CFG_RAMBOOT
+
+	/* Inflate flash location so it appears everywhere, calculate */
+	/* the absolute address in final location of the FLASH, jump  */
+	/* there and deflate the flash size back to minimal size      */
+	/*------------------------------------------------------------*/
+	bl map_flash_by_law1
+	lis r4, (CFG_MONITOR_BASE)@h
+	ori r4, r4, (CFG_MONITOR_BASE)@l
+	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr r5
+	blr
+in_flash:
+#if 1 /* Remapping flash with LAW0. */
+	bl remap_flash_by_law0
+#endif
+#endif	/* CFG_RAMBOOT */
+
+	bl setup_stack_in_data_cache_on_r1
+
+	/* let the C-code set up the rest	                    */
+	/*							                            */
+	/* Be careful to keep code relocatable & stack humble   */
+	/*------------------------------------------------------*/
+
+	GET_GOT			/* initialize GOT access	*/
+
+	/* r3: IMMR */
+	lis	r3, CFG_IMMRBAR@h
+	/* run low-level CPU init code (in Flash)*/
+	bl	cpu_init_f
+
+	/* r3: BOOTFLAG */
+	mr	r3, r21
+	/* run 1st part of board init code (in Flash)*/
+	bl	board_init_f
+
+/*
+ * Vector Table
+ */
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+#ifndef FIXME
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+#endif
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_Alignment:
+	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_ProgramCheck:
+	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+	/* I guess we could implement decrementer, and may have
+	 * to someday for timekeeping.
+	 */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+
+	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
+#ifdef DEBUG
+	. = 0x1300
+	/*
+	 * This exception occurs when the program counter matches the
+	 * Instruction Address Breakpoint Register (IABR).
+	 *
+	 * I want the cpu to halt if this occurs so I can hunt around
+	 * with the debugger and look at things.
+	 *
+	 * When DEBUG is defined, both machine check enable (in the MSR)
+	 * and checkstop reset enable (in the reset mode register) are
+	 * turned off and so a checkstop condition will result in the cpu
+	 * halting.
+	 *
+	 * I force the cpu into a checkstop condition by putting an illegal
+	 * instruction here (at least this is the theory).
+	 *
+	 * well - that didnt work, so just do an infinite loop!
+	 */
+1:	b	1b
+#else
+	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
+#endif
+	STD_EXCEPTION(0x1400, SMI, UnknownException)
+
+	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
+	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
+	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
+	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
+	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
+	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
+	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
+	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
+	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
+	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
+	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
+	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
+	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
+	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
+	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
+	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
+	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
+	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
+	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
+	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
+	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
+	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
+	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
+	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
+	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
+	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
+	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
+
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+	. = 0x3000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+
+/*
+ * This code initialises the E300 processor core
+ * (conforms to PowerPC 603e spec)
+ * Note: expects original MSR contents to be in r5.
+ */
+	.globl	init_e300_core
+init_e300_core: /* time t 10 */
+	/* Initialize machine status; enable machine check interrupt */
+	/*-----------------------------------------------------------*/
+
+	li	r3, MSR_KERNEL			/* Set ME and RI flags */
+	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */
+#ifdef DEBUG
+	rlwimi	r3, r5, 0, 21, 22   /* debugger might set SE & BE bits */
+#endif
+	SYNC						/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+	mtspr	SRR1, r3			/* Make SRR1 match MSR */
+
+
+	lis	r3, CFG_IMMRBAR@h
+#if defined(CONFIG_WATCHDOG)
+	/* Initialise the Wathcdog values and reset it (if req) */
+	/*------------------------------------------------------*/
+	lis r4, CFG_WATCHDOG_VALUE
+	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+	stw r4, SWCRR(r3)
+
+	/* and reset it */
+
+	li	r4, 0x556C
+	sth	r4, SWSRR@l(r3)
+	li	r4, 0xAA39
+	sth	r4, SWSRR@l(r3)
+#else
+	/* Disable Wathcdog  */
+	/*-------------------*/
+	xor r4, r4, r4
+	stw r4, SWCRR(r3)
+#endif /* CONFIG_WATCHDOG */
+
+	/* Initialize the Hardware Implementation-dependent Registers */
+	/* HID0 also contains cache control			*/
+	/*------------------------------------------------------*/
+
+	lis	r3, CFG_HID0_INIT@h
+	ori	r3, r3, CFG_HID0_INIT@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CFG_HID0_FINAL@h
+	ori	r3, r3, CFG_HID0_FINAL@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CFG_HID2@h
+	ori	r3, r3, CFG_HID2@l
+	SYNC
+	mtspr	HID2, r3
+
+	/* clear all BAT's					*/
+	/*----------------------------------*/
+
+	xor	r0, r0, r0
+	mtspr	DBAT0U, r0
+	mtspr	DBAT0L, r0
+	mtspr	DBAT1U, r0
+	mtspr	DBAT1L, r0
+	mtspr	DBAT2U, r0
+	mtspr	DBAT2L, r0
+	mtspr	DBAT3U, r0
+	mtspr	DBAT3L, r0
+	mtspr	IBAT0U, r0
+	mtspr	IBAT0L, r0
+	mtspr	IBAT1U, r0
+	mtspr	IBAT1L, r0
+	mtspr	IBAT2U, r0
+	mtspr	IBAT2L, r0
+	mtspr	IBAT3U, r0
+	mtspr	IBAT3L, r0
+	SYNC
+
+	/* invalidate all tlb's
+	 *
+	 * From the 603e User Manual: "The 603e provides the ability to
+	 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
+	 * instruction invalidates the TLB entry indexed by the EA, and
+	 * operates on both the instruction and data TLBs simultaneously
+	 * invalidating four TLB entries (both sets in each TLB). The
+	 * index corresponds to bits 15-19 of the EA. To invalidate all
+	 * entries within both TLBs, 32 tlbie instructions should be
+	 * issued, incrementing this field by one each time."
+	 *
+	 * "Note that the tlbia instruction is not implemented on the
+	 * 603e."
+	 *
+	 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
+	 * incrementing by 0x1000 each time. The code below is sort of
+	 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
+	 *
+	 */
+
+	li	r3, 32
+	mtctr	r3
+	li	r3, 0
+1:	tlbie	r3
+	addi	r3, r3, 0x1000
+	bdnz	1b
+	SYNC
+
+	/* Done!						*/
+	/*------------------------------*/
+	blr
+
+/* Cache functions.
+ *
+ * Note: requires that all cache bits in
+ * HID0 are in the low half word.
+ */
+	.globl	icache_enable
+icache_enable:
+	mfspr	r3, HID0
+	ori	r3, r3, HID0_ICE
+	lis	r4, 0
+	ori	r4, r4, HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_ICE|HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4     /* sets invalidate, clears enable and lock*/
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_status
+icache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, HID0_ICE_SHIFT, 31, 31
+	blr
+
+	.globl	dcache_enable
+dcache_enable:
+	mfspr	r3, HID0
+	ori	r3, r3, HID0_ENABLE_DATA_CACHE
+	lis	r4, 0
+	ori	r4, r4, HID0_LOCK_DATA_CACHE
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_LOCK_INSTRUCTION_CACHE
+	sync
+	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
+	sync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_INVALIDATE_DATA_CACHE
+	sync
+	mtspr	HID0, r4    /* sets invalidate, clears enable and lock */
+	sync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, HID0_DCE_SHIFT, 31, 31
+	blr
+
+	.globl get_pvr
+get_pvr:
+	mfspr	r3, PVR
+	blr
+
+/*-------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	mr	r1,  r3		/* Set new stack pointer	*/
+	mr	r9,  r4		/* Save copy of Global Data pointer */
+	mr	r10, r5		/* Save copy of Destination Address */
+
+	mr	r3,  r5				/* Destination Address */
+	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address */
+	ori	r4, r4, CFG_MONITOR_BASE@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
+	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size */
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
+	 *		+ Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r14, r14, r15
+	/* then the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary */
+	beq	7f		/* Protect against 0 count	  */
+	mtctr	r0
+	bge	cr1,2f
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+
+	/* copy */
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	mtctr	r0
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+
+	/* and compare */
+20:	lwzu	r20,4(r8)
+	lwzu	r21,4(r7)
+	xor. r22, r20, r21
+	bne  30f
+	bdnz	20b
+	b 4f
+
+	/* compare failed */
+30:	li r3, 0
+	blr
+
+2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:
+	bl un_setup_stack_in_data_cache
+	mr r7, r3
+	mr r8, r4
+	bl dcache_disable
+	mr r3, r7
+	mr r4, r8
+
+	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f	/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mfspr	r7,HID0		/* don't do dcbst if dcache is disabled*/
+	rlwinm	r7,r7,HID0_DCE_SHIFT,31,31
+	cmpwi	r7,0
+	beq	9f
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync		/* Wait for all dcbst to complete on bus */
+9:	mfspr	r7,HID0		/* don't do icbi if icache is disabled */
+	rlwinm	r7,r7,HID0_DCE_SHIFT,31,31
+	cmpwi	r7,0
+	beq	7f
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync		/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+
+	/*
+	 * Relocation Function, r14 point to got2+0x8000
+	 *
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	add	r0,r0,r11
+	stw	r0,0(r3)
+	bdnz	1b
+
+	/*
+	 * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+2:	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	add	r0,r0,r11
+	stw	r10,0(r3)
+	stw	r0,0(r4)
+	bdnz	3b
+4:
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(__bss_start)
+#if defined(CONFIG_HYMOD)
+	/*
+	 * For HYMOD - the environment is the very last item in flash.
+	 * The real .bss stops just before environment starts, so only
+	 * clear up to that point.
+	 *
+	 * taken from mods for FADS board
+	 */
+	lwz	r4,GOT(environment)
+#else
+	lwz	r4,GOT(_end)
+#endif
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+
+	mr	r3, r9		/* Global Data pointer		*/
+	mr	r4, r10		/* Destination Address		*/
+	bl	board_init_r
+
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	li	r9, 0x100	/* reset vector always at 0x100 */
+
+	cmplw	0, r7, r8
+	bgelr			/* return if r7>=r8 - just in case */
+
+	mflr	r4		/* save link register */
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	4b
+
+	mfmsr	r3			/* now that the vectors have */
+	lis	r7, MSR_IP@h		/* relocated into low memory */
+	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
+	andc	r3, r3, r7		/* (if it was on) */
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+
+	mtlr	r4			/* restore link register    */
+	blr
+
+	/*
+	 * Function: relocate entries for one exception vector
+	 */
+trap_reloc:
+	lwz	r0, 0(r7)		/* hdlr ...		*/
+	add	r0, r0, r3		/*  ... += dest_addr	*/
+	stw	r0, 0(r7)
+
+	lwz	r0, 4(r7)		/* int_return ...	*/
+	add	r0, r0, r3		/*  ... += dest_addr	*/
+	stw	r0, 4(r7)
+
+	blr
+
+#ifdef CFG_INIT_RAM_LOCK
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+	/* invalidate the INIT_RAM section */
+	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+	li	r2,512
+	mtctr	r2
+1:	icbi	r0, r3
+	dcbi	r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
+	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+	blr
+#endif
+
+map_flash_by_law1:
+	/* When booting from ROM (Flash or EPROM), clear the  */
+	/* Address Mask in OR0 so ROM appears everywhere      */
+	/*----------------------------------------------------*/
+	lis	r3, (CFG_IMMRBAR)@h  /* r3 <= CFG_IMMRBAR    */
+	lwz	r4, OR0@l(r3)
+	li	r5, 0x7fff        /* r5 <= 0x00007FFFF */
+	and	r4, r4, r5
+	stw	r4, OR0@l(r3)     /* OR0 <= OR0 & 0x00007FFFF */
+
+	/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
+	 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
+	 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
+	 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
+	 * 0xFF800.  From the hard resetting to here, the processor fetched and
+	 * executed the instructions one by one.  There is not absolutely
+	 * jumping happened.  Laterly, the u-boot code has to do an absolutely
+	 * jumping to tell the CPU instruction fetching component what the
+	 * u-boot TEXT base address is.  Because the TEXT base resides in the
+	 * boot ROM memory space, to garantee the code can run smoothly after
+	 * that jumping, we must map in the entire boot ROM by Local Access
+	 * Window.  Sometimes, we desire an non-0x00000 or non-0xFF800 starting
+	 * address for boot ROM, such as 0xFE000000.  In this case, the default
+	 * LBIU Local Access Widow 0 will not cover this memory space.  So, we
+	 * need another window to map in it.
+	 */
+	lis r4, (CFG_FLASH_BASE)@h
+	ori r4, r4, (CFG_FLASH_BASE)@l
+	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
+	lis r4, (0x80000016)@h
+	ori r4, r4, (0x80000016)@l
+	stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
+	blr
+
+	/* Though all the LBIU Local Access Windows and LBC Banks will be
+	 * initialized in the C code, we'd better configure boot ROM's
+	 * window 0 and bank 0 correctly at here.
+	 */
+remap_flash_by_law0:
+	/* Initialize the BR0 with the boot ROM starting address. */
+	lwz r4, BR0(r3)
+	li  r5, 0x7FFF
+	and r4, r4, r5
+	lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
+	ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
+	or  r5, r5, r4
+	stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+
+	lwz r4, OR0(r3)
+	lis r5, 0xFF80 /* 8M */
+	or r4, r4, r5
+	stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */
+
+	lis r4, (CFG_FLASH_BASE)@h
+	ori r4, r4, (CFG_FLASH_BASE)@l
+	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
+
+	lis r4, (0x80000016)@h
+	ori r4, r4, (0x80000016)@l
+	stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */
+
+	xor r4, r4, r4
+	stw r4, LBLAWBAR1(r3)
+	stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
+	blr
+
+setup_stack_in_data_cache_on_r1:
+	lis r3, (CFG_IMMRBAR)@h
+
+	/* setup D-BAT for the D-Cache (with out real memory backup) */
+
+	lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
+	mtspr	DBAT0U, r4
+	ori r4, r4, 0x0002
+	mtspr	DBAT0L, r4
+	isync
+
+#if 0
+	/* Enable MMU */
+	mfmsr r4
+	ori r4, r4, (MSR_DR | MSR_IR)@l
+	mtmsr r4
+#endif
+
+	/* Enable and invalidate data cache. */
+	mfspr	r4, HID0
+	mr	r5, r4
+	ori	r4, r4, HID0_DCE | HID0_DCI
+	ori	r5, r5, HID0_DCE
+	sync
+	mtspr	HID0, r4
+	mtspr	HID0, r5
+	sync
+
+	/* Allocate Initial RAM in data cache.*/
+	li  r0, 0
+	lis	r4, (CFG_INIT_RAM_ADDR)@h
+	ori	r4, r4, (CFG_INIT_RAM_ADDR)@l
+	li	r5, 128*8 /* 128*8*32=32Kb */
+	mtctr	r5
+1:
+	dcbz	r0, r4
+	addi	r4, r4, 32
+	bdnz	1b
+	isync
+
+	/* Lock all the D-cache, basically leaving the reset of the program without dcache */
+	mfspr	r4, HID0
+	ori	r4, r4, (HID0_DLOCK)@l
+	sync
+	mtspr	HID0 , r4
+
+	/* setup the stack pointer in r1 */
+	lis	r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+	li	r0, 0		        /* Make room for stack frame header and	*/
+
+	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
+	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
+
+	blr
+
+un_setup_stack_in_data_cache:
+	blr
+	mr r14, r4
+	mr r15, r5
+
+
+	lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
+	mtspr	DBAT0U, r4
+	ori r4, r4, 0x0002
+	mtspr	DBAT0L, r4
+	isync
+
+	/* un lock all the D-cache */
+	mfspr	r4, HID0
+	lis r5, (~(HID0_DLOCK))@h
+	ori	r5, r5, (~(HID0_DLOCK))@l
+	and r4, r4, r5
+	sync
+	mtspr	HID0 , r4
+
+	/* Re - Allocate Initial RAM in data cache.*/
+	li  r0, 0
+	lis	r4, (CFG_INIT_RAM_ADDR)@h
+	ori	r4, r4, (CFG_INIT_RAM_ADDR)@l
+	li	r5, 128*8 /* 128*8*32=32Kb */
+	mtctr	r5
+1:
+	dcbz	r0, r4
+	addi	r4, r4, 32
+	bdnz	1b
+	isync
+
+	mflr r16
+	bl dcache_disable
+	mtlr r16
+
+	blr
+
+#if 0
+#define GREEN_LIGHT 0x2B0D4046
+#define RED_LIGHT   0x250D4046
+#define LIB_CNT     0x4FFF
+
+/*
+ * Lib Light
+ */
+
+	.globl liblight
+liblight:
+	lis	r3, CFG_IMMRBAR@h
+	ori	r3, r3, CFG_IMMRBAR@l
+	li r4, 0x3002
+	mtmsr r4
+	xor r4, r4, r4
+	mtspr	HID0, r4
+	mtspr	HID2, r4
+	lis r4, 0xF8000000@h
+	ori r4, r4, 0xF8000000@l
+	stw r4, LBLAWBAR1(r3)
+	lis r4, 0x8000000E@h
+	ori r4, r4, 0x8000000E@l
+	stw r4, LBLAWAR1(r3)
+	lis r4, 0xF8000801@h
+	ori r4, r4, 0xF8000801@l
+	stw r4, BR1(r3)
+	lis r4, 0xFFFFE8f0@h
+	ori r4, r4, 0xFFFFE8f0@l
+	stw r4, OR1(r3)
+
+	lis r4, 0xF8000000@h
+	ori r4, r4, 0xF8000000@l
+	lis r5, GREEN_LIGHT@h
+	ori r5, r5, GREEN_LIGHT@l
+	lis r6, RED_LIGHT@h
+	ori r6, r6, RED_LIGHT@l
+	lis r7, LIB_CNT@h
+	ori r7, r7, LIB_CNT@l
+
+1:
+	stw r5, 0(r4)
+	mtctr r7
+2:	bdnz 2b
+	stw r6, 0(r4)
+	mtctr r7
+3:	bdnz 3b
+	b 1b
+
+#endif
diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c
new file mode 100644
index 0000000..c7a5638
--- /dev/null
+++ b/cpu/mpc83xx/traps.c
@@ -0,0 +1,274 @@
+/*
+ * linux/arch/ppc/kernel/traps.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware
+ * exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mpc8349_pci.h>
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+#define END_OF_MEM	(gd->bd->bi_memstart + gd->bd->bi_memsize)
+
+/*
+ * Trap & Exception support
+ */
+
+void
+print_backtrace(unsigned long *sp)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int cnt = 0;
+	unsigned long i;
+
+	puts ("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
+
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			putc ('\n');
+		printf("%08lX ", i);
+		if (cnt > 32) break;
+		sp = (unsigned long *)*sp;
+	}
+	putc ('\n');
+}
+
+void show_regs(struct pt_regs * regs)
+{
+	int i;
+
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+	       regs->msr&MSR_IR ? 1 : 0,
+	       regs->msr&MSR_DR ? 1 : 0);
+
+	putc ('\n');
+	for (i = 0;  i < 32;  i++) {
+		if ((i % 8) == 0) {
+			printf("GPR%02d: ", i);
+		}
+
+		printf("%08lX ", regs->gpr[i]);
+		if ((i % 8) == 7) {
+			putc ('\n');
+		}
+	}
+}
+
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+#ifdef CONFIG_PCI
+void dump_pci (void)
+{
+/*
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	printf ("PCI: err status %x err mask %x err ctrl %x\n",
+		le32_to_cpu (immap->im_pci.pci_esr),
+		le32_to_cpu (immap->im_pci.pci_emr),
+		le32_to_cpu (immap->im_pci.pci_ecr));
+	printf ("     error address %x error data %x ctrl %x\n",
+		le32_to_cpu (immap->im_pci.pci_eacr),
+		le32_to_cpu (immap->im_pci.pci_edcr),
+		le32_to_cpu (immap->im_pci.pci_eccr));
+*/
+}
+#endif
+
+void
+MachineCheckException(struct pt_regs *regs)
+{
+	unsigned long fixup;
+
+	/* Probing PCI using config cycles cause this exception
+	 * when a device is not present.  Catch it and return to
+	 * the PCI exception handler.
+	 */
+#ifdef CONFIG_PCI
+#if 0
+	volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+#ifdef DEBUG
+	dump_pci();
+#endif
+	/* clear the error in the error status register */
+	if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
+		immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
+		return;
+	}
+#endif
+#endif /* CONFIG_PCI */
+	if ((fixup = search_exception_table(regs->nip)) != 0) {
+		regs->nip = fixup;
+		return;
+	}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+
+	puts ("Machine check in kernel mode.\n"
+		"Caused by (from msr): ");
+	printf("regs %p ",regs);
+	switch( regs->msr & 0x000F0000) {
+	case (0x80000000>>12):
+		puts ("Machine check signal - probably due to mm fault\n"
+			"with mmu off\n");
+		break;
+	case (0x80000000>>13):
+		puts ("Transfer error ack signal\n");
+		break;
+	case (0x80000000>>14):
+		puts ("Data parity signal\n");
+		break;
+	case (0x80000000>>15):
+		puts ("Address parity signal\n");
+		break;
+	default:
+		puts ("Unknown values in msr\n");
+	}
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+#ifdef CONFIG_PCI
+	dump_pci();
+#endif
+	panic("machine check");
+}
+
+void
+AlignmentException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
+}
+
+void
+ProgramCheckException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
+}
+
+void
+SoftEmuException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
+}
+
+
+void
+UnknownException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	       regs->nip, regs->msr, regs->trap);
+	_exception(0, regs);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+void
+DebugException(struct pt_regs *regs)
+{
+	printf("Debugger trap at @ %lx\n", regs->nip );
+	show_regs(regs);
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+	do_bedbug_breakpoint( regs );
+#endif
+}
+
+/* Probe an address by reading.  If not present, return -1, otherwise
+ * return 0.
+ */
+int
+addr_probe(uint *addr)
+{
+#if 0
+	int	retval;
+
+	__asm__ __volatile__(			\
+		"1:	lwz %0,0(%1)\n"		\
+		"	eieio\n"		\
+		"	li %0,0\n"		\
+		"2:\n"				\
+		".section .fixup,\"ax\"\n"	\
+		"3:	li %0,-1\n"		\
+		"	b 2b\n"			\
+		".section __ex_table,\"a\"\n"	\
+		"	.align 2\n"		\
+		"	.long 1b,3b\n"		\
+		".text"				\
+		: "=r" (retval) : "r"(addr));
+
+	return (retval);
+#endif
+	return 0;
+}
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 996915e..5298dc1 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o resetvec.o
-COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o tsec.o \
+COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
 	  pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
 OBJS	= $(COBJS)
 
diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c
index df11052..aa8a5a5 100644
--- a/cpu/mpc85xx/commproc.c
+++ b/cpu/mpc85xx/commproc.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/cpm_85xx.h>
 
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 /*
  * because we have stack and init data in dual port ram
  * we must reduce the size
@@ -211,4 +211,4 @@ ulong post_word_load (void)
 
 #endif	/* CONFIG_POST */
 
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 4a1ccb0..f7fe22e 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -38,6 +38,7 @@ int checkcpu (void)
 	uint lcrr;		/* local bus clock ratio register */
 	uint clkdiv;		/* clock divider portion of lcrr */
 	uint pvr, svr;
+	uint fam;
 	uint ver;
 	uint major, minor;
 
@@ -60,6 +61,12 @@ int checkcpu (void)
 	case SVR_8560:
 		puts("8560");
 		break;
+	case SVR_8548:
+		puts("8548");
+		break;
+	case SVR_8548_E:
+		puts("8548_E");
+		break;
 	default:
 		puts("Unknown");
 		break;
@@ -67,13 +74,14 @@ int checkcpu (void)
 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 
 	pvr = get_pvr();
+	fam = PVR_FAM(pvr);
 	ver = PVR_VER(pvr);
 	major = PVR_MAJ(pvr);
 	minor = PVR_MIN(pvr);
 
 	printf("Core:  ");
-	switch (ver) {
-	case PVR_VER(PVR_85xx):
+	switch (fam) {
+	case PVR_FAM(PVR_85xx):
 	    puts("E500");
 	    break;
 	default:
@@ -84,7 +92,7 @@ int checkcpu (void)
 
 	get_sys_info(&sysinfo);
 
-	puts("Clocks Configuration:\n");
+	puts("Clock Configuration:\n");
 	printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
 	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
 	printf("       DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
@@ -101,6 +109,13 @@ int checkcpu (void)
 #endif
 	clkdiv = lcrr & 0x0f;
 	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+#ifdef CONFIG_MPC8548
+		/*
+		 * Yes, the entire PQ38 family use the same
+		 * bit-representation for twice the clock divider values.
+		 */
+		 clkdiv *= 2;
+#endif
 		printf("LBC:%4lu MHz\n",
 		       sysinfo.freqSystemBus / 1000000 / clkdiv);
 	} else {
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index ee2f79f..efde9cc 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -30,7 +30,7 @@
 #include <ioports.h>
 #include <asm/io.h>
 
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_CPM2
 static void config_8560_ioports (volatile immap_t * immr)
 {
 	int portnum;
@@ -115,7 +115,7 @@ void cpu_init_f (void)
 	memset ((void *) gd, 0, sizeof (gd_t));
 
 
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_CPM2
 	config_8560_ioports(immap);
 #endif
 
@@ -173,32 +173,63 @@ void cpu_init_f (void)
 	memctl->br7 = CFG_BR7_PRELIM;
 #endif
 
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	m8560_cpm_reset();
 #endif
 }
 
+
 /*
- * We initialize L2 as cache here.
+ * Initialize L2 as cache.
+ *
+ * The newer 8548, etc, parts have twice as much cache, but
+ * use the same bit-encoding as the older 8555, etc, parts.
+ *
+ * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
  */
-int cpu_init_r (void)
+
+int cpu_init_r(void)
 {
 #if defined(CONFIG_L2_CACHE)
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
-	volatile uint temp;
+	volatile uint cache_ctl;
+	uint svr, ver;
+
+	svr = get_svr();
+	ver = SVR_VER(svr);
+
+	asm("msync;isync");
+	cache_ctl = l2cache->l2ctl;
+
+	switch (cache_ctl & 0x30000000) {
+	case 0x20000000:
+		if (ver == SVR_8548 || ver == SVR_8548_E) {
+			printf ("L2 cache 512KB:");
+		} else {
+			printf ("L2 cache 256KB:");
+		}
+		break;
+	case 0x00000000:
+	case 0x10000000:
+	case 0x30000000:
+	default:
+		printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
+		return -1;
+	}
 
 	asm("msync;isync");
 	l2cache->l2ctl = 0x68000000; /* invalidate */
-	temp = l2cache->l2ctl;
+	cache_ctl = l2cache->l2ctl;
 	asm("msync;isync");
+
 	l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
-	temp = l2cache->l2ctl;
+	cache_ctl = l2cache->l2ctl;
 	asm("msync;isync");
 
-	printf("L2:    256 kB enabled\n");
+	printf(" enabled\n");
 #else
-	printf("L2:    disabled.\n");
+	printf("L2 cache: disabled\n");
 #endif
 
 	return 0;
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index 122ca87..cbbb3a4 100644
--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -48,7 +48,7 @@
 #include <config.h>
 #include <net.h>
 
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
 	defined(CONFIG_NET_MULTI)
@@ -458,4 +458,4 @@ int fec_initialize(bd_t *bis)
 
 #endif	/* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
 
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c
index ea82761..cf060d6 100644
--- a/cpu/mpc85xx/serial_scc.c
+++ b/cpu/mpc85xx/serial_scc.c
@@ -35,7 +35,7 @@
 #include <common.h>
 #include <asm/cpm_85xx.h>
 
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 #if defined(CONFIG_CONS_ON_SCC)
 
 #if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
@@ -271,4 +271,4 @@ serial_tstc()
 
 #endif	/* CONFIG_CONS_ON_SCC */
 
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 5a1dbe2..af99282 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -28,10 +28,11 @@
 #include <spd.h>
 #include <asm/mmu.h>
 
-#if defined(CONFIG_DDR_ECC)
-extern void dma_init (void);
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
 extern uint dma_check(void);
-extern int  dma_xfer (void *dest, uint count, void *src);
+extern int dma_xfer(void *dest, uint count, void *src);
 #endif
 
 #ifdef CONFIG_SPD_EEPROM
@@ -40,6 +41,9 @@ extern int  dma_xfer (void *dest, uint count, void *src);
 #define CFG_READ_SPD	i2c_read
 #endif
 
+static unsigned int setup_laws_and_tlbs(unsigned int memsize);
+
+
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
  */
@@ -57,311 +61,829 @@ picos_to_clk(int picos)
 	return clks;
 }
 
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ *		DDR I	DDR II
+ *	Bit	Size	Size
+ *	---	-----	------
+ *	7 high	512MB	512MB
+ *	6	256MB	256MB
+ *	5	128MB	128MB
+ *	4	 64MB	 16GB
+ *	3	 32MB	  8GB
+ *	2	 16MB	  4GB
+ *	1	  2GB	  2GB
+ *	0 low	  1GB	  1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ */
+
+unsigned int
+compute_banksize(unsigned int mem_type, unsigned char row_dens)
+{
+	unsigned int bsize;
+
+	if (mem_type == SPD_MEMTYPE_DDR) {
+		/* Bottom 2 bits up to the top. */
+		bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+		debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+	} else {
+		/* Bottom 5 bits up to the top. */
+		bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
+		debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+	}
+	return bsize;
+}
+
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II.  No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+
 unsigned int
-banksize(unsigned char row_dens)
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
 {
-	return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+	/*
+	 * Table look up the lower nibble, allow DDR I & II.
+	 */
+	unsigned int tenths_ps[16] = {
+		0,
+		100,
+		200,
+		300,
+		400,
+		500,
+		600,
+		700,
+		800,
+		900,
+		250,
+		330,	/* FIXME: Is 333 better/valid? */
+		660,	/* FIXME: Is 667 better/valid? */
+		750,
+		0,	/* undefined */
+		0	/* undefined */
+	};
+
+	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+	unsigned int tenth_ns = spd_val & 0x0F;
+	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+	return ps;
 }
 
+
 long int
 spd_sdram(void)
 {
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_ddr_t *ddr = &immap->im_ddr;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
 	spd_eeprom_t spd;
-	unsigned tmp, tmp1;
+	unsigned int n_ranks;
+	unsigned int rank_density;
+	unsigned int odt_rd_cfg, odt_wr_cfg;
+	unsigned int odt_cfg, mode_odt_enable;
+	unsigned int dqs_cfg;
+	unsigned char twr_clk, twtr_clk, twr_auto_clk;
+	unsigned int tCKmin_ps, tCKmax_ps;
+	unsigned int max_data_rate, effective_data_rate;
+	unsigned int busfreq;
+	unsigned sdram_cfg;
 	unsigned int memsize;
-	unsigned int tlb_size;
-	unsigned int law_size;
-	unsigned char caslat;
-	unsigned int ram_tlb_index;
-	unsigned int ram_tlb_address;
+	unsigned char caslat, caslat_ctrl;
+	unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+	unsigned int trcd_clk;
+	unsigned int trtp_clk;
+	unsigned char cke_min_clk;
+	unsigned char add_lat;
+	unsigned char wr_lat;
+	unsigned char wr_data_delay;
+	unsigned char four_act;
+	unsigned char cpo;
+	unsigned char burst_len;
+	unsigned int mode_caslat;
+	unsigned char sdram_type;
+	unsigned char d_init;
 
-	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+	/*
+	 * Read SPD information.
+	 */
+	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
 
-	if (spd.nrows > 2) {
-		puts("DDR:Only two chip selects are supported on ADS.\n");
+	/*
+	 * Check for supported memory module types.
+	 */
+	if (spd.mem_type != SPD_MEMTYPE_DDR &&
+	    spd.mem_type != SPD_MEMTYPE_DDR2) {
+		printf("Unable to locate DDR I or DDR II module.\n"
+		       "    Fundamental memory type is 0x%0x\n",
+		       spd.mem_type);
 		return 0;
 	}
 
-	if (spd.nrow_addr < 12
-	    || spd.nrow_addr > 14
-	    || spd.ncol_addr < 8
-	    || spd.ncol_addr > 11) {
-		puts("DDR:Row or Col number unsupported.\n");
+	/*
+	 * These test gloss over DDR I and II differences in interpretation
+	 * of bytes 3 and 4, but irrelevantly.  Multiple asymmetric banks
+	 * are not supported on DDR I; and not encoded on DDR II.
+	 *
+	 * Also note that the 8548 controller can support:
+	 *    12 <= nrow <= 16
+	 * and
+	 *     8 <= ncol <= 11 (still, for DDR)
+	 *     6 <= ncol <=  9 (for FCRAM)
+	 */
+	if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+		printf("DDR: Unsupported number of Row Addr lines: %d.\n",
+		       spd.nrow_addr);
+		return 0;
+	}
+	if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+		printf("DDR: Unsupported number of Column Addr lines: %d.\n",
+		       spd.ncol_addr);
 		return 0;
 	}
 
-	ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
-	ddr->cs0_config = ( 1 << 31
-			    | (spd.nrow_addr - 12) << 8
-			    | (spd.ncol_addr - 8) );
-	debug("\n");
-	debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
-	debug("cs0_config = 0x%08x\n",ddr->cs0_config);
-
-	if (spd.nrows == 2) {
-		ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
-				  | ((banksize(spd.row_dens) >> 23) - 1) );
-		ddr->cs1_config = ( 1<<31
-				    | (spd.nrow_addr-12) << 8
-				    | (spd.ncol_addr-8) );
-		debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
-		debug("cs1_config = 0x%08x\n",ddr->cs1_config);
+	/*
+	 * Determine the number of physical banks controlled by
+	 * different Chip Select signals.  This is not quite the
+	 * same as the number of DIMM modules on the board.  Feh.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		n_ranks = spd.nrows;
+	} else {
+		n_ranks = (spd.nrows & 0x7) + 1;
 	}
 
-	if (spd.mem_type != 0x07) {
-		puts("No DDR module found!\n");
+	debug("DDR: number of ranks = %d\n", n_ranks);
+
+	if (n_ranks > 2) {
+		printf("DDR: Only 2 chip selects are supported: %d\n",
+		       n_ranks);
 		return 0;
 	}
 
 	/*
-	 * Figure out memory size in Megabytes.
+	 * Adjust DDR II IO voltage biasing.  It just makes it work.
 	 */
-	memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		gur->ddrioovcr = (0
+				  | 0x80000000		/* Enable */
+				  | 0x10000000		/* VSEL to 1.8V */
+				  );
+	}
 
 	/*
-	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
+	 * Determine the size of each Rank in bytes.
 	 */
-	law_size = 19 + __ilog2(memsize);
+	rank_density = compute_banksize(spd.mem_type, spd.row_dens);
+
 
 	/*
-	 * Determine size of each TLB1 entry.
+	 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000	first 256 Meg
 	 */
-	switch (memsize) {
-	case 16:
-	case 32:
-		tlb_size = BOOKE_PAGESZ_16M;
-		break;
-	case 64:
-	case 128:
-		tlb_size = BOOKE_PAGESZ_64M;
-		break;
-	case 256:
-	case 512:
-	case 1024:
-	case 2048:
-		tlb_size = BOOKE_PAGESZ_256M;
-		break;
-	default:
-		puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
-		return 0;
-		break;
-	}
+	ddr->cs0_bnds = (rank_density >> 24) - 1;
 
 	/*
-	 * Configure DDR TLB1 entries.
-	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
+	 * ODT configuration recommendation from DDR Controller Chapter.
 	 */
-	ram_tlb_index = 8;
-	ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
-	while (ram_tlb_address < (memsize * 1024 * 1024)
-	      && ram_tlb_index < 16) {
-		mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
-		mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
-		mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-				      0, 0, 0, 0, 0, 0, 0, 0));
-		mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-				      0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
-		asm volatile("isync;msync;tlbwe;isync");
+	odt_rd_cfg = 0;			/* Never assert ODT */
+	odt_wr_cfg = 0;			/* Never assert ODT */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		odt_wr_cfg = 1;		/* Assert ODT on writes to CS0 */
+#if 0
+		/* FIXME: How to determine the number of dimm modules? */
+		if (n_dimm_modules == 2) {
+			odt_rd_cfg = 1;	/* Assert ODT on reads to CS0 */
+		}
+#endif
+	}
 
-		debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
-		debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
-		debug("DDR:MAS2=0x%08x\n",
-		      TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-				0, 0, 0, 0, 0, 0, 0, 0));
-		debug("DDR:MAS3=0x%08x\n",
-		      TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-				0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+	ddr->cs0_config = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
+			    | (spd.nrow_addr - 12) << 8
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("DDR: cs0_bnds   = 0x%08x\n", ddr->cs0_bnds);
+	debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
 
-		ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
-		ram_tlb_index++;
+	if (n_ranks == 2) {
+		/*
+		 * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
+		 */
+		ddr->cs1_bnds = ( (rank_density >> 8)
+				  | ((rank_density >> (24 - 1)) - 1) );
+		ddr->cs1_config = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
+				    | (spd.nrow_addr - 12) << 8
+				    | (spd.ncol_addr - 8) );
+		debug("DDR: cs1_bnds   = 0x%08x\n", ddr->cs1_bnds);
+		debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
 	}
 
+
 	/*
-	 * Set up LAWBAR for all of DDR.
+	 * Find the largest CAS by locating the highest 1 bit
+	 * in the spd.cas_lat field.  Translate it to a DDR
+	 * controller field value:
+	 *
+	 *	CAS Lat	DDR I	DDR II	Ctrl
+	 *	Clocks	SPD Bit	SPD Bit	Value
+	 *	-------	-------	-------	-----
+	 *	1.0	0		0001
+	 *	1.5	1		0010
+	 *	2.0	2	2	0011
+	 *	2.5	3		0100
+	 *	3.0	4	3	0101
+	 *	3.5	5		0110
+	 *	4.0		4	0111
+	 *	4.5			1000
+	 *	5.0		5	1001
 	 */
-	ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
-	ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
-	debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
-	debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
-
-	/*
-	 * find the largest CAS
-	 */
-	if(spd.cas_lat & 0x40) {
-		caslat = 7;
-	} else if (spd.cas_lat & 0x20) {
-		caslat = 6;
-	} else if (spd.cas_lat & 0x10) {
-		caslat = 5;
-	} else if (spd.cas_lat & 0x08) {
-		caslat = 4;
-	} else if (spd.cas_lat & 0x04) {
-		caslat = 3;
-	} else if (spd.cas_lat & 0x02) {
-		caslat = 2;
-	} else if (spd.cas_lat & 0x01) {
-		caslat = 1;
-	} else {
-		puts("DDR:no valid CAS Latency information.\n");
+	caslat = __ilog2(spd.cas_lat);
+	if ((spd.mem_type == SPD_MEMTYPE_DDR)
+	    && (caslat > 5)) {
+		printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+		return 0;
+
+	} else if (spd.mem_type == SPD_MEMTYPE_DDR2
+		   && (caslat < 2 || caslat > 5)) {
+		printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+		       spd.cas_lat);
 		return 0;
 	}
+	debug("DDR: caslat SPD bit is %d\n", caslat);
+
+	/*
+	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
+	 * nanoseconds and represented as BCD.
+	 */
+	tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
+	debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
+
+	/*
+	 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
+	 */
+	max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
+	debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
+
 
-	tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
-		       + (spd.clk_cycle & 0x0f));
-	debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
+	/*
+	 * Adjust the CAS Latency to allow for bus speeds that
+	 * are slower than the DDR module.
+	 */
+	busfreq = get_bus_freq(0) / 1000000;	/* MHz */
 
-	tmp1 = get_bus_freq(0) / 1000000;
-	if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
-		/* 90~230 range, treated as DDR 200 */
-		if (spd.clk_cycle3 == 0xa0)
+	effective_data_rate = max_data_rate;
+	if (busfreq < 90) {
+		/* DDR rate out-of-range */
+		puts("DDR: platform frequency is not fit for DDR rate\n");
+		return 0;
+
+	} else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
+		/*
+		 * busfreq 90~230 range, treated as DDR 200.
+		 */
+		effective_data_rate = 200;
+		if (spd.clk_cycle3 == 0xa0)	/* 10 ns */
 			caslat -= 2;
-		else if(spd.clk_cycle2 == 0xa0)
+		else if (spd.clk_cycle2 == 0xa0)
 			caslat--;
-	} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
-		/* 230-280 range, treated as DDR 266 */
-		if (spd.clk_cycle3 == 0x75)
+
+	} else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
+		/*
+		 * busfreq 230~280 range, treated as DDR 266.
+		 */
+		effective_data_rate = 266;
+		if (spd.clk_cycle3 == 0x75)	/* 7.5 ns */
 			caslat -= 2;
 		else if (spd.clk_cycle2 == 0x75)
 			caslat--;
-	} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
-		/* 280~350 range, treated as DDR 333 */
-		if (spd.clk_cycle3 == 0x60)
+
+	} else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
+		/*
+		 * busfreq 280~350 range, treated as DDR 333.
+		 */
+		effective_data_rate = 333;
+		if (spd.clk_cycle3 == 0x60)	/* 6.0 ns */
 			caslat -= 2;
 		else if (spd.clk_cycle2 == 0x60)
 			caslat--;
-	} else if (tmp1 < 90 || tmp1 >= 350) {
-		/* DDR rate out-of-range */
-		puts("DDR:platform frequency is not fit for DDR rate\n");
+
+	} else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
+		/*
+		 * busfreq 350~460 range, treated as DDR 400.
+		 */
+		effective_data_rate = 400;
+		if (spd.clk_cycle3 == 0x50)	/* 5.0 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x50)
+			caslat--;
+
+	} else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
+		/*
+		 * busfreq 460~560 range, treated as DDR 533.
+		 */
+		effective_data_rate = 533;
+		if (spd.clk_cycle3 == 0x3D)	/* 3.75 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x3D)
+			caslat--;
+
+	} else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
+		/*
+		 * busfreq 560~700 range, treated as DDR 667.
+		 */
+		effective_data_rate = 667;
+		if (spd.clk_cycle3 == 0x30)	/* 3.0 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x30)
+			caslat--;
+
+	} else if (700 <= busfreq) {
+		/*
+		 * DDR rate out-of-range
+		 */
+		printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
+		     busfreq, max_data_rate);
 		return 0;
 	}
 
+
 	/*
-	 * note: caslat must also be programmed into ddr->sdram_mode
-	 * register.
-	 *
-	 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
-	 * use conservative value here.
+	 * Convert caslat clocks to DDR controller value.
+	 * Force caslat_ctrl to be DDR Controller field-sized.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		caslat_ctrl = (caslat + 1) & 0x07;
+	} else {
+		caslat_ctrl =  (2 * caslat - 1) & 0x0f;
+	}
+
+	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
+	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+	      caslat, caslat_ctrl);
+
+	/*
+	 * Timing Config 0.
+	 * Avoid writing for DDR I.  The new PQ38 DDR controller
+	 * dreams up non-zero default values to be backwards compatible.
 	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		unsigned char taxpd_clk = 8;		/* By the book. */
+		unsigned char tmrd_clk = 2;		/* By the book. */
+		unsigned char act_pd_exit = 2;		/* Empirical? */
+		unsigned char pre_pd_exit = 6;		/* Empirical? */
+
+		ddr->timing_cfg_0 = (0
+			| ((act_pd_exit & 0x7) << 20)	/* ACT_PD_EXIT */
+			| ((pre_pd_exit & 0x7) << 16)	/* PRE_PD_EXIT */
+			| ((taxpd_clk & 0xf) << 8)	/* ODT_PD_EXIT */
+			| ((tmrd_clk & 0xf) << 0)	/* MRS_CYC */
+			);
+#if 0
+		ddr->timing_cfg_0 |= 0xaa000000;	/* extra cycles */
+#endif
+		debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+
+	} else {
+#if 0
+		/*
+		 * Force extra cycles with 0xaa bits.
+		 * Incidentally supply the dreamt-up backwards compat value!
+		 */
+		ddr->timing_cfg_0 = 0x00110105;	/* backwards compat value */
+		ddr->timing_cfg_0 |= 0xaa000000;	/* extra cycles */
+		debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+#endif
+	}
+
+
+	/*
+	 * Some Timing Config 1 values now.
+	 * Sneak Extended Refresh Recovery in here too.
+	 */
+
+	/*
+	 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+	 * use conservative value.
+	 * For DDR II, they are bytes 36 and 37, in quarter nanos.
+	 */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_clk = 3;	/* Clocks */
+		twtr_clk = 1;	/* Clocks */
+	} else {
+		twr_clk = picos_to_clk(spd.twr * 250);
+		twtr_clk = picos_to_clk(spd.twtr * 250);
+	}
+
+	/*
+	 * Calculate Trfc, in picos.
+	 * DDR I:  Byte 42 straight up in ns.
+	 * DDR II: Byte 40 and 42 swizzled some, in ns.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		trfc = spd.trfc * 1000;		/* up to ps */
+	} else {
+		unsigned int byte40_table_ps[8] = {
+			0,
+			250,
+			330,
+			500,
+			660,
+			750,
+			0,
+			0
+		};
+
+		trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+			+ byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+	}
+	trfc_clk = picos_to_clk(trfc);
+
+	/*
+	 * Trcd, Byte 29, from quarter nanos to ps and clocks.
+	 */
+	trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+	/*
+	 * Convert trfc_clk to DDR controller fields.  DDR I should
+	 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+	 * 8548 controller has an extended REFREC field of three bits.
+	 * The controller automatically adds 8 clocks to this value,
+	 * so preadjust it down 8 first before splitting it up.
+	 */
+	trfc_low = (trfc_clk - 8) & 0xf;
+	trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
+
+	/*
+	 * Sneak in some Extended Refresh Recovery.
+	 */
+	ddr->ext_refrec = (trfc_high << 16);
+	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+
 	ddr->timing_cfg_1 =
-	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
-	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
-	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
-	     ((caslat & 0x07) << 16 ) |
-	     (((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
-	     ( 0x300 ) |
-	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
+	    (0
+	     | ((picos_to_clk(spd.trp * 250) & 0x07) << 28)	/* PRETOACT */
+	     | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24)	/* ACTTOPRE */
+	     | (trcd_clk << 20)					/* ACTTORW */
+	     | (caslat_ctrl << 16)				/* CASLAT */
+	     | (trfc_low << 12)					/* REFEC */
+	     | ((twr_clk & 0x07) << 8)				/* WRRREC */
+	     | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4)	/* ACTTOACT */
+	     | ((twtr_clk & 0x07) << 0)				/* WRTORD */
+	     );
 
-	ddr->timing_cfg_2 = 0x00000800;
+	debug("DDR: timing_cfg_1  = 0x%08x\n", ddr->timing_cfg_1);
 
-	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
-	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
 
 	/*
-	 * Only DDR I is supported
-	 * DDR I and II have different mode-register-set definition
+	 * Timing_Config_2
+	 * Was: 0x00000800;
 	 */
 
-	/* burst length is always 4 */
-	switch(caslat) {
-	case 2:
-		ddr->sdram_mode = 0x52; /* 1.5 */
-		break;
-	case 3:
-		ddr->sdram_mode = 0x22; /* 2.0 */
-		break;
-	case 4:
-		ddr->sdram_mode = 0x62; /* 2.5 */
-		break;
-	case 5:
-		ddr->sdram_mode = 0x32; /* 3.0 */
-		break;
-	default:
-		puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
-		return 0;
+	/*
+	 * Additive Latency
+	 * For DDR I, 0.
+	 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+	 * which comes from Trcd, and also note that:
+	 *	add_lat + caslat must be >= 4
+	 */
+	add_lat = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2
+	    && (odt_wr_cfg || odt_rd_cfg)
+	    && (caslat < 4)) {
+		add_lat = 4 - caslat;
+		if (add_lat > trcd_clk) {
+			add_lat = trcd_clk - 1;
+		}
 	}
-	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
-	switch(spd.refresh) {
-	case 0x00:
-	case 0x80:
-		tmp = picos_to_clk(15625000);
-		break;
-	case 0x01:
-	case 0x81:
-		tmp = picos_to_clk(3900000);
-		break;
-	case 0x02:
-	case 0x82:
-		tmp = picos_to_clk(7800000);
-		break;
-	case 0x03:
-	case 0x83:
-		tmp = picos_to_clk(31300000);
-		break;
-	case 0x04:
-	case 0x84:
-		tmp = picos_to_clk(62500000);
-		break;
-	case 0x05:
-	case 0x85:
-		tmp = picos_to_clk(125000000);
-		break;
-	default:
-		tmp = 0x512;
-		break;
+	/*
+	 * Write Data Delay
+	 * Historically 0x2 == 4/8 clock delay.
+	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+	 */
+	wr_data_delay = 3;
+
+	/*
+	 * Write Latency
+	 * Read to Precharge
+	 * Minimum CKE Pulse Width.
+	 * Four Activate Window
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		/*
+		 * This is a lie.  It should really be 1, but if it is
+		 * set to 1, bits overlap into the old controller's
+		 * otherwise unused ACSM field.  If we leave it 0, then
+		 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
+		 */
+		wr_lat = 0;
+
+		trtp_clk = 2;		/* By the book. */
+		cke_min_clk = 1;	/* By the book. */
+		four_act = 1;		/* By the book. */
+
+	} else {
+		wr_lat = caslat - 1;
+
+		/* Convert SPD value from quarter nanos to picos. */
+		trtp_clk = picos_to_clk(spd.trtp * 250);
+
+		cke_min_clk = 3;	/* By the book. */
+		four_act = picos_to_clk(37500);	/* By the book. 1k pages? */
+	}
+
+	/*
+	 * Empirically set ~MCAS-to-preamble override for DDR 2.
+	 * Your milage will vary.
+	 */
+	cpo = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		if (effective_data_rate == 266 || effective_data_rate == 333) {
+			cpo = 0x7;		/* READ_LAT + 5/4 */
+		} else if (effective_data_rate == 400) {
+			cpo = 0x9;		/* READ_LAT + 7/4 */
+		} else {
+			/* Pure speculation */
+			cpo = 0xb;
+		}
+	}
+
+	ddr->timing_cfg_2 = (0
+		| ((add_lat & 0x7) << 28)		/* ADD_LAT */
+		| ((cpo & 0x1f) << 23)			/* CPO */
+		| ((wr_lat & 0x7) << 19)		/* WR_LAT */
+		| ((trtp_clk & 0x7) << 13)		/* RD_TO_PRE */
+		| ((wr_data_delay & 0x7) << 10)		/* WR_DATA_DELAY */
+		| ((cke_min_clk & 0x7) << 6)		/* CKE_PLS */
+		| ((four_act & 0x1f) << 0)		/* FOUR_ACT */
+		);
+
+	debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
+
+
+	/*
+	 * Determine the Mode Register Set.
+	 *
+	 * This is nominally part specific, but it appears to be
+	 * consistent for all DDR I devices, and for all DDR II devices.
+	 *
+	 *     caslat must be programmed
+	 *     burst length is always 4
+	 *     burst type is sequential
+	 *
+	 * For DDR I:
+	 *     operating mode is "normal"
+	 *
+	 * For DDR II:
+	 *     other stuff
+	 */
+
+	mode_caslat = 0;
+
+	/*
+	 * Table lookup from DDR I or II Device Operation Specs.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		if (1 <= caslat && caslat <= 4) {
+			unsigned char mode_caslat_table[4] = {
+				0x5,	/* 1.5 clocks */
+				0x2,	/* 2.0 clocks */
+				0x6,	/* 2.5 clocks */
+				0x3	/* 3.0 clocks */
+			};
+			mode_caslat = mode_caslat_table[caslat - 1];
+		} else {
+			puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
+			     "2.5 and 3.0 clocks are supported.\n");
+			return 0;
+		}
+
+	} else {
+		if (2 <= caslat && caslat <= 5) {
+			mode_caslat = caslat;
+		} else {
+			puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
+			     "4.0 and 5.0 clocks are supported.\n");
+			return 0;
+		}
+	}
+
+	/*
+	 * Encoded Burst Lenght of 4.
+	 */
+	burst_len = 2;			/* Fiat. */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_auto_clk = 0;	/* Historical */
+	} else {
+		/*
+		 * Determine tCK max in picos.  Grab tWR and convert to picos.
+		 * Auto-precharge write recovery is:
+		 *	WR = roundup(tWR_ns/tCKmax_ns).
+		 *
+		 * Ponder: Is twr_auto_clk different than twr_clk?
+		 */
+		tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
+		twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
+	}
+
+
+	/*
+	 * Mode Reg in bits 16 ~ 31,
+	 * Extended Mode Reg 1 in bits 0 ~ 15.
+	 */
+	mode_odt_enable = 0x0;			/* Default disabled */
+	if (odt_wr_cfg || odt_rd_cfg) {
+		/*
+		 * Bits 6 and 2 in Extended MRS(1)
+		 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+		 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+		 */
+		mode_odt_enable = 0x40;		/* 150 Ohm */
 	}
 
+	ddr->sdram_mode =
+		(0
+		 | (add_lat << (16 + 3))	/* Additive Latency in EMRS1 */
+		 | (mode_odt_enable << 16)	/* ODT Enable in EMRS1 */
+		 | (twr_auto_clk << 9)		/* Write Recovery Autopre */
+		 | (mode_caslat << 4)		/* caslat */
+		 | (burst_len << 0)		/* Burst length */
+		 );
+
+	debug("DDR: sdram_mode   = 0x%08x\n", ddr->sdram_mode);
+
+
+	/*
+	 * Clear EMRS2 and EMRS3.
+	 */
+	ddr->sdram_mode_2 = 0;
+	debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
+
+
 	/*
-	 * Set BSTOPRE to 0x100 for page mode
-	 * If auto-charge is used, set BSTOPRE = 0
+	 * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
+	 * Table from SPD Spec, Byte 12, converted to picoseconds and
+	 * filled in with "default" normal values.
 	 */
-	ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
-	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
+	{
+		unsigned int refresh_clk;
+		unsigned int refresh_time_ns[8] = {
+			15625000,	/* 0 Normal    1.00x */
+			3900000,	/* 1 Reduced    .25x */
+			7800000,	/* 2 Extended   .50x */
+			31300000,	/* 3 Extended  2.00x */
+			62500000,	/* 4 Extended  4.00x */
+			125000000,	/* 5 Extended  8.00x */
+			15625000,	/* 6 Normal    1.00x  filler */
+			15625000,	/* 7 Normal    1.00x  filler */
+		};
+
+		refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
+
+		/*
+		 * Set BSTOPRE to 0x100 for page mode
+		 * If auto-charge is used, set BSTOPRE = 0
+		 */
+		ddr->sdram_interval =
+			(0
+			 | (refresh_clk & 0x3fff) << 16
+			 | 0x100
+			 );
+		debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
+	}
 
 	/*
 	 * Is this an ECC DDR chip?
+	 * But don't mess with it if the DDR controller will init mem.
 	 */
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	if (spd.config == 0x02) {
 		ddr->err_disable = 0x0000000d;
 		ddr->err_sbe = 0x00ff0000;
 	}
-	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
-	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
+	debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
+	debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
 #endif
-	asm("sync;isync;msync");
 
+	asm("sync;isync;msync");
 	udelay(500);
 
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
-	/* Setup the clock control (8555 and later)
-	 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
-	 * SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
+	/*
+	 * SDRAM Cfg 2
+	 */
+
+	/*
+	 * When ODT is enabled, Chap 9 suggests asserting ODT to
+	 * internal IOs only during reads.
+	 */
+	odt_cfg = 0;
+	if (odt_rd_cfg | odt_wr_cfg) {
+		odt_cfg = 0x2;		/* ODT to IOs during reads */
+	}
+
+	/*
+	 * Try to use differential DQS with DDR II.
 	 */
-	ddr->sdram_clk_cntl = 0x83000000;
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		dqs_cfg = 0;		/* No Differential DQS for DDR I */
+	} else {
+		dqs_cfg = 0x1;		/* Differential DQS for DDR II */
+	}
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Use the DDR controller to auto initialize memory.
+	 */
+	d_init = 1;
+	ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
+	debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
+#else
+	/*
+	 * Memory will be initialized via DMA, or not at all.
+	 */
+	d_init = 0;
+#endif
+
+	ddr->sdram_cfg_2 = (0
+			    | (dqs_cfg << 26)	/* Differential DQS */
+			    | (odt_cfg << 21)	/* ODT */
+			    | (d_init << 4)	/* D_INIT auto init DDR */
+			    );
+
+	debug("DDR: sdram_cfg_2  = 0x%08x\n", ddr->sdram_cfg_2);
+
+
+#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
+	{
+		unsigned char clk_adjust;
+
+		/*
+		 * Setup the clock control.
+		 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+		 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+		 *	0110	3/4 cycle late
+		 *	0111	7/8 cycle late
+		 */
+		if (spd.mem_type == SPD_MEMTYPE_DDR) {
+			clk_adjust = 0x6;
+		} else {
+			clk_adjust = 0x7;
+		}
+
+		ddr->sdram_clk_cntl = (0
+			       | 0x80000000
+			       | (clk_adjust << 23)
+			       );
+		debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
+	}
 #endif
 
 	/*
-	 * Figure out the settings for the sdram_cfg register.  Build up
-	 * the entire register in 'tmp' before writing since the write into
-	 * the register will actually enable the memory controller, and all
-	 * settings must be done before enabling.
+	 * Figure out the settings for the sdram_cfg register.
+	 * Build up the entire register in 'sdram_cfg' before writing
+	 * since the write into the register will actually enable the
+	 * memory controller; all settings must be done before enabling.
 	 *
 	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
 	 * sdram_cfg[1]   = 1 (self-refresh-enable)
-	 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+	 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+	 *			010 DDR 1 SDRAM
+	 *			011 DDR 2 SDRAM
 	 */
-	tmp = 0xc2000000;
+	sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
+	sdram_cfg = (0
+		     | (1 << 31)			/* Enable */
+		     | (1 << 30)			/* Self refresh */
+		     | (sdram_type << 24)		/* SDRAM type */
+		     );
 
 	/*
 	 * sdram_cfg[3] = RD_EN - registered DIMM enable
 	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
 	 */
-	if (spd.mod_attr == 0x26) {
-		tmp |= 0x10000000;
+	if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
+		sdram_cfg |= 0x10000000;		/* RD_EN */
 	}
 
 #if defined(CONFIG_DDR_ECC)
@@ -369,7 +891,7 @@ spd_sdram(void)
 	 * If the user wanted ECC (enabled via sdram_cfg[2])
 	 */
 	if (spd.config == 0x02) {
-		tmp |= 0x20000000;
+		sdram_cfg |= 0x20000000;		/* ECC_EN */
 	}
 #endif
 
@@ -385,27 +907,160 @@ spd_sdram(void)
 			/*
 			 * Enable 2T timing by setting sdram_cfg[16].
 			 */
-			tmp |= 0x8000;
+			sdram_cfg |= 0x8000;		/* 2T_EN */
 #endif
 		}
 	}
 
-	ddr->sdram_cfg = tmp;
+	/*
+	 * 200 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 */
+	udelay(200);
+
+	/*
+	 * Go!
+	 */
+	ddr->sdram_cfg = sdram_cfg;
 
 	asm("sync;isync;msync");
 	udelay(500);
 
-	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
+	debug("DDR: sdram_cfg   = 0x%08x\n", ddr->sdram_cfg);
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+		udelay(1000);
+	}
+#endif
+
+
+	/*
+	 * Figure out memory size in Megabytes.
+	 */
+	memsize = n_ranks * rank_density / 0x100000;
+
+	/*
+	 * Establish Local Access Window and TLB mappings for DDR memory.
+	 */
+	memsize = setup_laws_and_tlbs(memsize);
+	if (memsize == 0) {
+		return 0;
+	}
 
 	return memsize * 1024 * 1024;
 }
+
+
+/*
+ * Setup Local Access Window and TLB1 mappings for the requested
+ * amount of memory.  Returns the amount of memory actually mapped
+ * (usually the original request size), or 0 on error.
+ */
+
+static unsigned int
+setup_laws_and_tlbs(unsigned int memsize)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	unsigned int tlb_size;
+	unsigned int law_size;
+	unsigned int ram_tlb_index;
+	unsigned int ram_tlb_address;
+
+	/*
+	 * Determine size of each TLB1 entry.
+	 */
+	switch (memsize) {
+	case 16:
+	case 32:
+		tlb_size = BOOKE_PAGESZ_16M;
+		break;
+	case 64:
+	case 128:
+		tlb_size = BOOKE_PAGESZ_64M;
+		break;
+	case 256:
+	case 512:
+	case 1024:
+	case 2048:
+		tlb_size = BOOKE_PAGESZ_256M;
+		break;
+	default:
+		puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
+
+		/*
+		 * The memory was not able to be mapped.
+		 */
+		return 0;
+		break;
+	}
+
+	/*
+	 * Configure DDR TLB1 entries.
+	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
+	 */
+	ram_tlb_index = 8;
+	ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+	while (ram_tlb_address < (memsize * 1024 * 1024)
+	      && ram_tlb_index < 16) {
+		mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
+		mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
+		mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
+				      0, 0, 0, 0, 0, 0, 0, 0));
+		mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
+				      0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+		asm volatile("isync;msync;tlbwe;isync");
+
+		debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
+		debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
+		debug("DDR: MAS2=0x%08x\n",
+		      TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
+				0, 0, 0, 0, 0, 0, 0, 0));
+		debug("DDR: MAS3=0x%08x\n",
+		      TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
+				0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+
+		ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+		ram_tlb_index++;
+	}
+
+
+	/*
+	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.  Fnord.
+	 */
+	law_size = 19 + __ilog2(memsize);
+
+	/*
+	 * Set up LAWBAR for all of DDR.
+	 */
+	ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+	ecm->lawar1 = (LAWAR_EN
+		       | LAWAR_TRGT_IF_DDR
+		       | (LAWAR_SIZE & law_size));
+	debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
+	debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
+
+	/*
+	 * Confirm that the requested amount of memory was mapped.
+	 */
+	return memsize;
+}
+
 #endif /* CONFIG_SPD_EEPROM */
 
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+
 /*
  * Initialize all of memory for ECC, then enable errors.
  */
+
 void
 ddr_enable_ecc(unsigned int dram_size)
 {
@@ -420,7 +1075,7 @@ ddr_enable_ecc(unsigned int dram_size)
 		if (((unsigned int)p & 0x1f) == 0) {
 			ppcDcbz((unsigned long) p);
 		}
-		*p = (unsigned int)0xdeadbeef;
+		*p = (unsigned int)CONFIG_MEM_INIT_VALUE;
 		if (((unsigned int)p & 0x1c) == 0x1c) {
 			ppcDcbf((unsigned long) p);
 		}
@@ -454,7 +1109,10 @@ ddr_enable_ecc(unsigned int dram_size)
 	/*
 	 * Enable errors for ECC.
 	 */
+	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
 	ddr->err_disable = 0x00000000;
 	asm("sync;isync;msync");
+	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
 }
-#endif	/* CONFIG_DDR_ECC */
+
+#endif	/* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 787f7fa..d736742 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -82,7 +82,7 @@ int get_clocks (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	sys_info_t sys_info;
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	uint sccr, dfbrg;
 
@@ -94,7 +94,7 @@ int get_clocks (void)
 	get_sys_info (&sys_info);
 	gd->cpu_clk = sys_info.freqProcessor;
 	gd->bus_clk = sys_info.freqSystemBus;
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	gd->vco_out = 2*sys_info.freqSystemBus;
 	gd->cpm_clk = gd->vco_out / 2;
 	gd->scc_clk = gd->vco_out / 4;
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index af28ebe..5f75bc1 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -155,11 +155,13 @@ _start_e500:
 	mtspr	MCSR,r0
 	mtspr	DEAR,r0
 
-	mtspr	DBCR0,r0
+	/* not needed and conflicts with some debuggers */
+	/* mtspr	DBCR0,r0 */
 	mtspr	DBCR1,r0
 	mtspr	DBCR2,r0
-	mtspr	IAC1,r0
-	mtspr	IAC2,r0
+	/* not needed and conflicts with some debuggers */
+	/* mtspr	IAC1,r0 */
+	/* mtspr	IAC2,r0 */
 	mtspr	DAC1,r0
 	mtspr	DAC2,r0
 
@@ -174,6 +176,9 @@ _start_e500:
 	mtspr	BUCSR,r0	/* disable branch prediction */
 	mtspr	MAS4,r0
 	mtspr	MAS6,r0
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+	mtspr	MAS7,r0
+#endif
 	isync
 
 	/* Setup interrupt vectors */
@@ -358,6 +363,9 @@ _start:
 	/* Enable Time Base and Select Time Base Clock */
 	lis	r0,HID0_EMCP@h		/* Enable machine check */
 	ori	r0,r0,0x4000		/* time base is processor clock */
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+	ori	r0,r0,0x0080		/* enable MAS7 updates */
+#endif
 	mtspr	HID0,r0
 
 #if defined(CONFIG_ADDR_STREAMING)
diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads
new file mode 100644
index 0000000..3d38397
--- /dev/null
+++ b/doc/README.mpc83xxads
@@ -0,0 +1,96 @@
+Freescale MPC83xx ADS Boards
+-----------------------------------------
+
+0. Toolchain / Building
+
+    % setenv CROSS_COMPILE /usr/powerpc/bin/powerpc-linux-
+
+    % /usr/powerpc/bin/powerpc-linux-gcc -v
+    Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs
+    Configured with: ../configure --prefix=/usr/powerpc
+    --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared
+    --disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc
+    Thread model: posix
+    gcc version 3.4.3 (Debian)
+
+    % /usr/powerpc/bin/powerpc-linux-as -v
+    GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15
+
+
+    % make MPC8349ADS_config
+    Configuring for MPC8349ADS board...
+
+    % make
+
+
+1. Board Switches and Jumpers
+
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+     0x0000_0000     0x7fff_ffff     DDR		     2G
+     0x8000_0000     0x9fff_ffff     PCI MEM		     512M
+     0xc000_0000     0xdfff_ffff     Rapid IO		     512M
+     0xe000_0000     0xe00f_ffff     CCSR		     1M
+     0xe200_0000     0xe2ff_ffff     PCI IO		     16M
+     0xf000_0000     0xf7ff_ffff     SDRAM		     128M
+     0xf800_0000     0xf80f_ffff     BCSR		     1M
+     0xfe00_0000     0xffff_ffff     FLASH (boot bank)	     16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC8349ADS.h
+
+    CONFIG_MPC83xx	    MPC83xx family
+    CONFIG_MPC8349	    MPC8349 specific
+    CONFIG_MPC8349ADS	    MPC8349ADS board specific
+    CONFIG_TSEC_ENET	    Use on-chip 10/100/1000 ethernet
+
+
+4. Compilation
+
+    Assuming you're using BASH shell:
+
+	export CROSS_COMPILE=your-cross-compile-prefix
+	cd u-boot
+	make distclean
+	make MPC8349ADS_config
+	make
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+	loadb
+	[Drop to kermit:
+	    ^\c
+	    send <u-boot-bin-image>
+	    c
+	]
+
+
+    Or via tftp:
+
+        tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+    tftp 10000 u-boot.bin
+    protect off fe000000 fe09ffff
+    erase fe000000 fe09ffff
+
+    cp.b 10000 fe000000 xxxx
+or
+    cp.b 10000 fe000000 a0000
+
+You might have to supply the correct byte count for 'xxxx' from
+the TFTP.  Maybe a0000 will work too, that corresponds to the
+erased sectors.
+
+
+6. Notes
diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads
index 939de20..08d6831 100644
--- a/doc/README.mpc85xxads
+++ b/doc/README.mpc85xxads
@@ -134,7 +134,6 @@ Updated 13-July-2004 Jon Loeliger
     CONFIG_E500		    BOOKE e500 family(Motorola)
     CONFIG_MPC85xx	    MPC8540,MPC8560 and their derivatives
     CONFIG_MPC8540	    MPC8540 specific
-    CONFIG_MPC8560	    MPC8560 specific
     CONFIG_MPC8540ADS	    MPC8540ADS board specific
     CONFIG_MPC8560ADS	    MPC8560ADS board specific
     CONFIG_TSEC_ENET	    Use on-chip 10/100/1000 ethernet for networking
@@ -144,6 +143,7 @@ Updated 13-July-2004 Jon Loeliger
     CONFIG_DDR_ECC	    only for ECC DDR module
     CONFIG_DDR_DLL	    DLL fix on some ADS boards needed for more
 			    stability.
+    CONFIG_HAS_FEC	    If an FEC is on chip, set to 1, else 0.
 
 Other than the above definitions, the rest in the config files are
 straightforward.
@@ -191,10 +191,10 @@ straightforward.
 
 4.4 Reflash U-boot Image using U-boot
 
-    => tftp 10000 u-boot.bin
-    => protect off fff80000 ffffffff
-    => erase fff80000 ffffffff
-    => cp.b 10000 fff80000 80000
+    tftp 10000 u-boot.bin
+    protect off fff80000 ffffffff
+    erase fff80000 ffffffff
+    cp.b 10000 fff80000 80000
 
 
 4.5 Reflash U-Boot with a BDI-2000
diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds
index e0f4916..bc5db0c 100644
--- a/doc/README.mpc85xxcds
+++ b/doc/README.mpc85xxcds
@@ -135,8 +135,8 @@ The default setting of all switches on the carrier board is:
   SW4=10001000
 
 
-CPU Card Switches
------------------
+8555/41 CPU Card Switches
+-------------------------
 
 Most switches on the CPU Card should not be changed.  However, the
 frequency can be changed by setting SW3:
@@ -160,6 +160,45 @@ A safe default setting for all switches on the CPU board is:
   SW4=11111110
 
 
+8548 CPU Card Switches
+----------------------
+And, just to be confusing, in this set of switches:
+
+    ON  = 1
+    OFF = 0
+
+Default
+  SW1=11111101
+  SW2=10011111
+  SW3=11001000    (8X) (2:1)
+  SW4=11110011
+
+  SW3=X000XXXX  == CORE:CCB    4:1
+      X001XXXX  == CORE:CCB    9:2
+      X010XXXX  == CORE:CCB    1:1
+      X011XXXX  == CORE:CCB    3:2
+      X100XXXX  == CORE:CCB    2:1
+      X101XXXX  == CORE:CCB    5:2
+      X110XXXX  == CORE:CCB    3:1
+      X111XXXX  == CORE:CCB    7:2
+      XXXX0000  == CCB:SYSCLK 16:1
+      XXXX0001  == RESERVED
+      XXXX0010  == CCB:SYSCLK  2:1
+      XXXX0011  == CCB:SYSCLK  3:1
+      XXXX0100  == CCB:SYSCLK  4:1
+      XXXX0101  == CCB:SYSCLK  5:1
+      XXXX0110  == CCB:SYSCLK  6:1
+      XXXX0111  == RESERVED
+      XXXX1000  == CCB:SYSCLK  8:1
+      XXXX1001  == CCB:SYSCLK  9:1
+      XXXX1010  == CCB:SYSCLK 10:1
+      XXXX1011  == RESERVED
+      XXXX1100  == CCB:SYSCLK 12:1
+      XXXX1101  == CCB:SYSCLK 20:1
+      XXXX1110  == RESERVED
+      XXXX1111  == RESERVED
+
+
 eDINK Info
 ----------
 
diff --git a/drivers/Makefile b/drivers/Makefile
index 3461bb1..26a556e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -45,7 +45,7 @@ OBJS	= 3c589.o 5701rls.o ali512x.o \
 	  serial_pl010.o serial_pl011.o serial_xuartlite.o \
 	  sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
 	  status_led.o sym53c8xx.o \
-	  ti_pci1410a.o tigon3.o \
+	  ti_pci1410a.o tigon3.o tsec.o \
 	  usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
 	  videomodes.o w83c553f.o \
 	  ks8695eth.o
diff --git a/cpu/mpc85xx/tsec.c b/drivers/tsec.c
index d327a6d..0c8b0de 100644
--- a/cpu/mpc85xx/tsec.c
+++ b/drivers/tsec.c
@@ -8,7 +8,6 @@
  *
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2003, Motorola, Inc.
- * maintained by Jon Loeliger (loeliger@freescale.com)
  * author Andy Fleming
  *
  */
@@ -35,7 +34,7 @@ typedef volatile struct rtxbd {
 
 struct tsec_info_struct {
 	unsigned int phyaddr;
-	unsigned int gigabit;
+	u32 flags;
 	unsigned int phyregidx;
 };
 
@@ -48,8 +47,9 @@ struct tsec_info_struct {
  *  phyaddr - The address of the PHY which is attached to
  *	the given device.
  *
- *  gigabit - This variable indicates whether the device
- *	supports gigabit speed ethernet
+ *  flags - This variable indicates whether the device
+ *	supports gigabit speed ethernet, and whether it should be
+ *	in reduced mode.
  *
  *  phyregidx - This variable specifies which ethernet device
  *	controls the MII Management registers which are connected
@@ -69,24 +69,33 @@ struct tsec_info_struct {
  *   FEC_PHYIDX
  */
 static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_MPC85XX_TSEC1
-	{TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
+#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
+	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
 #else
 	{ 0, 0, 0},
 #endif
-#ifdef CONFIG_MPC85XX_TSEC2
-	{TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
+#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
+	{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
 #else
 	{ 0, 0, 0},
 #endif
 #ifdef CONFIG_MPC85XX_FEC
 	{FEC_PHY_ADDR, 0, FEC_PHYIDX},
 #else
+#    if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
+	{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
+#    else
 	{ 0, 0, 0},
+#    endif
+#    if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
+	{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
+#    else
+	{ 0, 0, 0},
+#    endif
 #endif
 };
 
-#define MAXCONTROLLERS 3
+#define MAXCONTROLLERS	(4)
 
 static int relocated = 0;
 
@@ -115,7 +124,7 @@ static void relocate_cmds(void);
 /* Initialize device structure. Returns success if PHY
  * initialization succeeded (i.e. if it recognizes the PHY)
  */
-int tsec_initialize(bd_t *bis, int index)
+int tsec_initialize(bd_t *bis, int index, char *devname)
 {
 	struct eth_device* dev;
 	int i;
@@ -139,9 +148,9 @@ int tsec_initialize(bd_t *bis, int index)
 			tsec_info[index].phyregidx*TSEC_SIZE);
 
 	priv->phyaddr = tsec_info[index].phyaddr;
-	priv->gigabit = tsec_info[index].gigabit;
+	priv->flags = tsec_info[index].flags;
 
-	sprintf(dev->name, "ENET%d", index);
+	sprintf(dev->name, devname);
 	dev->iobase = 0;
 	dev->priv   = priv;
 	dev->init   = tsec_init;
@@ -226,7 +235,7 @@ void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
 
 	regbase->miimadd = (phyid << 8) | regnum;
 	regbase->miimcon = value;
-	asm("msync");
+	asm("sync");
 
 	timeout=1000000;
 	while((regbase->miimind & MIIMIND_BUSY) && timeout--);
@@ -251,11 +260,11 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum)
 
 	/* Clear the command register, and wait */
 	regbase->miimcom = 0;
-	asm("msync");
+	asm("sync");
 
 	/* Initiate a read command, and wait */
 	regbase->miimcom = MIIM_READ_COMMAND;
-	asm("msync");
+	asm("sync");
 
 	/* Wait for the the indication that the read is done */
 	while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
@@ -283,14 +292,14 @@ static int init_phy(struct eth_device *dev)
 		regs->tbipa = TBIPA_VALUE;
 		regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 		regs->tbipa = TBIPA_VALUE;
-		asm("msync");
+		asm("sync");
 	}
 
 	/* Reset MII (due to new addresses) */
 	priv->phyregs->miimcfg = MIIMCFG_RESET;
-	asm("msync");
+	asm("sync");
 	priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
-	asm("msync");
+	asm("sync");
 	while(priv->phyregs->miimind & MIIMIND_BUSY);
 
 	if(0 == relocated)
@@ -318,7 +327,7 @@ static int init_phy(struct eth_device *dev)
 /* For 10/100, the value is slightly different */
 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
 {
-	if(priv->gigabit)
+	if(priv->flags & TSEC_GIGABIT)
 		return MIIM_CONTROL_INIT;
 	else
 		return MIIM_CR_INIT;
@@ -429,7 +438,7 @@ uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
 	for(phyid=0;phyid<4;phyid++) {
 		regbase->miimadd = (phyid << 8) | mii_reg;
 		regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
-		asm("msync");
+		asm("sync");
 
 		timeout=1000000;
 		while((regbase->miimind & MIIMIND_BUSY) && timeout--);
@@ -438,6 +447,13 @@ uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
 	return MIIM_CIS8204_SLEDCON_INIT;
 }
 
+uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
+{
+	if (priv->flags & TSEC_REDUCED)
+		return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
+	else
+		return MIIM_CIS8204_EPHYCON_INIT;
+}
 
 /* Initialized required registers to appropriate values, zeroing
  * those we don't care about (unless zero is bad, in which case,
@@ -507,6 +523,15 @@ static void adjust_link(struct eth_device *dev)
 			case 10:
 				regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
 					| MACCFG2_MII);
+
+				/* If We're in reduced mode, we need
+				 * to say whether we're 10 or 100 MB.
+				 */
+				if ((priv->speed == 100)
+				    && (priv->flags & TSEC_REDUCED))
+					regs->ecntrl |= ECNTRL_R100;
+				else
+					regs->ecntrl &= ~(ECNTRL_R100);
 				break;
 			default:
 				printf("%s: Speed was bad\n", dev->name);
@@ -731,7 +756,7 @@ struct phy_info phy_info_cis8204 = {
 		/* Configure some basic stuff */
 		{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 		{MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
-		{MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
+		{MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
 		{miim_end,}
 	},
 	(struct phy_cmd[]) { /* startup */
diff --git a/cpu/mpc85xx/tsec.h b/drivers/tsec.h
index e24351a..15961d7 100644
--- a/cpu/mpc85xx/tsec.h
+++ b/drivers/tsec.h
@@ -18,11 +18,22 @@
 #define __TSEC_H
 
 #include <net.h>
-#include <mpc85xx.h>
+#include <config.h>
+
+#ifndef CFG_TSEC1_OFFSET
+    #define CFG_TSEC1_OFFSET	(0x24000)
+#endif
 
-#define TSEC_BASE_ADDR	(CFG_IMMR + 0x24000)
 #define TSEC_SIZE	0x01000
 
+/* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
+#if defined(CONFIG_MPC85xx)
+    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
+#elif defined(CONFIG_MPC83XX)
+    #define TSEC_BASE_ADDR	(CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#endif
+
+
 #define MAC_ADDR_LEN 6
 
 /* #define TSEC_TIMEOUT 	1000000 */
@@ -51,6 +62,7 @@
 
 #define ECNTRL_INIT_SETTINGS	0x00001000
 #define ECNTRL_TBI_MODE         0x00000020
+#define ECNTRL_R100		0x00000008
 
 #define miim_end -2
 #define miim_read -1
@@ -107,6 +119,7 @@
 /* Cicada 8204 Extended PHY Control Register 1 */
 #define MIIM_CIS8204_EPHY_CON		0x17
 #define MIIM_CIS8204_EPHYCON_INIT	0x0006
+#define MIIM_CIS8204_EPHYCON_RGMII	0x1000
 
 /* Cicada 8204 Serial LED Control Register */
 #define MIIM_CIS8204_SLED_CON		0x1b
@@ -424,12 +437,18 @@ typedef struct tsec
 	uint	resc00[256];
 } tsec_t;
 
+#define TSEC_GIGABIT (1)
+
+/* This flag currently only has
+ * meaning if we're using the eTSEC */
+#define TSEC_REDUCED (1 << 1)
+
 struct tsec_private {
 	volatile tsec_t *regs;
 	volatile tsec_t *phyregs;
 	struct phy_info *phyinfo;
 	uint phyaddr;
-	uint gigabit;
+	u32 flags;
 	uint link;
 	uint duplexity;
 	uint speed;
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
new file mode 100644
index 0000000..908007c
--- /dev/null
+++ b/include/asm-ppc/e300.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ * Liberty Eran (liberty@freescale.com)
+ */
+
+#ifndef	__E300_H__
+#define __E300_H__
+
+/*
+ * e300 Processor Version & Revision Numbers
+ */
+#define PVR_83xx 0x80830000
+#define PVR_8349_REV10 (PVR_83xx | 0x0010)
+#define PVR_8349_REV11 (PVR_83xx | 0x0011)
+
+/*
+ * Hardware Implementation-Dependent Register 0 (HID0)
+ */
+
+/* #define HID0 1008 already defined in processor.h */
+#define HID0_MASK_MACHINE_CHECK              0x00000000
+#define HID0_ENABLE_MACHINE_CHECK            0x80000000
+
+#define HID0_DISABLE_CACHE_PARITY            0x00000000
+#define HID0_ENABLE_CACHE_PARITY             0x40000000
+
+#define HID0_DISABLE_ADDRESS_PARITY          0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY           0x20000000
+
+#define HID0_DISABLE_DATA_PARITY             0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY              0x10000000
+
+#define HID0_CORE_CLK_OUT                    0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2              0x08000000
+
+#define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
+#define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
+
+#define HID0_DISABLE_DOSE_MODE               0x00000000
+#define HID0_ENABLE_DOSE_MODE                0x00800000
+
+#define HID0_DISABLE_NAP_MODE                0x00000000
+#define HID0_ENABLE_NAP_MODE                 0x00400000
+
+#define HID0_DISABLE_SLEEP_MODE              0x00000000
+#define HID0_ENABLE_SLEEP_MODE               0x00200000
+
+#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
+#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
+
+#define HID0_SOFT_RESET                      0x00010000
+
+#define HID0_DISABLE_INSTRUCTION_CACHE       0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE        0x00008000
+
+#define HID0_DISABLE_DATA_CACHE              0x00000000
+#define HID0_ENABLE_DATA_CACHE               0x00004000
+
+#define HID0_LOCK_INSTRUCTION_CACHE          0x00002000
+
+#define HID0_LOCK_DATA_CACHE                 0x00001000
+
+#define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
+
+#define HID0_INVALIDATE_DATA_CACHE           0x00000400
+
+#define HID0_DISABLE_M_BIT                   0x00000000
+#define HID0_ENABLE_M_BIT                    0x00000080
+
+#define HID0_FBIOB                           0x00000010
+
+#define HID0_DISABLE_ADDRESS_BROADCAST       0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST        0x00000008
+
+#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
+#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
+
+/*
+ * Hardware Implementation-Dependent Register 2 (HID2)
+ */
+#define HID2		1011
+
+#define HID2_LET       0x08000000
+#define HID2_HBE       0x00040000
+#define HID2_IWLCK_000 0x00000000 /* no ways locked */
+#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
+#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
+#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
+#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
+#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
+#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
+
+
+/* BAT (block address translation */
+#define BATU_BEPI_MSK	    0xfffe0000
+#define BATU_BL_MSK         0x00001ffc
+
+#define BATU_BL_128K        0x00000000
+#define BATU_BL_256K        0x00000004
+#define BATU_BL_512K        0x0000000c
+#define BATU_BL_1M          0x0000001c
+#define BATU_BL_2M          0x0000003c
+#define BATU_BL_4M          0x0000007c
+#define BATU_BL_8M          0x000000fc
+#define BATU_BL_16M         0x000001fc
+#define BATU_BL_32M         0x000003fc
+#define BATU_BL_64M         0x000007fc
+#define BATU_BL_128M        0x00000ffc
+#define BATU_BL_256M        0x00001ffc
+
+#define BATU_VS             0x00000002
+#define BATU_VP             0x00000001
+
+#define BATL_BRPN_MSK       0xfffe0000
+#define BATL_WIMG_MSK       0x00000078
+
+#define BATL_WRITETHROUGH   0x00000040
+#define BATL_CACHEINHIBIT   0x00000020
+#define BATL_MEMCOHERENCE   0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+
+#define BATL_PP_MSK         0x00000003
+#define BATL_PP_00          0x00000000 /* No access */
+#define BATL_PP_01          0x00000001 /* Read-only */
+#define BATL_PP_10          0x00000002 /* Read-write */
+#define BATL_PP_11        	0x00000003
+
+#endif	/* __E300_H__ */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index c800f63..9681a74 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -23,6 +23,9 @@
 
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
+
+#include "asm/types.h"
+
 /*
  * The following data structure is placed in some memory wich is
  * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
@@ -39,13 +42,27 @@ typedef	struct	global_data {
 	unsigned long	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
 	unsigned long	bus_clk;
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	/* There are many clocks on the MPC8260 - see page 9-5 */
 	unsigned long	vco_out;
 	unsigned long	cpm_clk;
 	unsigned long	scc_clk;
 	unsigned long	brg_clk;
 #endif
+#if defined(CONFIG_MPC83XX)
+	/* There are other clocks in the MPC83XX */
+	u32 csb_clk;
+	u32 tsec1_clk;
+	u32 tsec2_clk;
+	u32 core_clk;
+	u32 usbmph_clk;
+	u32 usbdr_clk;
+	u32 i2c_clk;
+	u32 enc_clk;
+	u32 lbiu_clk;
+	u32 lclk_clk;
+	u32 ddr_clk;
+#endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
 	unsigned long	pci_clk;
@@ -64,7 +81,7 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
 	unsigned int	dp_alloc_base;
 	unsigned int	dp_alloc_top;
 #endif
diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
new file mode 100644
index 0000000..2a4ac0f
--- /dev/null
+++ b/include/asm-ppc/i2c.h
@@ -0,0 +1,103 @@
+/*
+ * Freescale I2C Controller
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003, Motorola, Inc.
+ * author: Eran Liberty (liberty@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_I2C_H_
+#define _ASM_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct i2c
+{
+    u8 adr;          /**< I2C slave address              */
+#define I2C_ADR	      0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES   ~(I2C_ADR)
+    u8 res0[3];
+    u8 fdr;          /**< I2C frequency divider register */
+#define IC2_FDR       0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES   ~(IC2_FDR)
+    u8 res1[3];
+    u8 cr;           /**< I2C control redister           */
+#define I2C_CR_MEN	  0x80
+#define I2C_CR_MIEN	  0x40
+#define I2C_CR_MSTA   0x20
+#define I2C_CR_MTX    0x10
+#define I2C_CR_TXAK   0x08
+#define I2C_CR_RSTA   0x04
+#define I2C_CR_BCST   0x01
+    u8 res2[3];
+    u8 sr;           /**< I2C status register            */
+#define I2C_SR_MCF    0x80
+#define I2C_SR_MAAS   0x40
+#define I2C_SR_MBB    0x20
+#define I2C_SR_MAL    0x10
+#define I2C_SR_BCSTM  0x08
+#define I2C_SR_SRW    0x04
+#define I2C_SR_MIF    0x02
+#define I2C_SR_RXAK   0x01
+    u8 res3[3];
+    u8 dr;           /**< I2C data register              */
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+    u8 res4[3];
+    u8 dfsrr;        /**< I2C digital filter sampling rate register */
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+    u8 res5[3];
+    u8 res6[0xE8];
+} i2c_t;
+
+#ifndef CFG_HZ
+#error CFG_HZ is not defined in /include/configs/${BOARD}.h
+#endif
+#define I2C_TIMEOUT (CFG_HZ/4)
+
+#ifndef CFG_IMMRBAR
+#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifndef CFG_I2C_OFFSET
+#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifdef CONFIG_MPC8349ADS
+/*
+ * MPC8349 have two i2c bus
+ */
+extern i2c_t * mpc8349_i2c;
+#define I2C mpc8349_i2c
+#else
+#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
+#endif
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+#endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
new file mode 100644
index 0000000..5d284d4
--- /dev/null
+++ b/include/asm-ppc/immap_83xx.h
@@ -0,0 +1,1060 @@
+/*
+ * MPC8349 Internal Memory Map
+ * Copyright (c) 2004 Freescale Semiconductor.
+ * Eran Liberty (liberty@freescale.com)
+ *
+ * based on:
+ * - MPC8260 Internal Memory Map
+ *   Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ * - MPC85xx Internal Memory Map
+ *   Copyright(c) 2002,2003 Motorola Inc.
+ *   Xianghua Xiao (x.xiao@motorola.com)
+ */
+#ifndef __IMMAP_8349__
+#define __IMMAP_8349__
+
+#include <asm/types.h>
+#include <asm/i2c.h>
+
+/*
+ * Local Access Window.
+ */
+typedef struct law8349 {
+	u32 bar; /* LBIU local access window base address register */
+/* Identifies the 20 most-significant address bits of the base of local
+ * access window n. The specified base address should be aligned to the
+ * window size, as defined by LBLAWARn[SIZE].
+ */
+#define LAWBAR_BAR         0xFFFFF000
+#define LAWBAR_RES	     ~(LAWBAR_BAR)
+	u32 ar; /* LBIU local access window attribute register */
+/*
+ * This Macro were moved into mmu.h
+ */
+#if 0
+/* 0 The local bus local access window n is disabled. 1 The local bus
+ * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
+ * combine to identify an address range for this window.
+ */
+#define LAWAR_EN           0x80000000
+/* Identifies the size of the window from the starting address. Window
+ * size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is
+ * undefined.
+ */
+#define LAWAR_SIZE         0x0000003F
+#define	LAWAR_SIZE_4K	0x0000000B
+#define	LAWAR_SIZE_8K	0x0000000C
+#define	LAWAR_SIZE_16K	0x0000000D
+#define	LAWAR_SIZE_32K	0x0000000E
+#define	LAWAR_SIZE_64K	0x0000000F
+#define	LAWAR_SIZE_128K	0x00000010
+#define	LAWAR_SIZE_256K	0x00000011
+#define	LAWAR_SIZE_512K	0x00000012
+#define	LAWAR_SIZE_1M	0x00000013
+#define	LAWAR_SIZE_2M	0x00000014
+#define	LAWAR_SIZE_4M	0x00000015
+#define	LAWAR_SIZE_8M	0x00000016
+#define	LAWAR_SIZE_16M	0x00000017
+#define	LAWAR_SIZE_32M	0x00000018
+#define	LAWAR_SIZE_64M	0x00000019
+#define	LAWAR_SIZE_128M	0x0000001A
+#define	LAWAR_SIZE_256M	0x0000001B
+#define	LAWAR_SIZE_512M	0x0000001C
+#define	LAWAR_SIZE_1G	0x0000001D
+#define	LAWAR_SIZE_2G	0x0000001E
+#define LAWAR_RES          ~(LAWAR_EN|LAWAR_SIZE)
+#endif
+
+} law8349_t;
+
+/*
+ * System configuration registers.
+ */
+typedef struct sysconf8349 {
+	u32 immrbar; /* Internal memory map base address register */
+	u8 res0[0x04];
+	u32 altcbar; /* Alternate configuration base address register */
+/* Identifies the12 most significant address bits of an alternate base
+ * address used for boot sequencer configuration accesses.
+ */
+#define ALTCBAR_BASE_ADDR     0xFFF00000
+#define ALTCBAR_RES           ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
+	u8 res1[0x14];
+	law8349_t lblaw[4]; /* LBIU local access window */
+	u8 res2[0x20];
+	law8349_t pcilaw[2]; /* PCI local access window */
+	u8 res3[0x30];
+	law8349_t ddrlaw[2]; /* DDR local access window */
+	u8 res4[0x50];
+	u32 sgprl; /* System General Purpose Register Low */
+	u32 sgprh; /* System General Purpose Register High */
+	u32 spridr; /* System Part and Revision ID Register */
+#define SPRIDR_PARTID         0xFFFF0000 /* Part Identification. */
+#define SPRIDR_REVID          0x0000FFFF /* Revision Identification. */
+	u8 res5[0x04];
+	u32 spcr; /* System Priority Configuration Register */
+#define SPCR_PCIHPE   0x10000000 /* PCI Highest Priority Enable. */
+#define SPCR_PCIPR    0x03000000 /* PCI bridge system bus request priority. */
+#define SPCR_TBEN     0x00400000 /* E300 PowerPC core time base unit enable. */
+#define SPCR_COREPR   0x00300000 /* E300 PowerPC Core system bus request priority. */
+#define SPCR_TSEC1DP  0x00003000 /* TSEC1 data priority. */
+#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
+#define SPCR_TSEC1EP  0x00000300 /* TSEC1 emergency priority. */
+#define SPCR_TSEC2DP  0x00000030 /* TSEC2 data priority. */
+#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
+#define SPCR_TSEC2EP  0x00000003 /* TSEC2 emergency priority. */
+#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
+			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
+			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
+	u32 sicrl; /* System General Purpose Register Low */
+#define SICRL_LDP_A   0x80000000
+#define SICRL_USB0    0x40000000
+#define SICRL_USB1    0x20000000
+#define SICRL_UART    0x0C000000
+#define SICRL_GPIO1_A 0x02000000
+#define SICRL_GPIO1_B 0x01000000
+#define SICRL_GPIO1_C 0x00800000
+#define SICRL_GPIO1_D 0x00400000
+#define SICRL_GPIO1_E 0x00200000
+#define SICRL_GPIO1_F 0x00180000
+#define SICRL_GPIO1_G 0x00040000
+#define SICRL_GPIO1_H 0x00020000
+#define SICRL_GPIO1_I 0x00010000
+#define SICRL_GPIO1_J 0x00008000
+#define SICRL_GPIO1_K 0x00004000
+#define SICRL_GPIO1_L 0x00003000
+#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
+			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
+			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
+			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
+			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
+	u32 sicrh; /* System General Purpose Register High */
+#define SICRH_DDR     0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC1_C 0x04000000
+#define SICRH_TSEC1_D 0x02000000
+#define SICRH_TSEC1_E 0x01000000
+#define SICRH_TSEC1_F 0x00800000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TSEC2_F 0x00020000
+#define SICRH_TSEC2_G 0x00010000
+#define SICRH_TSEC2_H 0x00008000
+#define SICRH_GPIO2_A 0x00004000
+#define SICRH_GPIO2_B 0x00002000
+#define SICRH_GPIO2_C 0x00001000
+#define SICRH_GPIO2_D 0x00000800
+#define SICRH_GPIO2_E 0x00000400
+#define SICRH_GPIO2_F 0x00000200
+#define SICRH_GPIO2_G 0x00000180
+#define SICRH_GPIO2_H 0x00000060
+#define SICRH_TSOBI1  0x00000002
+#define SICRH_TSOBI2  0x00000001
+#define SICRh_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
+			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
+			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
+			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
+			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
+			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
+			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
+			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
+			| SICRH_TSOBI2)
+	u8 res6[0xE4];
+} sysconf8349_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt8349 {
+	u8 res0[4];
+	u32 swcrr; /* System watchdog control register */
+	u32 swcnr; /* System watchdog count register */
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES  ~(SWCNR_SWCN)
+	u8 res1[2];
+	u16 swsrr; /* System watchdog service register */
+	u8 res2[0xF0];
+} wdt8349_t;
+
+/*
+ * RTC/PIT Module Registers
+ */
+typedef struct rtclk8349 {
+	u32 cnr; /* control register */
+#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit  */
+#define CNR_CLIN 0x00000040 /* Input Clock Control Bit  */
+#define CNR_AIM  0x00000002 /* Alarm Interrupt Mask Bit  */
+#define CNR_SIM  0x00000001 /* Second Interrupt Mask Bit  */
+#define CNR_RES  ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
+	u32 ldr; /* load register */
+	u32 psr; /* prescale register */
+	u32 ctr; /* register */
+	u32 evr; /* event register */
+#define RTEVR_SIF  0x00000001 /* Second Interrupt Flag Bit  */
+#define RTEVR_AIF  0x00000002 /* Alarm Interrupt Flag Bit  */
+#define RTEVR_RES  ~(EVR_SIF | EVR_AIF)
+	u32 alr; /* alarm register */
+	u8 res0[0xE8];
+} rtclk8349_t;
+
+/*
+ * Global timper module
+ */
+
+typedef struct gtm8349 {
+	u8    cfr1; /* Timer1/2 Configuration  */
+#define CFR1_PCAS 0x80 /* Pair Cascade mode  */
+#define CFR1_BCM  0x40  /* Backward compatible mode  */
+#define CFR1_STP2 0x20 /* Stop timer  */
+#define CFR1_RST2 0x10 /* Reset timer  */
+#define CFR1_GM2  0x08 /* Gate mode for pin 2  */
+#define CFR1_GM1  0x04 /* Gate mode for pin 1  */
+#define CFR1_STP1 0x02 /* Stop timer  */
+#define CFR1_RST1 0x01 /* Reset timer  */
+	u8    res0[3];
+	u8    cfr2; /* Timer3/4 Configuration  */
+#define CFR2_PCAS 0x80 /* Pair Cascade mode  */
+#define CFR2_SCAS 0x40 /* Super Cascade mode  */
+#define CFR2_STP4 0x20 /* Stop timer  */
+#define CFR2_RST4 0x10 /* Reset timer  */
+#define CFR2_GM4  0x08 /* Gate mode for pin 4  */
+#define CFR2_GM3  0x04 /* Gate mode for pin 3  */
+#define CFR2_STP3 0x02 /* Stop timer  */
+#define CFR2_RST3 0x01 /* Reset timer  */
+	u8    res1[10];
+	u16   mdr1; /* Timer1 Mode Register  */
+#define MDR_SPS  0xff00 /* Secondary Prescaler value  */
+#define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
+#define MDR_OM   0x0020 /* Output mode  */
+#define MDR_ORI  0x0010 /* Output reference interrupt enable  */
+#define MDR_FRR  0x0008 /* Free run/restart  */
+#define MDR_ICLK 0x0006 /* Input clock source for the timer  */
+#define MDR_GE   0x0001 /* Gate enable  */
+	u16   mdr2; /* Timer2 Mode Register  */
+	u16   rfr1; /* Timer1 Reference Register  */
+	u16   rfr2; /* Timer2 Reference Register  */
+	u16   cpr1; /* Timer1 Capture Register  */
+	u16   cpr2; /* Timer2 Capture Register  */
+	u16   cnr1; /* Timer1 Counter Register  */
+	u16   cnr2; /* Timer2 Counter Register  */
+	u16   mdr3; /* Timer3 Mode Register  */
+	u16   mdr4; /* Timer4 Mode Register  */
+	u16   rfr3; /* Timer3 Reference Register  */
+	u16   rfr4; /* Timer4 Reference Register  */
+	u16   cpr3; /* Timer3 Capture Register  */
+	u16   cpr4; /* Timer4 Capture Register  */
+	u16   cnr3; /* Timer3 Counter Register  */
+	u16   cnr4; /* Timer4 Counter Register  */
+	u16   evr1; /* Timer1 Event Register  */
+	u16   evr2; /* Timer2 Event Register  */
+	u16   evr3; /* Timer3 Event Register  */
+	u16   evr4; /* Timer4 Event Register  */
+#define GTEVR_REF 0x0002 /* Output reference event  */
+#define GTEVR_CAP 0x0001 /* Counter Capture event   */
+#define GTEVR_RES ~(EVR_CAP|EVR_REF)
+	u16   psr1; /* Timer1 Prescaler Register  */
+	u16   psr2; /* Timer2 Prescaler Register  */
+	u16   psr3; /* Timer3 Prescaler Register  */
+	u16   psr4; /* Timer4 Prescaler Register  */
+	u8    res[0xC0];
+} gtm8349_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic8349 {
+	u32    sicfr; /*  System Global Interrupt Configuration Register (SICFR)  */
+#define SICFR_HPI  0x7f000000 /*  Highest Priority Interrupt  */
+#define SICFR_MPSB 0x00400000 /*  Mixed interrupts Priority Scheme for group B  */
+#define SICFR_MPSA 0x00200000 /*  Mixed interrupts Priority Scheme for group A  */
+#define SICFR_IPSD 0x00080000 /*  Internal interrupts Priority Scheme for group D  */
+#define SICFR_IPSA 0x00010000 /*  Internal interrupts Priority Scheme for group A  */
+#define SICFR_HPIT 0x00000300 /*  HPI priority position IPIC output interrupt Type  */
+#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
+	u32    sivcr; /*  System Global Interrupt Vector Register (SIVCR)  */
+#define SICVR_IVECX 0xfc000000 /*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
+#define SICVR_IVEC  0x0000007f /*  Interrupt vector  */
+#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
+	u32    sipnr_h; /*  System Internal Interrupt Pending Register - High (SIPNR_H)  */
+#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt  */
+#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt  */
+#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
+#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt  */
+#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt  */
+#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
+#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
+#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt  */
+#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
+#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
+#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
+#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
+#define SIIH_I2C2    0x00000002 /*  I2C1 interrupt  */
+#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
+#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
+			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
+			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
+			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
+			| SIIH_I2C2 | SIIH_SPI)
+	u32    sipnr_l; /*  System Internal Interrupt Pending Register - Low (SIPNR_L)  */
+#define SIIL_RTCS  0x80000000 /*  RTC SECOND interrupt  */
+#define SIIL_PIT   0x40000000 /*  PIT interrupt  */
+#define SIIL_PCI1  0x20000000 /*  PCI1 interrupt  */
+#define SIIL_PCI2  0x10000000 /*  PCI2 interrupt  */
+#define SIIL_RTCA  0x08000000 /*  RTC ALARM interrupt  */
+#define SIIL_MU    0x04000000 /*  Message Unit interrupt  */
+#define SIIL_SBA   0x02000000 /*  System Bus Arbiter interrupt  */
+#define SIIL_DMA   0x01000000 /*  DMA interrupt  */
+#define SIIL_GTM4  0x00800000 /*  GTM4 interrupt  */
+#define SIIL_GTM8  0x00400000 /*  GTM8 interrupt  */
+#define SIIL_GPIO1 0x00200000 /*  GPIO1 interrupt  */
+#define SIIL_GPIO2 0x00100000 /*  GPIO2 interrupt  */
+#define SIIL_DDR   0x00080000 /*  DDR interrupt  */
+#define SIIL_LBC   0x00040000 /*  LBC interrupt  */
+#define SIIL_GTM2  0x00020000 /*  GTM2 interrupt  */
+#define SIIL_GTM6  0x00010000 /*  GTM6 interrupt  */
+#define SIIL_PMC   0x00008000 /*  PMC interrupt  */
+#define SIIL_GTM3  0x00000800 /*  GTM3 interrupt  */
+#define SIIL_GTM7  0x00000400 /*  GTM7 interrupt  */
+#define SIIL_GTM1  0x00000020 /*  GTM1 interrupt  */
+#define SIIL_GTM5  0x00000010 /*  GTM5 interrupt  */
+#define SIIL_DPTC  0x00000001 /*  DPTC interrupt (!!! Invisible for user !!!)  */
+#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
+			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
+			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
+			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
+			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
+			| SIIL_GTM5 |SIIL_DPTC )
+	u32    siprr_a; /*  System Internal Interrupt Group A Priority Register (PRR)  */
+	u8     res0[8];
+	u32    siprr_d; /*  System Internal Interrupt Group D Priority Register (PRR)  */
+	u32    simsr_h; /*  System Internal Interrupt Mask Register - High (SIIH)  */
+	u32    simsr_l; /*  System Internal Interrupt Mask Register - Low (SIIL)  */
+	u8     res1[4];
+	u32    sepnr;   /*  System External Interrupt Pending Register (SEI)  */
+	u32    smprr_a; /*  System Mixed Interrupt Group A Priority Register (PRR)  */
+	u32    smprr_b; /*  System Mixed Interrupt Group B Priority Register (PRR)  */
+#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
+#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
+#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
+#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
+#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
+#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
+#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
+#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
+#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
+	u32    semsr; /*  System External Interrupt Mask Register (SEI)  */
+#define SEI_IRQ0  0x80000000 /*  IRQ0 external interrupt  */
+#define SEI_IRQ1  0x40000000 /*  IRQ1 external interrupt  */
+#define SEI_IRQ2  0x20000000 /*  IRQ2 external interrupt  */
+#define SEI_IRQ3  0x10000000 /*  IRQ3 external interrupt  */
+#define SEI_IRQ4  0x08000000 /*  IRQ4 external interrupt  */
+#define SEI_IRQ5  0x04000000 /*  IRQ5 external interrupt  */
+#define SEI_IRQ6  0x02000000 /*  IRQ6 external interrupt  */
+#define SEI_IRQ7  0x01000000 /*  IRQ7 external interrupt  */
+#define SEI_SIRQ0 0x00008000 /*  SIRQ0 external interrupt  */
+#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
+			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
+			| SEI_SIRQ0)
+	u32    secnr; /*  System External Interrupt Control Register (SECNR) */
+#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type  */
+#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type  */
+#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type  */
+#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type  */
+#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
+#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
+#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
+#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
+#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
+#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
+#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
+#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
+#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
+			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
+			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
+			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
+	u32   sersr; /*  System Error Status Register (SERR)  */
+	u32   sermr; /*  System Error Mask Register (SERR)  */
+#define SERR_IRQ0 0x80000000 /*  IRQ0 MCP request  */
+#define SERR_WDT  0x40000000 /*  WDT MCP request  */
+#define SERR_SBA  0x20000000 /*  SBA MCP request  */
+#define SERR_DDR  0x10000000 /*  DDR MCP request  */
+#define SERR_LBC  0x08000000 /*  LBC MCP request  */
+#define SERR_PCI1 0x04000000 /*  PCI1 MCP request  */
+#define SERR_PCI2 0x02000000 /*  PCI2 MCP request  */
+#define SERR_MU   0x01000000 /*  MU MCP request  */
+#define SERR_RNC  0x00010000 /*  MU MCP request (!!! Non-visible for users !!!)  */
+#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
+			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
+			|SERR_RNC )
+	u32    sercr; /*  System Error Control Register  (SERCR)  */
+#define SERCR_MCPR 0x00000001 /*  MCP Route  */
+#define SERCR_RES ~(SERCR_MCPR)
+	u8    res2[4];
+	u32   sifcr_h; /*  System Internal Interrupt Force Register - High (SIIH)  */
+	u32   sifcr_l; /*  System Internal Interrupt Force Register - Low (SIIL)  */
+	u32   sefcr;   /*  System External Interrupt Force Register (SEI)  */
+	u32   serfr;   /*  System Error Force Register (SERR)  */
+	u8    res3[0xA0];
+} ipic8349_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter8349 {
+	u32 acr; /* Arbiter Configuration Register */
+#define ACR_COREDIS    0x10000000 /* Core disable. */
+#define ACR_PIPE_DEP   0x00070000 /* Pipeline depth (number of outstanding transactions). */
+#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
+#define ACR_RPTCNT     0x00000700 /* Repeat count. */
+#define ACR_APARK      0x00000030 /* Address parking. */
+#define ACR_PARKM	   0x0000000F /* Parking master. */
+#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
+	u32 atr; /* Arbiter Timers Register */
+#define ATR_DTO 0x00FF0000 /* Data time out. */
+#define ATR_ATO	0x000000FF /* Address time out. */
+#define ATR_RES ~(ATR_DTO|ATR_ATO)
+	u8 res[4];
+	u32 aer; /* Arbiter Event Register (AE)*/
+	u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
+	u32 amr; /* Arbiter Mask Register (AE) */
+	u32 aeatr; /* Arbiter Event Attributes Register */
+#define AEATR_EVENT   0x07000000 /* Event type. */
+#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
+#define AEATR_TBST    0x00000800 /* Transfer burst. */
+#define AEATR_TSIZE   0x00000700 /* Transfer Size. */
+#define AEATR_TTYPE	  0x0000001F /* Transfer Type. */
+#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
+	u32 aeadr; /* Arbiter Event Address Register */
+	u32 aerr; /* Arbiter Event Response Register (AE)*/
+#define AE_ETEA 0x00000020 /* Transfer error. */
+#define AE_RES_ 0x00000010 /* Reserved transfer type. */
+#define AE_ECW  0x00000008 /* External control word transfer type. */
+#define AE_AO   0x00000004 /* Address Only transfer type. */
+#define AE_DTO  0x00000002 /* Data time out. */
+#define AE_ATO	0x00000001 /* Address time out. */
+#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+	u8 res1[0xDC];
+} arbiter8349_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset8349 {
+	u32    rcwl; /* RCWL Register  */
+#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
+#define RCWL_LBIUCM_SHIFT    31
+#define RCWL_DDRCM   0x40000000 /* DDRCM  */
+#define RCWL_DDRCM_SHIFT     30
+#define RCWL_SVCOD   0x30000000 /* SVCOD  */
+#define RCWL_SPMF    0x0f000000 /* SPMF  */
+#define RCWL_SPMF_SHIFT      24
+#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
+#define RCWL_COREPLL_SHIFT   16
+#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
+#define RCWL_CEPDF   0x00000020 /* CEPDF  */
+#define RCWL_CEPMF   0x0000001F /* CEPMF  */
+#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
+	u32    rcwh; /* RCHL Register  */
+#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define RCWH_PCIHOST_SHIFT   31
+#define RCWH_PCI64   0x40000000 /* PCI64  */
+#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
+#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
+#define RCWH_COREDIS 0x08000000 /* COREDIS  */
+#define RCWH_BMS     0x04000000 /* BMS  */
+#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
+#define RCWH_SWEN    0x00800000 /* SWEN  */
+#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
+#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
+#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
+#define RCWH_TPR     0x00000100 /* TPR  */
+#define RCWH_TLE     0x00000008 /* TLE  */
+#define RCWH_LALE    0x00000004 /* LALE  */
+#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
+			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
+			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
+			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
+			| RCWH_TLE | RCWH_LALE)
+	u8     res0[8];
+	u32    rsr; /* Reset status Register  */
+#define RSR_RSTSRC 0xE0000000 /* Reset source  */
+#define RSR_RSTSRC_SHIFT   29
+#define RSR_BSF    0x00010000 /* Boot seq. fail  */
+#define RSR_BSF_SHIFT      16
+#define RSR_SWSR   0x00002000 /* software soft reset  */
+#define RSR_SWSR_SHIFT     13
+#define RSR_SWHR   0x00001000 /* software hard reset  */
+#define RSR_SWHR_SHIFT     12
+#define RSR_JHRS   0x00000200 /* jtag hreset  */
+#define RSR_JHRS_SHIFT      9
+#define RSR_JSRS   0x00000100 /* jtag sreset status  */
+#define RSR_JSRS_SHIFT      8
+#define RSR_CSHR   0x00000010 /* checkstop reset status  */
+#define RSR_CSHR_SHIFT      4
+#define RSR_SWRS   0x00000008 /* software watchdog reset status  */
+#define RSR_SWRS_SHIFT      3
+#define RSR_BMRS   0x00000004 /* bus monitop reset status  */
+#define RSR_BMRS_SHIFT      2
+#define RSR_SRS    0x00000002 /* soft reset status  */
+#define RSR_SRS_SHIFT       1
+#define RSR_HRS    0x00000001 /* hard reset status  */
+#define RSR_HRS_SHIFT       0
+#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
+	u32    rmr; /* Reset mode Register  */
+#define RMR_CSRE   0x00000001 /* checkstop reset enable  */
+#define RMR_CSRE_SHIFT      0
+#define RMR_RES ~(RMR_CSRE)
+	u32    rpr; /* Reset protection Register  */
+	u32    rcr; /* Reset Control Register  */
+#define RCR_SWHR 0x00000002 /* software hard reset  */
+#define RCR_SWSR 0x00000001 /* software soft reset  */
+#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
+	u32    rcer; /* Reset Control Enable Register  */
+#define RCER_CRE 0x00000001 /* software hard reset  */
+#define RCER_RES ~(RCER_CRE)
+	u8     res1[0xDC];
+} reset8349_t;
+
+typedef struct clk8349 {
+	u32    spmr; /* system PLL mode Register  */
+#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
+#define SPMR_DDRCM   0x40000000 /* DDRCM  */
+#define SPMR_SVCOD   0x30000000 /* SVCOD  */
+#define SPMR_SPMF    0x0F000000 /* SPMF  */
+#define SPMR_CKID    0x00800000 /* CKID  */
+#define SPMR_CKID_SHIFT 23
+#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
+#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
+#define SPMR_CEPDF   0x00000020 /* CEPDF  */
+#define SPMR_CEPMF   0x0000001F /* CEPMF  */
+#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
+			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
+			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
+	u32    occr; /* output clock control Register  */
+#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
+#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
+#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
+#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
+#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
+#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
+#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
+#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
+#define OCCR_PCICD0  0x00800000 /* PCICD0  */
+#define OCCR_PCICD1  0x00400000 /* PCICD1  */
+#define OCCR_PCICD2  0x00200000 /* PCICD2  */
+#define OCCR_PCICD3  0x00100000 /* PCICD3  */
+#define OCCR_PCICD4  0x00080000 /* PCICD4  */
+#define OCCR_PCICD5  0x00040000 /* PCICD5  */
+#define OCCR_PCICD6  0x00020000 /* PCICD6  */
+#define OCCR_PCICD7  0x00010000 /* PCICD7  */
+#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
+#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
+#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
+			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
+			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
+			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
+			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
+			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
+	u32    sccr; /* system clock control Register  */
+#define SCCR_TSEC1CM  0xc0000000 /* TSEC1CM  */
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC2CM  0x30000000 /* TSEC2CM  */
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_ENCCM    0x03000000 /* ENCCM  */
+#define SCCR_ENCCM_SHIFT 24
+#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM  */
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM  0x00300000 /* USBDRCM  */
+#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_PCICM    0x00010000 /* PCICM  */
+#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
+			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
+	u8     res0[0xF4];
+} clk8349_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc8349 {
+	u32    pmccr; /* PMC Configuration Register  */
+#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable  */
+#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable  */
+#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
+	u32    pmcer; /* PMC Event Register  */
+#define PMCER_PMCI  0x00000001 /* PMC Interrupt  */
+#define PMCER_RES ~(PMCER_PMCI)
+	u32    pmcmr; /* PMC Mask Register  */
+#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable  */
+#define PMCMR_RES ~(PMCMR_PMCIE)
+	u8 res0[0xF4];
+} pmc8349_t;
+
+
+/*
+ * general purpose I/O module
+ */
+typedef struct gpio8349 {
+	u32 dir; /* direction register */
+	u32 odr; /* open drain register */
+	u32 dat; /* data register */
+	u32 ier; /* interrupt event register */
+	u32 imr; /* interrupt mask register */
+	u32 icr; /* external interrupt control register */
+	u8 res0[0xE8];
+} gpio8349_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr_cs_bnds{
+	u32 csbnds;
+#define CSBNDS_SA 0x00FF0000
+#define CSBNDS_SA_SHIFT   16
+#define CSBNDS_EA 0x000000FF
+#define CSBNDS_EA_SHIFT    0
+	u8  res0[4];
+} ddr_cs_bnds_t;
+
+typedef struct ddr8349{
+	ddr_cs_bnds_t csbnds[4];            /**< Chip Select x Memory Bounds */
+	u8 res0[0x60];
+	u32 cs_config[4];       /**< Chip Select x Configuration */
+#define CSCONFIG_EN         0x80000000
+#define CSCONFIG_AP         0x00800000
+#define CSCONFIG_ROW_BIT    0x00000700
+#define CSCONFIG_ROW_BIT_12 0x00000000
+#define CSCONFIG_ROW_BIT_13 0x00000100
+#define CSCONFIG_ROW_BIT_14 0x00000200
+#define CSCONFIG_COL_BIT    0x00000007
+#define CSCONFIG_COL_BIT_8  0x00000000
+#define CSCONFIG_COL_BIT_9  0x00000001
+#define CSCONFIG_COL_BIT_10 0x00000002
+#define CSCONFIG_COL_BIT_11 0x00000003
+	u8 res1[0x78];
+	u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
+#define TIMING_CFG1_PRETOACT 0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT   28
+#define TIMING_CFG1_ACTTOPRE 0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT   24
+#define TIMING_CFG1_ACTTORW  0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT    20
+#define TIMING_CFG1_CASLAT   0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT     16
+#define TIMING_CFG1_REFREC   0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT     12
+#define TIMING_CFG1_WRREC    0x00000700
+#define TIMING_CFG1_WRREC_SHIFT       8
+#define TIMING_CFG1_ACTTOACT 0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT    4
+#define TIMING_CFG1_WRTORD   0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT      0
+
+	u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
+#define TIMING_CFG2_CPO           0x0F000000
+#define TIMING_CFG2_CPO_SHIFT             24
+#define TIMING_CFG2_ACSM          0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
+
+	u32 sdram_cfg;          /**< SDRAM Control Configuration */
+#define SDRAM_CFG_MEM_EN     0x80000000
+#define SDRAM_CFG_SREN       0x40000000
+#define SDRAM_CFG_ECC_EN     0x20000000
+#define SDRAM_CFG_RD_EN      0x10000000
+#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
+#define SDRAM_CFG_DYN_PWR    0x00200000
+#define SDRAM_CFG_32_BE      0x00080000
+#define SDRAM_CFG_8_BE       0x00040000
+#define SDRAM_CFG_NCAP       0x00020000
+#define SDRAM_CFG_2T_EN      0x00008000
+
+	u8 res2[4];
+	u32 sdram_mode;         /**< SDRAM Mode Configuration */
+#define SDRAM_MODE_ESD 0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT   16
+#define SDRAM_MODE_SD  0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT     0
+
+	u8 res3[8];
+	u32 sdram_interval;     /**< SDRAM Interval Configuration */
+#define SDRAM_INTERVAL_REFINT  0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT    16
+#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
+	u8   res9[8];
+	u32  sdram_clk_cntl;
+	u8 res4[0xCCC];
+	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
+	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
+	u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
+	u8 res5[0x14];
+	u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
+	u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
+	u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
+	u8 res6[0x14];
+	u32 err_detect;         /**< Memory Error Detect */
+	u32 err_disable;        /**< Memory Error Disable */
+	u32 err_int_en;         /**< Memory Error Interrupt Enable */
+	u32 capture_attributes; /**< Memory Error Attributes Capture */
+	u32 capture_address;    /**< Memory Error Address Capture */
+	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
+	u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
+	u8 res7[0xA4];
+	u32 debug_reg;
+	u8 res8[0xFC];
+} ddr8349_t;
+
+/*
+ * I2C1 Controller
+ */
+
+
+/*
+ * DUART
+ */
+typedef struct duart8349{
+	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
+	u8 uier_udmb;      /**< combined register for UIER and UDMB */
+	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
+	u8 ulcr;        /**< line control register */
+	u8 umcr;        /**< MODEM control register */
+	u8 ulsr;        /**< line status register */
+	u8 umsr;        /**< MODEM status register */
+	u8 uscr;        /**< scratch register */
+	u8 res0[8];
+	u8 udsr;        /**< DMA status register */
+	u8 res1[3];
+	u8 res2[0xEC];
+} duart8349_t;
+
+/*
+ * Local Bus Controller Registers
+ */
+typedef struct lbus_bank{
+	u32 br;             /**< Base Register  */
+	u32 or;             /**< Base Register  */
+} lbus_bank_t;
+
+typedef struct lbus8349 {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;                /**< UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;               /**< UPMA Mode Register */
+	u32 mbmr;               /**< UPMB Mode Register */
+	u32 mcmr;               /**< UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
+	u32 mdr;                /**< UPM Data Register */
+	u8 res3[0x8];
+	u32 lsdmr;              /**< SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;               /**< UPM Refresh Timer */
+	u32 lsrt;               /**< SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;              /**< Transfer Error Status Register */
+	u32 ltedr;              /**< Transfer Error Disable Register */
+	u32 lteir;              /**< Transfer Error Interrupt Register */
+	u32 lteatr;             /**< Transfer Error Attributes Register */
+	u32 ltear;              /**< Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;               /**< Configuration Register */
+#define LBCR_LDIS  0x80000000
+#define LBCR_LDIS_SHIFT    31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT   22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT   17
+#define LBCR_EPAR  0x00010000
+#define LBCR_EPAR_SHIFT    16
+#define LBCR_BMT   0x0000FF00
+#define LBCR_BMT_SHIFT      8
+	u32 lcrr;               /**< Clock Ratio Register */
+#define LCRR_DBYP    0x80000000
+#define LCRR_DBYP_SHIFT      31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT   28
+#define LCRR_ECL     0x03000000
+#define LCRR_ECL_SHIFT       24
+#define LCRR_EADC    0x00030000
+#define LCRR_EADC_SHIFT      16
+#define LCRR_CLKDIV  0x0000000F
+#define LCRR_CLKDIV_SHIFT     0
+
+
+	u8 res7[0x28];
+	u8 res8[0xF00];
+} lbus8349_t;
+
+/*
+ * Serial Peripheral Interface
+ */
+typedef struct spi8349
+{
+	u32 mode;     /**< mode register  */
+	u32 event;    /**< event register */
+	u32 mask;     /**< mask register  */
+	u32 com;      /**< command register */
+	u8 res0[0x10];
+	u32 tx;       /**< transmit register */
+	u32 rx;       /**< receive register */
+	u8 res1[0xD8];
+} spi8349_t;
+
+typedef struct dma8349 {
+	u8 fixme[0x300];
+} dma8349_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf8349 {
+	u32	config_address;
+#define PCI_CONFIG_ADDRESS_EN	0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+	u32 config_data;
+	u32 int_ack;
+	u8	res[116];
+} pciconf8349_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32	potar;
+	u8	res0[4];
+	u32	pobar;
+	u8	res1[4];
+	u32	pocmr;
+	u8	res2[4];
+} pot8349_t;
+/*
+ * Sequencer
+ */
+typedef struct ios8349 {
+	pot8349_t	pot[6];
+#define POTAR_TA_MASK	0x000fffff
+#define	POBAR_BA_MASK	0x000fffff
+#define	POCMR_EN	0x80000000
+#define	POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
+#define	POCMR_SE	0x20000000	/* streaming enable */
+#define	POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2*/
+#define	POCMR_CM_MASK	0x000fffff
+#define	POCMR_CM_4G	0x00000000
+#define	POCMR_CM_2G	0x00080000
+#define	POCMR_CM_1G	0x000C0000
+#define	POCMR_CM_512M	0x000E0000
+#define	POCMR_CM_256M	0x000F0000
+#define	POCMR_CM_128M	0x000F8000
+#define	POCMR_CM_64M	0x000FC000
+#define	POCMR_CM_32M	0x000FE000
+#define	POCMR_CM_16M	0x000FF000
+#define	POCMR_CM_8M	0x000FF800
+#define	POCMR_CM_4M	0x000FFC00
+#define	POCMR_CM_2M	0x000FFE00
+#define	POCMR_CM_1M	0x000FFF00
+#define	POCMR_CM_512K	0x000FFF80
+#define	POCMR_CM_256K	0x000FFFC0
+#define	POCMR_CM_128K	0x000FFFE0
+#define	POCMR_CM_64K	0x000FFFF0
+#define	POCMR_CM_32K	0x000FFFF8
+#define	POCMR_CM_16K	0x000FFFFC
+#define	POCMR_CM_8K	0x000FFFFE
+#define	POCMR_CM_4K	0x000FFFFF
+	u8	res0[0x60];
+	u32	pmcr;
+	u8	res1[4];
+	u32	dtcr;
+	u8	res2[4];
+} ios8349_t;
+
+/*
+ * PCI Controller Control and Status Registers
+ */
+typedef struct pcictrl8349 {
+	u32	esr;
+#define ESR_MERR	0x80000000
+#define ESR_APAR	0x00000400
+#define	ESR_PCISERR	0x00000200
+#define	ESR_MPERR	0x00000100
+#define	ESR_TPERR	0x00000080
+#define	ESR_NORSP	0x00000040
+#define	ESR_TABT	0x00000020
+	u32	ecdr;
+#define ECDR_APAR	0x00000400
+#define	ECDR_PCISERR	0x00000200
+#define	ECDR_MPERR	0x00000100
+#define	ECDR_TPERR	0x00000080
+#define	ECDR_NORSP	0x00000040
+#define	ECDR_TABT	0x00000020
+	u32 eer;
+#define EER_APAR	0x00000400
+#define	EER_PCISERR	0x00000200
+#define	EER_MPERR	0x00000100
+#define	EER_TPERR	0x00000080
+#define	EER_NORSP	0x00000040
+#define	EER_TABT	0x00000020
+	u32	eatcr;
+#define	EATCR_ERRTYPR_MASK	0x70000000
+#define	EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
+#define	EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
+#define	EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
+#define	EATCR_ERRTYPR_MA	0x30000000	/* master abort */
+#define	EATCR_ERRTYPR_TA	0x40000000	/* target abort */
+#define	EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */
+#define	EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
+#define	EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
+#define EATCR_BN_MASK		0x0f000000	/* beat number */
+#define	EATCR_BN_1st		0x00000000
+#define	EATCR_BN_2ed		0x01000000
+#define	EATCR_BN_3rd		0x02000000
+#define	EATCR_BN_4th		0x03000000
+#define	EATCR_BN_5th		0x0400000
+#define	EATCR_BN_6th		0x05000000
+#define	EATCR_BN_7th		0x06000000
+#define	EATCR_BN_8th		0x07000000
+#define	EATCR_BN_9th		0x08000000
+#define EATCR_TS_MASK		0x00300000	/* transaction size */
+#define	EATCR_TS_4		0x00000000
+#define	EATCR_TS_1		0x00100000
+#define	EATCR_TS_2		0x00200000
+#define	EATCR_TS_3		0x00300000
+#define	EATCR_ES_MASK		0x000f0000	/* error source */
+#define	EATCR_ES_EM		0x00000000	/* external master */
+#define	EATCR_ES_DMA		0x00050000
+#define	EATCR_CMD_MASK		0x0000f000
+#define	EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable*/
+#define	EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
+#define	EATCR_HPB		0x00000004	/* high parity bit */
+#define	EATCR_PB		0x00000002	/* parity bit*/
+#define	EATCR_VI		0x00000001	/* error information valid */
+	u32	eacr;
+	u32	eeacr;
+	u32	edlcr;
+	u32	edhcr;
+	u32	gcr;
+	u32	ecr;
+	u32	gsr;
+	u8	res0[12];
+	u32	pitar2;
+	u8	res1[4];
+	u32	pibar2;
+	u32	piebar2;
+	u32	piwar2;
+	u8	res2[4];
+	u32	pitar1;
+	u8	res3[4];
+	u32	pibar1;
+	u32	piebar1;
+	u32	piwar1;
+	u8	res4[4];
+	u32	pitar0;
+	u8	res5[4];
+	u32	pibar0;
+	u8	res6[4];
+	u32	piwar0;
+	u8	res7[132];
+#define PITAR_TA_MASK		0x000fffff
+#define PIBAR_MASK		0xffffffff
+#define PIEBAR_EBA_MASK		0x000fffff
+#define PIWAR_EN		0x80000000
+#define PIWAR_PF		0x20000000
+#define	PIWAR_RTT_MASK		0x000f0000
+#define	PIWAR_RTT_NO_SNOOP	0x00040000
+#define PIWAR_RTT_SNOOP		0x00050000
+#define	PIWAR_WTT_MASK		0x0000f000
+#define	PIWAR_WTT_NO_SNOOP	0x00004000
+#define PIWAR_WTT_SNOOP		0x00005000
+#define	PIWAR_IWS_MASK	0x0000003F
+#define	PIWAR_IWS_4K	0x0000000B
+#define	PIWAR_IWS_8K	0x0000000C
+#define	PIWAR_IWS_16K	0x0000000D
+#define	PIWAR_IWS_32K	0x0000000E
+#define	PIWAR_IWS_64K	0x0000000F
+#define	PIWAR_IWS_128K	0x00000010
+#define	PIWAR_IWS_256K	0x00000011
+#define	PIWAR_IWS_512K	0x00000012
+#define	PIWAR_IWS_1M	0x00000013
+#define	PIWAR_IWS_2M	0x00000014
+#define	PIWAR_IWS_4M	0x00000015
+#define	PIWAR_IWS_8M	0x00000016
+#define	PIWAR_IWS_16M	0x00000017
+#define	PIWAR_IWS_32M	0x00000018
+#define	PIWAR_IWS_64M	0x00000019
+#define	PIWAR_IWS_128M	0x0000001A
+#define	PIWAR_IWS_256M	0x0000001B
+#define	PIWAR_IWS_512M	0x0000001C
+#define	PIWAR_IWS_1G	0x0000001D
+#define	PIWAR_IWS_2G	0x0000001E
+} pcictrl8349_t;
+
+/*
+ * USB
+ */
+typedef struct usb8349 {
+	u8 fixme[0x2000];
+} usb8349_t;
+
+/*
+ * TSEC
+ */
+typedef struct tsec8349 {
+	u8 fixme[0x1000];
+} tsec8349_t;
+
+/*
+ * Security
+ */
+typedef struct security8349 {
+	u8 fixme[0x10000];
+} security8349_t;
+
+typedef struct immap {
+	sysconf8349_t sysconf; /* System configuration */
+	wdt8349_t     wdt;     /* Watch Dog Timer (WDT) Registers */
+	rtclk8349_t   rtc;     /* Real Time Clock Module Registers */
+	rtclk8349_t   pit;     /* Periodic Interval Timer */
+	gtm8349_t     gtm[2];  /* Global Timers Module */
+	ipic8349_t    ipic;    /* Integrated Programmable Interrupt Controller */
+	arbiter8349_t arbiter; /* System Arbiter Registers */
+	reset8349_t   reset;   /* Reset Module */
+	clk8349_t     clk;     /* System Clock Module */
+	pmc8349_t     pmc;     /* Power Management Control Module */
+	gpio8349_t    pgio[2]; /* general purpose I/O module */
+	u8 res0[0x200];
+	u8 DDL_DDR[0x100];
+	u8 DDL_LBIU[0x100];
+	u8 res1[0xE00];
+	ddr8349_t     ddr;     /* DDR Memory Controller Memory */
+	i2c_t     i2c[2];      /* I2C1 Controller */
+	u8 res2[0x1300];
+	duart8349_t   duart[2];/* DUART */
+	u8 res3[0x900];
+	lbus8349_t    lbus;    /* Local Bus Controller Registers */
+	u8 res4[0x1000];
+	spi8349_t     spi;     /* Serial Peripheral Interface */
+	u8 res5[0xF00];
+	dma8349_t     dma;     /* DMA */
+	pciconf8349_t pci_conf[2];  /* PCI Software Configuration Registers */
+	ios8349_t     ios;     /* Sequencer */
+	pcictrl8349_t pci_ctrl[2];  /* PCI Controller Control and Status Registers */
+	u8 res6[0x19900];
+	usb8349_t     usb;
+	tsec8349_t    tsec[2];
+	u8 res7[0xA000];
+	security8349_t security;
+} immap_t;
+
+#endif /* __IMMAP_8349__ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 1b73def..2f10e95 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -9,9 +9,9 @@
 #ifndef __IMMAP_85xx__
 #define __IMMAP_85xx__
 
-
-/* Local-Access Registers and ECM Registers(0x0000-0x2000) */
-
+/*
+ * Local-Access Registers and ECM Registers(0x0000-0x2000)
+ */
 typedef struct ccsr_local_ecm {
 	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
 	char	res1[4];
@@ -65,9 +65,9 @@ typedef struct ccsr_local_ecm {
 	char	res24[492];
 } ccsr_local_ecm_t;
 
-
-/* DDR memory controller registers(0x2000-0x3000) */
-
+/*
+ * DDR memory controller registers(0x2000-0x3000)
+ */
 typedef struct ccsr_ddr {
 	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
 	char	res1[4];
@@ -81,21 +81,27 @@ typedef struct ccsr_ddr {
 	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
 	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
 	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
-	char	res5[120];
+	char	res5[112];
+	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
 	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration */
-	char	res6[4];
+	uint	sdram_cfg_2;		/* 0x2114 - DDR SDRAM Control Configuration 2 */
 	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration */
-	char	res7[8];
+	uint	sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2*/
+	uint	sdram_md_cntl;		/* 0x2120 - DDR SDRAM Mode Control */
 	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
-	char	res7_5[8];
+	uint	sdram_data_init;	/* 0x2128 - DDR SDRAM Data initialization */
+	char	res6[4];
 	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
-	char	res8[3276];
-#else
-	char	res8[3288];
-#endif
+	char	res7[20];
+	uint	init_address;		/* 0x2148 - DDR training initialization address */
+	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
+	char	res8_1[2728];
+	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
+	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
+	char	res8_2[512];
 	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
 	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
 	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
@@ -119,9 +125,9 @@ typedef struct ccsr_ddr {
 	char	res12[240];
 } ccsr_ddr_t;
 
-
-/* I2C Registers(0x3000-0x4000) */
-
+/*
+ * I2C Registers(0x3000-0x4000)
+ */
 typedef struct ccsr_i2c {
 	u_char	i2cadr;		/* 0x3000 - I2C Address Register */
 #define MPC85xx_I2CADR_MASK	0xFE
@@ -158,6 +164,7 @@ typedef struct ccsr_i2c {
 
 #if defined(CONFIG_MPC8540) \
 	|| defined(CONFIG_MPC8541) \
+	|| defined(CONFIG_MPC8548) \
 	|| defined(CONFIG_MPC8555)
 /* DUART Registers(0x4000-0x5000) */
 typedef struct ccsr_duart {
@@ -237,10 +244,10 @@ typedef struct ccsr_lbc {
 	char	res8[12072];
 } ccsr_lbc_t;
 
-
-/* PCI Registers(0x8000-0x9000) */
-/* Omitting Reserved(0x9000-0x2_0000) */
-
+/*
+ * PCI Registers(0x8000-0x9000)
+ * Omitting Reserved(0x9000-0x2_0000)
+ */
 typedef struct ccsr_pcix {
 	uint	cfg_addr;	/* 0x8000 - PCIX Configuration Address Register */
 	uint	cfg_data;	/* 0x8004 - PCIX Configuration Data Register */
@@ -305,9 +312,9 @@ typedef struct ccsr_pcix {
 	char	res11[94688];
 } ccsr_pcix_t;
 
-
-/* L2 Cache Registers(0x2_0000-0x2_1000) */
-
+/*
+ * L2 Cache Registers(0x2_0000-0x2_1000)
+ */
 typedef struct ccsr_l2cache {
 	uint	l2ctl;		/* 0x20000 - L2 configuration register 0 */
 	char	res1[12];
@@ -349,9 +356,9 @@ typedef struct ccsr_l2cache {
 	char	res15[420];
 } ccsr_l2cache_t;
 
-
-/* DMA Registers(0x2_1000-0x2_2000) */
-
+/*
+ * DMA Registers(0x2_1000-0x2_2000)
+ */
 typedef struct ccsr_dma {
 	char	res1[256];
 	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
@@ -430,7 +437,9 @@ typedef struct ccsr_dma {
 	char	res22[11516];
 } ccsr_dma_t;
 
-/* tsec1 tsec2: 24000-26000 */
+/*
+ * tsec1 tsec2: 24000-26000
+ */
 typedef struct ccsr_tsec {
 	char	res1[16];
 	uint	ievent;		/* 0x24010 - Interrupt Event Register */
@@ -717,8 +726,9 @@ typedef struct ccsr_tsec {
 	char	res74[1024];
 } ccsr_tsec_t;
 
-/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */
-
+/*
+ * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ */
 typedef struct ccsr_pic {
 	char 	res0[106496];	/* 0x26000-0x40000 */
 	char	res1[64];
@@ -1024,17 +1034,18 @@ typedef struct ccsr_pic {
 	char	res150[130892];
 } ccsr_pic_t;
 
-/* CPM Block(0x8_0000-0xc_0000) */
-#if defined(CONFIG_MPC8540) \
-	|| defined(CONFIG_MPC8541) \
-	|| defined(CONFIG_MPC8555)
+/*
+ * CPM Block(0x8_0000-0xc_0000)
+ */
+#ifndef CONFIG_CPM2
 typedef struct ccsr_cpm {
 	char res[262144];
 } ccsr_cpm_t;
 #else
-/* 0x8000-0x8ffff:DPARM */
-
-/* 0x9000-0x90bff: General SIU */
+/*
+ * 0x8000-0x8ffff:DPARM
+ * 0x9000-0x90bff: General SIU
+ */
 typedef struct ccsr_cpm_siu {
 	char 	res1[80];
 	uint	smaer;
@@ -1325,7 +1336,6 @@ typedef struct ccsr_cpm {
 	char            	res1[16*1024];
 	u_char          	im_dpram2[16*1024];
 	char            	res2[16*1024];
-
 	ccsr_cpm_siu_t  	im_cpm_siu;     /* SIU Configuration */
 	ccsr_cpm_intctl_t    	im_cpm_intctl;  /* Interrupt Controller */
 	ccsr_cpm_iop_t       	im_cpm_iop;     /* IO Port control/status */
@@ -1350,8 +1360,10 @@ typedef struct ccsr_cpm {
 	ccsr_cpm_iram_t		im_cpm_iram;
 } ccsr_cpm_t;
 #endif
-/* RapidIO Registers(0xc_0000-0xe_0000) */
 
+/*
+ * RapidIO Registers(0xc_0000-0xe_0000)
+ */
 typedef struct ccsr_rio {
 	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
 	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
@@ -1517,7 +1529,9 @@ typedef struct ccsr_rio {
 	char	res58[60176];
 } ccsr_rio_t;
 
-/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+/*
+ * Global Utilities Register Block(0xe_0000-0xf_ffff)
+ */
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
@@ -1549,7 +1563,13 @@ typedef struct ccsr_gur {
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
 	char	res12[12];
 	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
-	char	res13[61915];
+	char	res13[248];
+	uint	lbiuiplldcr0;	/* 0xe0f1c -- LBIU PLL Debug Reg 0 */
+	uint	lbiuiplldcr1;	/* 0xe0f20 -- LBIU PLL Debug Reg 1 */
+	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Override Control */
+	uint	res14;		/* 0xe0f28 */
+	uint	tsec34ioovcr;	/* 0xe0f2c - eTSEC 3/4 IO override control */
+	char	res15[61651];
 } ccsr_gur_t;
 
 typedef struct immap {
diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h
new file mode 100644
index 0000000..48255a3
--- /dev/null
+++ b/include/asm-ppc/mpc8349_pci.h
@@ -0,0 +1,167 @@
+#ifndef _PPC_KERNEL_MPC8349_PCI_H
+#define _PPC_KERNEL_MPC8349_PCI_H
+
+
+#define M8265_PCIBR0	0x101ac
+#define M8265_PCIBR1	0x101b0
+#define M8265_PCIMSK0	0x101c4
+#define M8265_PCIMSK1	0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KB         0xFFFF0000
+#define PCIMSK_128KB        0xFFFE0000
+#define PCIMSK_256KB        0xFFFC0000
+#define PCIMSK_512KB        0xFFF80000
+#define PCIMSK_1MB          0xFFF00000
+#define PCIMSK_2MB          0xFFE00000
+#define PCIMSK_4MB          0xFFC00000
+#define PCIMSK_8MB          0xFF800000
+#define PCIMSK_16MB         0xFF000000
+#define PCIMSK_32MB         0xFE000000
+#define PCIMSK_64MB         0xFC000000
+#define PCIMSK_128MB        0xF8000000
+#define PCIMSK_256MB        0xF0000000
+#define PCIMSK_512MB        0xE0000000
+#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus
+ * (local) addresses are translated to PCI addresses when the MPC826x is
+ * a PCI bus master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB      0x000FFFFF
+#define POCMR_MASK_8KB      0x000FFFFE
+#define POCMR_MASK_16KB     0x000FFFFC
+#define POCMR_MASK_32KB     0x000FFFF8
+#define POCMR_MASK_64KB     0x000FFFF0
+#define POCMR_MASK_128KB    0x000FFFE0
+#define POCMR_MASK_256KB    0x000FFFC0
+#define POCMR_MASK_512KB    0x000FFF80
+#define POCMR_MASK_1MB      0x000FFF00
+#define POCMR_MASK_2MB      0x000FFE00
+#define POCMR_MASK_4MB      0x000FFC00
+#define POCMR_MASK_8MB      0x000FF800
+#define POCMR_MASK_16MB     0x000FF000
+#define POCMR_MASK_32MB     0x000FE000
+#define POCMR_MASK_64MB     0x000FC000
+#define POCMR_MASK_128MB    0x000F8000
+#define POCMR_MASK_256MB    0x000F0000
+#define POCMR_MASK_512MB    0x000E0000
+#define POCMR_MASK_1GB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI
+ * addresses are translated to 60x bus (local) addresses when the
+ * MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB       0x000FFFFF
+#define PICMR_MASK_8KB       0x000FFFFE
+#define PICMR_MASK_16KB      0x000FFFFC
+#define PICMR_MASK_32KB      0x000FFFF8
+#define PICMR_MASK_64KB      0x000FFFF0
+#define PICMR_MASK_128KB     0x000FFFE0
+#define PICMR_MASK_256KB     0x000FFFC0
+#define PICMR_MASK_512KB     0x000FFF80
+#define PICMR_MASK_1MB       0x000FFF00
+#define PICMR_MASK_2MB       0x000FFE00
+#define PICMR_MASK_4MB       0x000FFC00
+#define PICMR_MASK_8MB       0x000FF800
+#define PICMR_MASK_16MB      0x000FF000
+#define PICMR_MASK_32MB      0x000FE000
+#define PICMR_MASK_64MB      0x000FC000
+#define PICMR_MASK_128MB     0x000F8000
+#define PICMR_MASK_256MB     0x000F0000
+#define PICMR_MASK_512MB     0x000E0000
+#define PICMR_MASK_1GB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define	PCI_ERROR_STATUS_REG		0x10884
+#define	PCI_ERROR_MASK_REG		0x10888
+#define	PCI_ERROR_CONTROL_REG		0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
+#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
+#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
+#define	PCI_ERROR_PCI_NO_RSP			0x00000008
+#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
+#define	PCI_ERROR_PCI_SERR			0x00000020
+#define	PCI_ERROR_PCI_PERR_RD			0x00000040
+#define	PCI_ERROR_PCI_PERR_WR			0x00000080
+#define	PCI_ERROR_I2O_OFQO			0x00000100
+#define	PCI_ERROR_I2O_IPQO			0x00000200
+#define	PCI_ERROR_IRA				0x00000400
+#define	PCI_ERROR_NMI				0x00000800
+#define	PCI_ERROR_I2O_DBMC			0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 806085e..6b131b6 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -200,6 +200,11 @@
 #define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
 #define SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */
 #define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT		15
+#define HID0_DCE_SHIFT		14
+#define HID0_DLOCK_SHIFT	12
+
 #define   HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
 #define   HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
 #define   HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
@@ -211,10 +216,10 @@
 #define   HID0_NAP	(1<<22)
 #define   HID0_SLEEP	(1<<21)
 #define   HID0_DPM	(1<<20)
-#define   HID0_ICE	(1<<15)		/* Instruction Cache Enable */
-#define   HID0_DCE	(1<<14)		/* Data Cache Enable */
+#define   HID0_ICE	(1<<HID0_ICE_SHIFT)	/* Instruction Cache Enable */
+#define   HID0_DCE	(1<<HID0_DCE_SHIFT)	/* Data Cache Enable */
 #define   HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
-#define   HID0_DLOCK	(1<<12)		/* Data Cache Lock */
+#define   HID0_DLOCK	(1<<HID0_DLOCK_SHIFT)	/* Data Cache Lock */
 #define   HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
 #define   HID0_DCFI	(1<<10)		/* Data Cache Flash Invalidate */
 #define   HID0_DCI	HID0_DCFI
@@ -420,6 +425,7 @@
 #define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
 #define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
 #define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
+#define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
 
 #define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
 #define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
@@ -584,6 +590,7 @@
 #define MAS4	SPRN_MAS4
 #define MAS5	SPRN_MAS5
 #define MAS6	SPRN_MAS6
+#define MAS7	SPRN_MAS7
 
 /* Device Control Registers */
 
@@ -794,6 +801,8 @@
 #define SVR_8560	0x8070
 #define SVR_8555	0x8079
 #define SVR_8541	0x807A
+#define SVR_8548	0x8031
+#define SVR_8548_E	0x8039
 
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index a759315..5b6cd6f 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -45,6 +45,9 @@ typedef struct bd_info {
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 #endif
+#if defined(CONFIG_MPC83XX)
+	unsigned long	bi_immrbar;
+#endif
 #if defined(CONFIG_MPC8220)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 	unsigned long   bi_inpfreq;     /* Input Freq, In MHz */
@@ -59,7 +62,7 @@ typedef struct bd_info {
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
 	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
 	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
diff --git a/include/common.h b/include/common.h
index 625c389..efc638d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -83,6 +83,10 @@ typedef volatile unsigned char	vu_char;
 #include <mpc85xx.h>
 #include <asm/immap_85xx.h>
 #endif
+#ifdef CONFIG_MPC83XX
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
 #ifdef	CONFIG_4xx
 #include <ppc4xx.h>
 #endif
@@ -409,8 +413,9 @@ int	sdram_adjust_866 (void);
 int	adjust_sdram_tbs_8xx (void);
 #if defined(CONFIG_8260)
 int	prt_8260_clks (void);
-#endif
-#if defined(CONFIG_MPC5xxx)
+#elif defined(CONFIG_MPC83XX)
+int print_clock_conf(void);
+#elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
 #if defined(CONFIG_MPC8220)
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index ce7ccc2..09185b1 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -35,6 +35,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /*
  * select serial console configuration
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 0e0876f..c50870f 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -36,6 +36,7 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
 #define CONFIG_PCI
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /*
  * select serial console configuration
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index c4fb01d..729b048 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -37,6 +37,7 @@
 #define CONFIG_MPC8272_FAMILY	1
 #define CONFIG_IDS8247		1
 #define CPU_ID_STR		"MPC8247"
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index 6b7079e..c1565fc 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -40,6 +40,8 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */
 
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
 /*-----------------------------------------------------------------------
  * select serial console configuration
  *
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 8aa18ca..65056a2 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -31,6 +31,7 @@
 
 #define CONFIG_MPC8260			/* This is an MPC8260 CPU               */
 #define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /*-----------------------------------------------------------------------
  * Select serial console configuration
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index ed8fe6b..bba476a 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -42,6 +42,8 @@
 
 #define CONFIG_MPC8260ADS	1	/* Motorola PQ2 ADS family board */
 
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
 /*
  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  */
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 89f2d09..d8e91a5 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -51,6 +51,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
new file mode 100644
index 0000000..d6d2fab
--- /dev/null
+++ b/include/configs/MPC8349ADS.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8349ads board configuration file
+ *
+ * Please refer to doc/README.mpc83xxads for more info.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_MII
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_MPC8349ADS	1	/* MPC8349ADS board specific */
+
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+
+#define CFG_IMMRBAR		0xE0000000
+
+#undef CFG_DRAM_TEST                   /* memory test, takes time */
+#define CFG_MEMTEST_START       0x00000000      /* memtest region */
+#define CFG_MEMTEST_END         0x00100000
+
+/*
+ * DDR Setup
+ */
+
+#define CFG_DDR_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#undef  CONFIG_DDR_2T_TIMING
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+	/*
+	 * Determine DDR configuration from I2C interface.
+	 */
+	#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#else
+	/*
+	 * Manually set up DDR parameters
+	 */
+	#define CFG_DDR_SIZE	    256		/* Mb */
+	#define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+	#define CFG_DDR_TIMING_1	0x37344321
+	#define CFG_DDR_TIMING_2	0x00000800  /* P9-45,may need tuning */
+	#define CFG_DDR_CONTROL 	0xc2000000  /* unbuffered,no DYN_PWR */
+	#define CFG_DDR_MODE    	0x00000062  /* DLL,normal,seq,4/2.5 */
+	#define CFG_DDR_INTERVAL	0x05200100  /* autocharge,no open page */
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI			/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* FLASH size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+			(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+			BR_V)			/* valid */
+#define CFG_OR0_PRELIM		0xff806ff7	/* 16Mb Flash size*/
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE	/* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM  0x80000016		/* 16Mb window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP      0x7F000000
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BCSR             0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR	/* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM  0x8000000E		/* Access window size 32K */
+#define CFG_BR1_PRELIM	  (CFG_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE8f0	/* length 32K */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000   /* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x1000	     /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE  	0x100     /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR	0x00000000
+
+#define CFG_LB_SDRAM	/* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
+#define CFG_LBLAWBAR2_PRELIM	0xF0000000
+#define CFG_LBLAWAR2_PRELIM	0x80000019 /*64M*/
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM	0xfc006901
+
+#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
+				| CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR8		\
+				| CFG_LBC_LSDMR_PRETOACT6	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC3		\
+				| CFG_LBC_LSDMR_CL3		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET      0x3000
+#define CFG_I2C2_OFFSET      0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+
+/* IO Configuration */
+#define CFG_IO_CONF (\
+	IO_CONF_UART |\
+	IO_CONF_TSEC1 |\
+	IO_CONF_IRQ0 |\
+	IO_CONF_IRQ1 |\
+	IO_CONF_IRQ2 |\
+	IO_CONF_IRQ3 |\
+	IO_CONF_IRQ4 |\
+	IO_CONF_IRQ5 |\
+	IO_CONF_IRQ6 |\
+	IO_CONF_IRQ7 )
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xA0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1	1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2	1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C       \
+				| CFG_CMD_MII       \
+				)
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+#define CFG_HID0_INIT 0x000000000
+
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+/* #define CFG_HID0_FINAL		(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+#define CFG_HID2 0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:04:9f:11:22:33
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:7D:01
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME	 unknown
+#define CONFIG_ROOTPATH	 /nfsroot
+#define CONFIG_BOOTFILE	 your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+
+#define	CONFIG_EXTRA_ENV_SETTINGS			\
+	"netdev=eth0\0"					\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=400000\0"				\
+	"ramdiskfile=ramfs.83xx\0"
+
+#define CONFIG_NFSBOOTCOMMAND				\
+	"setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=$serverip:$rootpath "			\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 1c11c6f..131c832 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -41,14 +41,20 @@
 #define CONFIG_MPC8540		1	/* MPC8540 specific */
 #define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */
 
+#ifndef CONFIG_HAS_FEC
+#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
+#endif
+
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 
 /*
  * sysclk for MPC85xx
@@ -338,17 +344,24 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 
+
+#if CONFIG_HAS_FEC
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
+#endif
 
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
new file mode 100644
index 0000000..1af9231
--- /dev/null
+++ b/include/configs/MPC8540EVAL.h
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Modified by Lunsheng Wang, lunsheng@sohu.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8540eval board configuration file */
+/* please refer to doc/README.mpc85xxads for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	    /* BOOKE 			*/
+#define CONFIG_E500		1	    /* BOOKE e500 family	*/
+#define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
+#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
+#define CONFIG_MPC8540EVAL	1	    /* MPC8540EVAL board specific */
+
+#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
+#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
+ * Not availabe for EVAL board
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+/* sysclk for MPC8540EVAL */
+#if defined(CONFIG_SYSCLK_66M)
+	/*
+	 * the oscillator on board is 66Mhz
+	 * can also get 66M clock from external PCI
+	 */
+	#define CONFIG_SYS_CLK_FREQ   66000000
+#else
+	#define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#undef  CONFIG_BTB			    /* toggle branch predition */
+#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+
+#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00400000
+
+#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
+#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
+#define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
+#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit	*/
+#endif
+
+#define	CFG_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
+#define CFG_FLASH_CFI		1
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/* Here some DDR setting should be added */
+
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
+#define CFG_OR2_PRELIM		0xfc006901
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM          0xffffe1f1
+#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_BAUDRATE	 	115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/* General PCI */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	0x80000000
+#define CFG_PCI_MEM_SIZE	0x20000000
+#define CFG_PCI_IO_BASE         0xe2000000
+
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100
+#define CONFIG_TULIP
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#if !defined(CONFIG_PCI_PNP)
+#define PCI_ENET0_IOADDR      0xe0000000
+#define PCI_ENET0_MEMADDR     0xe0000000
+#define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#elif defined(CONFIG_TSEC_ENET)
+#define CONFIG_NET_MULTI 	1
+#define CONFIG_MII		1	/* MII PHY management	*/
+#define CONFIG_MPC85XX_TSEC1    1
+#define CONFIG_MPC85XX_TSEC1_NAME      "TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME      "TSEC1"
+#define CONFIG_MPC85XX_FEC      1
+#define CONFIG_MPC85XX_FEC_NAME                "FEC"
+#define TSEC1_PHY_ADDR          7
+#define	TSEC2_PHY_ADDR		4
+#define FEC_PHY_ADDR            2
+#define TSEC1_PHYIDX            0
+#define TSEC2_PHYIDX            0
+#define FEC_PHYIDX              0
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME                "TSEC0"
+
+#define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
+#define INTEL_LXT971_PHY	1
+#endif
+
+#undef DEBUG
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
+#define CFG_ENV_SIZE		0x2000
+#else
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#endif
+#define CFG_ENV_SIZE		0x2000
+#else
+/* #define CFG_NO_FLASH		1 */	/* Flash is not usable now	*/
+#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"
+#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING \
+				| CFG_CMD_PCI | CFG_CMD_I2C ) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING \
+				| CFG_CMD_I2C ) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI \
+				| CFG_CMD_PING | CFG_CMD_I2C )
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_LOAD_ADDR   0x2000000       /* default load address */
+#define CFG_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*****************************/
+/* Environment Configuration */
+/*****************************/
+/* The mac addresses for all ethernet interface */
+/* NOTE: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR  00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP         192.168.101.1
+#define CONFIG_IPADDR           192.168.101.11
+#define CONFIG_GATEWAYIP        192.168.101.0
+#define CONFIG_NETMASK          255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
+
+#define CONFIG_HOSTNAME         MPC8540EVAL
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 3dd4957..c96b98b 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -33,6 +33,7 @@
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8541		1	/* MPC8541 specific */
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
 
@@ -40,9 +41,12 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
@@ -94,18 +98,50 @@ extern unsigned long get_clock_freq(void);
 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 #endif
 
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
 /*
- * SDRAM on the Local Bus
+ * Local Bus Definitions
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
 #define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
 
-#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit */
-#define CFG_BR1_PRELIM		0xff001001	/* port size 16bit */
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
 
-#define	CFG_OR0_PRELIM		0xff806e61	/* 8MB Flash */
-#define	CFG_OR1_PRELIM		0xff806e61	/* 8MB Flash */
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
 
 #define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
@@ -120,11 +156,12 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
-#undef CONFIG_CLOCKS_IN_MHZ
 
 /*
- * Local Bus Definitions
+ * SDRAM on the Local Bus
  */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
@@ -326,7 +363,9 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -334,7 +373,9 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
new file mode 100644
index 0000000..4ca8bc3
--- /dev/null
+++ b/include/configs/MPC8548CDS.h
@@ -0,0 +1,521 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8548cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548		1	/* MPC8548 specific */
+#define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
+
+#undef CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
+
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
+
+#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
+				| CFG_LBC_LSDMR_PRETOACT7	\
+				| CFG_LBC_LSDMR_ACTTORW7	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC4		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CFG_BR3_PRELIM   0xf8000801
+#define CFG_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR      0xe0000000
+    #define PCI_ENET0_MEMADDR     0xe0000000
+    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
+#define CONFIG_MPC85XX_TSEC3	1
+#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
+#define CONFIG_MPC85XX_TSEC4	1
+#define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define FEC_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define FEC_PHYIDX		0
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=400000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 379a12c..a44e3ec 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -33,6 +33,7 @@
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8555		1	/* MPC8555 specific */
 #define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
 
@@ -40,9 +41,12 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
@@ -94,18 +98,50 @@ extern unsigned long get_clock_freq(void);
 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 #endif
 
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
 /*
- * SDRAM on the Local Bus
+ * Local Bus Definitions
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
 #define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
 
-#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit */
-#define CFG_BR1_PRELIM		0xff001001	/* port size 16bit */
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
 
-#define	CFG_OR0_PRELIM		0xff806e61	/* 8MB Flash */
-#define	CFG_OR1_PRELIM		0xff806e61	/* 8MB Flash */
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
 
 #define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
@@ -120,11 +156,12 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
-#undef CONFIG_CLOCKS_IN_MHZ
 
 /*
- * Local Bus Definitions
+ * SDRAM on the Local Bus
  */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
@@ -326,7 +363,9 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -334,7 +373,9 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 7271737..db878cb 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -38,7 +38,7 @@
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
-#define CONFIG_MPC8560		1	/* MPC8560 specific */
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
 
 #define CONFIG_PCI
@@ -46,10 +46,12 @@
 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 
 /*
  * sysclk for MPC85xx
@@ -337,13 +339,17 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index a4c4fc9..9ca1e52 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM826		1	/* ...on a PM8260 module	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/
 
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 5b71c96..7d98df5 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM828		1	/* ...on a PM828 module */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier */
 
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index b3e1f5e..07e3f06 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -45,10 +45,12 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #undef	CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 
 /*
  * sysclk for MPC85xx
@@ -256,17 +258,21 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
 
-#define CONFIG_ETHPRIME		"ENET0"
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #define	CONFIG_HAS_ETH1		1
 #define	CONFIG_HAS_ETH2		1
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index cdf716c..6ae9403 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -173,6 +173,7 @@
 
 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index f98a6c6..a552970 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -33,6 +33,8 @@
 #define CPU_ID_STR		"MPC8250"
 #endif /* CONFIG_MPC8248 */
 
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
 #define CONFIG_RATTLER			/* Analogue&Micro Rattler board */
 
 #undef DEBUG
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 60561eb..0451b20 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -46,7 +46,7 @@
 #define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
 
 
-#define CONFIG_MPC8560		1	/* MPC8560 (CPU) specific		*/
+#define CONFIG_CPM2		1	/* has CPM2 */
 
 #define CONFIG_SBC8540      	1   	/* configuration for SBC8560 board */
 
@@ -227,10 +227,14 @@
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S		/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
 
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h
index 6bd0abe..8b46a17 100644
--- a/include/configs/SBC8560.h
+++ b/include/configs/SBC8560.h
@@ -46,7 +46,7 @@
 #define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
 
 
-#define CONFIG_MPC8560		1	/* MPC8560 (CPU) specific		*/
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_SBC8560      	1   	/* configuration for SBC8560 board */
 
 #define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific (supplement)	*/
@@ -215,10 +215,14 @@
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S		/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
 
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index e4533b4..91914e8 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -36,6 +36,7 @@
 #define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 #define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
 #define CONFIG_SCM              1	/* ...on a System Controller Module	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #if (CONFIG_TQM8260 <= 100)
 #  error "TQM8260 module revison not supported"
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index eaf138a..e6266b5 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -52,6 +52,8 @@
 #define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
 #endif
 
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
 #define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
diff --git a/include/configs/TQM8540.h b/include/configs/TQM8540.h
index 9dc77c4..8438b93 100644
--- a/include/configs/TQM8540.h
+++ b/include/configs/TQM8540.h
@@ -280,20 +280,24 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME	"FEC"
 #define FEC_PHY_ADDR		2
 #define FEC_PHYIDX		0
 
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 
-#define CONFIG_ETHPRIME		"ENET1"
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC1"
 
 #endif	/* CONFIG_TSEC_ENET */
 
diff --git a/include/configs/TQM8560.h b/include/configs/TQM8560.h
index f418e26..1466f31 100644
--- a/include/configs/TQM8560.h
+++ b/include/configs/TQM8560.h
@@ -276,6 +276,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC2_PHY_ADDR		1
 #define TSEC2_PHYIDX		0
 
@@ -288,7 +289,7 @@
 #define CFG_CPMFCR_RAMTYPE    0
 #define CFG_FCC_PSMR          (FCC_PSMR_FDE | FCC_PSMR_LPB)
 
-#define CONFIG_ETHPRIME		"ENET1"
+#define CONFIG_ETHPRIME		"TSEC1"
 
 /*
  * Environment
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 6857973..f71e691 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -30,6 +30,7 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU      */
 #define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
 #define CPU_ID_STR		"MPC8265"
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #undef DEBUG
 
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 2751248..881a4ca 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -35,6 +35,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_ATC		1	/* ...on a ATC board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /*
  * select serial console configuration
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index b3ec89b..aea2e64 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -35,6 +35,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
 
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index fb335db..98e1716 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -48,6 +48,8 @@
 #define CFG_EP8260_H2	1
 /* #undef CFG_EP8260_H2  */
 
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
 /* What is the oscillator's (UX2) frequency in Hz? */
 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
 
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 3666bdb..6c08043 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -330,6 +330,7 @@
 
 #define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
 #define CONFIG_GW8260       1   /* on an GW8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 90d6b25..0d62b9e 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -35,6 +35,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
 
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index 2ad2867..60b0b37 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -297,6 +297,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index b1f6cb2..6c9e392 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
 
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index cc9774c..031eba5 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -544,6 +544,7 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_SBC8260		1	/* on an EST SBC8260 Board  */
 #define CONFIG_SACSng		1	/* munged for the SACSng */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index dc9cec3..45e4494 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -481,6 +481,7 @@
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_SBC8260		1	/* on an EST SBC8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 8cf9eeb..5a434dc 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -40,7 +40,7 @@
 #define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
 
 
-#define CONFIG_MPC8560		1	/* MPC8560 specific		*/
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_SBC8560		1	/* configuration for SBC8560 board */
 
 /* XXX flagging this as something I might want to delete */
@@ -210,10 +210,14 @@
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S	1	/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index e9261db..e218597 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -39,7 +39,7 @@
 #define CONFIG_BOOKE		1	/* BOOKE		*/
 #define CONFIG_E500		1	/* BOOKE e500 family	*/
 #define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
-#define CONFIG_MPC8560		1	/* MPC8560 specific	*/
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
 
 #undef  CONFIG_PCI	         	/* pci ethernet support	*/
@@ -227,14 +227,16 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
diff --git a/include/ioports.h b/include/ioports.h
index eba9aee..d7e19e1 100644
--- a/include/ioports.h
+++ b/include/ioports.h
@@ -25,7 +25,7 @@ typedef struct {
  * the internal memory map aligns the above structure on
  * a 0x20 byte boundary
  */
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_MPC85xx
 #define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
 #else
 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
new file mode 100644
index 0000000..38f7115
--- /dev/null
+++ b/include/mpc83xx.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc83xx.h
+ *
+ * MPC83xx specific definitions
+ */
+
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially. easier
+ * to implement
+ */
+
+#define MPC83xx_RESET
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define CONFIG_DEFAULT_IMMR 0xFF400000
+
+/*
+ * Watchdog
+ */
+#define SWCRR      0x0204
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
+#define SWCRR_RES  ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+#define SWCNR      0x0208
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES  ~(SWCNR_SWCN)
+
+#define SWSRR      0x020E
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define IMMRBAR 0x0000
+#define IMMRBAR_BASE_ADDR     0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
+#define IMMRBAR_RES           ~(IMMRBAR_BASE_ADDR)
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define LBLAWBAR0 0x0020
+#define LBLAWAR0  0x0024
+#define LBLAWBAR1 0x0028
+#define LBLAWAR1  0x002C
+#define LBLAWBAR2 0x0030
+#define LBLAWAR2  0x0034
+#define LBLAWBAR3 0x0038
+#define LBLAWAR3  0x003C
+
+
+/*
+ * Base Registers & Option Registers
+ */
+#define BR0 0x5000
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA   0xFFFF8000
+#define BR_BA_SHIFT     15
+#define BR_PS   0x00001800
+#define BR_PS_SHIFT     11
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT    9
+#define BR_WP   0x00000100
+#define BR_WP_SHIFT      8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT    5
+#define BR_V    0x00000001
+#define BR_V_SHIFT       0
+#define BR_RES  ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM    0xFFFF8000
+#define OR_GPCM_AM_SHIFT      15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT   12
+#define OR_GPCM_CSNT  0x00000800
+#define OR_GPCM_CSNT_SHIFT    11
+#define OR_GPCM_ACS   0x00000600
+#define OR_GPCM_ACS_SHIFT      9
+#define OR_GPCM_XACS  0x00000100
+#define OR_GPCM_XACS_SHIFT     8
+#define OR_GPCM_SCY   0x000000F0
+#define OR_GPCM_SCY_SHIFT      4
+#define OR_GPCM_SETA  0x00000008
+#define OR_GPCM_SETA_SHIFT     3
+#define OR_GPCM_TRLX  0x00000004
+#define OR_GPCM_TRLX_SHIFT     2
+#define OR_GPCM_EHTR  0x00000002
+#define OR_GPCM_EHTR_SHIFT     1
+#define OR_GPCM_EAD   0x00000001
+#define OR_GPCM_EAD_SHIFT      0
+
+#define OR_UPM_AM    0xFFFF8000
+#define OR_UPM_AM_SHIFT      15
+#define OR_UPM_XAM   0x00006000
+#define OR_UPM_XAM_SHIFT     13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT   12
+#define OR_UPM_BI    0x00000100
+#define OR_UPM_BI_SHIFT       8
+#define OR_UPM_TRLX  0x00000004
+#define OR_UPM_TRLX_SHIFT     2
+#define OR_UPM_EHTR  0x00000002
+#define OR_UPM_EHTR_SHIFT     1
+#define OR_UPM_EAD   0x00000001
+#define OR_UPM_EAD_SHIFT      0
+
+#define OR_SDRAM_AM    0xFFFF8000
+#define OR_SDRAM_AM_SHIFT      15
+#define OR_SDRAM_XAM   0x00006000
+#define OR_SDRAM_XAM_SHIFT     13
+#define OR_SDRAM_COLS  0x00001C00
+#define OR_SDRAM_COLS_SHIFT    10
+#define OR_SDRAM_ROWS  0x000001C0
+#define OR_SDRAM_ROWS_SHIFT     6
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT    5
+#define OR_SDRAM_EAD   0x00000001
+#define OR_SDRAM_EAD_SHIFT      0
+
+/*
+ * Hard Reset Configration Word - High
+ */
+#define HRCWH_PCI_AGENT              0x00000000
+#define HRCWH_PCI_HOST               0x80000000
+
+#define HRCWH_32_BIT_PCI             0x00000000
+#define HRCWH_64_BIT_PCI             0x40000000
+
+#define HRCWH_PCI1_ARBITER_DISABLE   0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE    0x20000000
+
+#define HRCWH_PCI2_ARBITER_DISABLE   0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE    0x10000000
+
+#define HRCWH_CORE_DISABLE           0x08000000
+#define HRCWH_CORE_ENABLE            0x00000000
+
+#define HRCWH_FROM_0X00000100        0x00000000
+#define HRCWH_FROM_0XFFF00100        0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE        0x00000000
+#define HRCWH_BOOTSEQ_NORMAL         0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED       0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE    0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE     0x00800000
+
+#define HRCWH_ROM_LOC_DDR_SDRAM      0x00000000
+#define HRCWH_ROM_LOC_PCI1           0x00100000
+#define HRCWH_ROM_LOC_PCI2           0x00200000
+#define HRCWH_ROM_LOC_LOCAL_8BIT     0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT    0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT    0x00700000
+
+#define HRCWH_TSEC1M_IN_RGMII        0x00000000
+#define HRCWH_TSEC1M_IN_RTBI         0x00004000
+#define HRCWH_TSEC1M_IN_GMII         0x00008000
+#define HRCWH_TSEC1M_IN_TBI          0x0000C000
+
+#define HRCWH_TSEC2M_IN_RGMII        0x00000000
+#define HRCWH_TSEC2M_IN_RTBI         0x00001000
+#define HRCWH_TSEC2M_IN_GMII         0x00002000
+#define HRCWH_TSEC2M_IN_TBI          0x00003000
+
+#define HRCWH_BIG_ENDIAN             0x00000000
+#define HRCWH_LITTLE_ENDIAN          0x00000008
+
+/*
+ * Hard Reset Configration Word - Low
+ */
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
+
+#define HRCWL_DDR_TO_SCB_CLK_1X1     0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1     0x40000000
+
+#define HRCWL_CSB_TO_CLKIN_16X1      0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1       0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1       0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1       0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1       0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1       0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1       0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1       0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1       0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1       0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1      0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1      0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1      0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1      0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1      0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1      0x0F000000
+
+#define HRCWL_VCO_BYPASS             0x00000000
+#define HRCWL_VCO_1X2                0x00000000
+#define HRCWL_VCO_1X4                0x00200000
+#define HRCWL_VCO_1X8                0x00400000
+
+#define HRCWL_CORE_TO_CSB_BYPASS     0x00000000
+#define HRCWL_CORE_TO_CSB_1X1        0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1      0x00030000
+#define HRCWL_CORE_TO_CSB_2X1        0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1      0x00050000
+#define HRCWL_CORE_TO_CSB_3X1        0x00060000
+
+/*
+ * LCRR - Clock Ratio Register (10.3.1.16)
+ */
+#define LCRR_DBYP      0x80000000
+#define LCRR_DBYP_SHIFT        31
+#define LCRR_BUFCMDC   0x30000000
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_BUFCMDC_SHIFT     28
+#define LCRR_ECL       0x03000000
+#define LCRR_ECL_4     0x00000000
+#define LCRR_ECL_5     0x01000000
+#define LCRR_ECL_6     0x02000000
+#define LCRR_ECL_7     0x03000000
+#define LCRR_ECL_SHIFT         24
+#define LCRR_EADC      0x00030000
+#define LCRR_EADC_1    0x00010000
+#define LCRR_EADC_2    0x00020000
+#define LCRR_EADC_3    0x00030000
+#define LCRR_EADC_4    0x00000000
+#define LCRR_EADC_SHIFT        16
+#define LCRR_CLKDIV    0x0000000F
+#define LCRR_CLKDIV_2  0x00000002
+#define LCRR_CLKDIV_4  0x00000004
+#define LCRR_CLKDIV_8  0x00000008
+#define LCRR_CLKDIV_SHIFT       0
+
+#endif	/* __MPC83XX_H__ */
diff --git a/include/net.h b/include/net.h
index e50c381..623d225 100644
--- a/include/net.h
+++ b/include/net.h
@@ -29,7 +29,7 @@
 # endif
 #endif	/* CONFIG_MPC5xxx */
 
-#if !defined(CONFIG_NET_MULTI) && (defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2)
 #include <config.h>
 #if defined(CONFIG_ETHER_ON_FCC)
 #if defined(CONFIG_ETHER_ON_SCC)
diff --git a/include/spd.h b/include/spd.h
index 1ad4d80..54b60d1 100644
--- a/include/spd.h
+++ b/include/spd.h
@@ -25,54 +25,82 @@
 #define _SPD_H_
 
 typedef struct spd_eeprom_s {
-   unsigned char info_size;   /* # of bytes written into serial memory           */
-   unsigned char chip_size;   /* Total # of bytes of SPD memory device           */
-   unsigned char mem_type;    /* Fundamental memory type (FPM, EDO, SDRAM...)    */
-   unsigned char nrow_addr;   /* # of Row Addresses on this assembly             */
-   unsigned char ncol_addr;   /* # of Column Addresses on this assembly          */
-   unsigned char nrows;       /* # of Module Rows on this assembly               */
-   unsigned char dataw_lsb;   /* Data Width of this assembly                     */
-   unsigned char dataw_msb;   /* ... Data Width continuation                     */
-   unsigned char voltage;     /* Voltage interface standard of this assembly     */
-   unsigned char clk_cycle;   /* SDRAM Cycle time at CL=X                        */
-   unsigned char clk_access;  /* SDRAM Access from Clock at CL=X                 */
-   unsigned char config;      /* DIMM Configuration type (non-parity, ECC)       */
-   unsigned char refresh;     /* Refresh Rate/Type                               */
-   unsigned char primw;       /* Primary SDRAM Width                             */
-   unsigned char ecw;         /* Error Checking SDRAM width                      */
-   unsigned char min_delay;   /* Min Clock Delay for Back to Back Random Address */
-   unsigned char burstl;      /* Burst Lengths Supported                         */
-   unsigned char nbanks;      /* # of Banks on Each SDRAM Device                 */
-   unsigned char cas_lat;     /* CAS# Latencies Supported                        */
-   unsigned char cs_lat;      /* CS# Latency                                     */
-   unsigned char write_lat;   /* Write Latency (also called Write Recovery time) */
-   unsigned char mod_attr;    /* SDRAM Module Attributes                         */
-   unsigned char dev_attr;    /* SDRAM Device Attributes                         */
-   unsigned char clk_cycle2;  /* Min SDRAM Cycle time at CL=X-1                  */
-   unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1               */
-   unsigned char clk_cycle3;  /* Min SDRAM Cycle time at CL=X-2                  */
-   unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2           */
-   unsigned char trp;         /* Min Row Precharge Time (tRP)                    */
-   unsigned char trrd;        /* Min Row Active to Row Active (tRRD)             */
-   unsigned char trcd;        /* Min RAS to CAS Delay (tRCD)                     */
-   unsigned char tras;        /* Minimum RAS Pulse Width (tRAS)                  */
-   unsigned char row_dens;    /* Density of each row on module                   */
-   unsigned char ca_setup;    /* Command and Address signal input setup time     */
-   unsigned char ca_hold;     /* Command and Address signal input hold time      */
-   unsigned char data_setup;  /* Data signal input setup time                    */
-   unsigned char data_hold;   /* Data signal input hold time                     */
-   unsigned char sset[26];    /* Superset Information (may be used in future)    */
-   unsigned char spd_rev;     /* SPD Data Revision Code                          */
-   unsigned char cksum;       /* Checksum for bytes 0-62                         */
-   unsigned char mid[8];      /* Manufacturer's JEDEC ID code per JEP-108E       */
-   unsigned char mloc;        /* Manufacturing Location                          */
-   unsigned char mpart[18];   /* Manufacturer's Part Number                      */
-   unsigned char rev[2];      /* Revision Code                                   */
-   unsigned char mdate[2];    /* Manufacturing Date                              */
-   unsigned char sernum[4];   /* Assembly Serial Number                          */
-   unsigned char mspec[27];   /* Manufacturer Specific Data                      */
-   unsigned char freq;        /* Intel specification frequency                   */
-   unsigned char intel_cas;   /* Intel Specification CAS# Latency support        */
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 # of Module Rows on this assembly */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time at CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clock at CL=X */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time at CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time at CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char row_dens;    /* 31 Density of each row on module */
+	unsigned char ca_setup;    /* 32 Cmd + Addr signal input setup time */
+	unsigned char ca_hold;     /* 33 Cmd and Addr signal input hold time */
+	unsigned char data_setup;  /* 34 Data signal input setup time */
+	unsigned char data_hold;   /* 35 Data signal input hold time */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew tQHS */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char res[15];     /* 47-xx IDD in SPD and Reserved space */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-108E */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99 Manufacturer Specific Data */
+
+	/*
+	 * Open for Customer Use starting with byte 128.
+	 */
+	unsigned char freq;        /* 128 Intel spec: frequency */
+	unsigned char intel_cas;   /* 129 Intel spec: CAS# Latency support */
 } spd_eeprom_t;
 
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+
 #endif /* _SPD_H_ */
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 5951d56..c4b16e8 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -50,7 +50,7 @@
 #include <net.h>
 #include <serial.h>
 #ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
 #include <commproc.h>
 #endif
 #endif
@@ -272,7 +272,7 @@ init_fnc_t *init_sequence[] = {
 	init_timebase,
 #endif
 #ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
 	dpram_init,
 #endif
 #endif
@@ -293,6 +293,11 @@ init_fnc_t *init_sequence[] = {
 	prt_8260_rsr,
 	prt_8260_clks,
 #endif /* CONFIG_8260 */
+
+#if defined(CONFIG_MPC83XX)
+	print_clock_conf,
+#endif
+
 	checkcpu,
 #if defined(CONFIG_MPC5xxx)
 	prt_mpc5xxx_clks,
@@ -360,7 +365,7 @@ void board_init_f (ulong bootflag)
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 #endif
@@ -495,6 +500,9 @@ void board_init_f (ulong bootflag)
 #if defined(CONFIG_MPC5xxx)
 	bd->bi_mbar_base = CFG_MBAR;	/* base of internal registers */
 #endif
+#if defined(CONFIG_MPC83XX)
+	bd->bi_immrbar = CFG_IMMRBAR;
+#endif
 #if defined(CONFIG_MPC8220)
 	bd->bi_mbar_base = CFG_MBAR;	/* base of internal registers */
 	bd->bi_inpfreq   = gd->inp_clk;
@@ -521,12 +529,12 @@ void board_init_f (ulong bootflag)
 	WATCHDOG_RESET ();
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
 	bd->bi_cpmfreq = gd->cpm_clk;
 	bd->bi_brgfreq = gd->brg_clk;
 	bd->bi_sccfreq = gd->scc_clk;
 	bd->bi_vco     = gd->vco_out;
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_CPM2 */
 #if defined(CONFIG_MPC5xxx)
 	bd->bi_ipbfreq = gd->ipb_clk;
 	bd->bi_pcifreq = gd->pci_clk;
diff --git a/net/eth.c b/net/eth.c
index 29c24c8..61862aa 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -52,7 +52,7 @@ extern int rtl8139_initialize(bd_t*);
 extern int rtl8169_initialize(bd_t*);
 extern int scc_initialize(bd_t*);
 extern int skge_initialize(bd_t*);
-extern int tsec_initialize(bd_t*, int);
+extern int tsec_initialize(bd_t*, int, char *);
 
 static struct eth_device *eth_devices, *eth_current;
 
@@ -155,13 +155,28 @@ int eth_initialize(bd_t *bis)
 	skge_initialize(bis);
 #endif
 #if defined(CONFIG_MPC85XX_TSEC1)
-	tsec_initialize(bis, 0);
+	tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME);
+#elif defined(CONFIG_MPC83XX_TSEC1)
+	tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME);
 #endif
 #if defined(CONFIG_MPC85XX_TSEC2)
-	tsec_initialize(bis, 1);
+	tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME);
+#elif defined(CONFIG_MPC83XX_TSEC2)
+	tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME);
 #endif
 #if defined(CONFIG_MPC85XX_FEC)
-	tsec_initialize(bis, 2);
+	tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
+#else
+#    if defined(CONFIG_MPC85XX_TSEC3)
+	tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME);
+#    elif defined(CONFIG_MPC83XX_TSEC3)
+	tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME);
+#    endif
+#    if defined(CONFIG_MPC85XX_TSEC4)
+	tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME);
+#    elif defined(CONFIG_MPC83XX_TSEC4)
+	tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
+#    endif
 #endif
 #if defined(CONFIG_AU1X00)
 	au1x00_enet_initialize(bis);