ColdFire: Add M5253EVBE platform for MCF52x2

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

18 files changed, 1010 insertions, 35 deletions

diff --git a/CREDITS b/CREDITS
index b31125b..b1abad3 100644
--- a/CREDITS
+++ b/CREDITS
@@ -494,3 +494,8 @@ E: Tsi-Chung.Liew@freescale.com
 D: Support for ColdFire MCF532x
 W: www.freescale.com
 
+N: Hayden Fraser
+E: Hayden.Fraser@freescale.com
+D: Support for ColdFire MCF5253
+W: www.freescale.com
+
diff --git a/MAKEALL b/MAKEALL
index 4467d75..890ee39 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -618,6 +618,8 @@ LIST_coldfire="			\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
 	idmr			\
+	M5249EVB		\
+	M5253EVB		\
 	M5271EVB		\
 	M5272C3			\
 	M5282EVB		\
diff --git a/Makefile b/Makefile
index af49438..e5995eb 100644
--- a/Makefile
+++ b/Makefile
@@ -1642,6 +1642,9 @@ ZPC1900_config: unconfig
 M5249EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
 
+M5253EVBE_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
+
 cobra5272_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
 
diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile
new file mode 100644
index 0000000..424ab1c
--- /dev/null
+++ b/board/freescale/m5253evbe/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk
new file mode 100644
index 0000000..ccb2cf7
--- /dev/null
+++ b/board/freescale/m5253evbe/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
new file mode 100644
index 0000000..67fab5b
--- /dev/null
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5253 EVBE\n");
+	return 0;
+};
+
+long int initdram(int board_type)
+{
+	int i;
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+		u32 RC, dramsize;
+
+		RC = (CFG_CLK / 1000000) >> 1;
+		RC = (RC * 15) >> 4;
+
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+
+		/* Initialize DMR0 */
+		dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
+		mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
+
+		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		udelay(500);
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
+
+		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+	}
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
+	};
+
+	if (idereset) {
+		ata->cr = 0;	/* control reset */
+		udelay(100);
+	} else {
+		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		ata->t1 = CALC_TIMING(piotms[2][0]);
+		ata->t2w = CALC_TIMING(piotms[2][1]);
+		ata->t2r = CALC_TIMING(piotms[2][1]);
+		ata->ta = CALC_TIMING(piotms[2][8]);
+		ata->trd = CALC_TIMING(piotms[2][7]);
+		ata->t4 = CALC_TIMING(piotms[2][3]);
+		ata->t9 = CALC_TIMING(piotms[2][6]);
+
+		ata->cr = 0x40;	/* IORDY enable */
+		udelay(2000);
+		ata->cr |= 0x01;	/* IORDY enable */
+	}
+}
+#endif				/* CONFIG_CMD_IDE */
+
diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds
new file mode 100644
index 0000000..e2fd070
--- /dev/null
+++ b/board/freescale/m5253evbe/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 96fe371..71ea408 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -205,7 +205,7 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 };
 #endif
 
-#ifdef CONFIG_M5249		/* test-only: todo... */
+#ifdef CONFIG_M5249
 int checkcpu(void)
 {
 	char buf[32];
@@ -225,3 +225,33 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 	return 0;
 };
 #endif
+
+#ifdef CONFIG_M5253
+int checkcpu(void)
+{
+	char buf[32];
+
+	unsigned char resetsource = mbar_readLong(SIM_RSR);
+	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
+	       strmhz(buf, CFG_CLK));
+
+	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
+		printf("Reset:%s%s\n",
+		       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
+		       : "",
+		       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
+		       "");
+	}
+	return 0;
+}
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+	/* enable watchdog, set timeout to 0 and wait */
+	mbar_writeByte(SIM_SYPCR, 0xc0);
+	while (1) ;
+
+	/* we don't return! */
+	return 0;
+};
+#endif
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 5736d0f..f41d77b 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -6,6 +6,10 @@
  * (C) Copyright 2005
  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -29,6 +33,74 @@
 #include <watchdog.h>
 #include <asm/immap.h>
 
+#if defined(CONFIG_M5253)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */
+	mbar_writeByte(MCFSIM_SYPCR, 0x00);
+	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
+	mbar_writeByte(MCFSIM_SWSR, 0x00);
+	mbar_writeByte(MCFSIM_SWDICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
+	mbar_writeByte(MCFSIM_I2CICR, 0x00);
+	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
+	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
+	mbar_writeByte(MCFSIM_ICR6, 0x00);
+	mbar_writeByte(MCFSIM_ICR7, 0x00);
+	mbar_writeByte(MCFSIM_ICR8, 0x00);
+	mbar_writeByte(MCFSIM_ICR9, 0x00);
+	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
+
+	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
+	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
+	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
+
+	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
+
+	/*
+	 *  Setup chip selects...
+	 */
+
+	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
+	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
+	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
+
+	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
+	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
+	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+
+	/* enable instruction cache now */
+	icache_enable();
+}
+
+/*initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	/* Setup Ports: */
+	switch (CFG_UART_PORT) {
+	case 0:
+		break;
+	case 1:
+		break;
+	case 2:
+		break;
+	}
+}
+#endif				/* #if defined(CONFIG_M5253) */
+
 #if defined(CONFIG_M5271)
 void cpu_init_f(void)
 {
@@ -394,26 +466,6 @@ void uart_port_conf(void)
  */
 void cpu_init_f(void)
 {
-#ifndef CFG_PLL_BYPASS
-	/*
-	 *  Setup the PLL to run at the specified speed
-	 *
-	 */
-	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
-	unsigned long pllcr;
-#ifdef CFG_FAST_CLK
-	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
-#else
-	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
-#endif
-	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
-	mbar2_writeLong(MCFSIM_PLLCR, cpll);	/* Set the PLL to bypass mode (PSTCLK = crystal) */
-	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* set the clock speed */
-	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
-	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
-	udelay(0x20);		/* Wait for a lock ... */
-#endif				/* #ifndef CFG_PLL_BYPASS */
-
 	/*
 	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
 	 *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index d9a35bb..2ccbde5 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -1,9 +1,10 @@
 /*
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -82,7 +83,7 @@ void dtimer_intr_setup(void)
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 */
 
-#ifdef	CONFIG_M5249
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 int interrupt_init(void)
 {
 	enable_interrupts();
@@ -94,9 +95,7 @@ int interrupt_init(void)
 void dtimer_intr_setup(void)
 {
 	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
-	mbar_writeByte(MCFSIM_TIMER2ICR,
-		       MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 |
-		       MCFSIM_ICR_PRI3);
+	mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
-#endif				/* CONFIG_M5249 */
+#endif				/* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index ac860b2..bc1e200 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -23,6 +26,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/immap.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,8 +35,37 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int get_clocks (void)
 {
-	gd->cpu_clk = CFG_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
+	unsigned long pllcr;
+
+#ifndef CFG_PLL_BYPASS
+
 #ifdef CONFIG_M5249
+	/* Setup the PLL to run at the specified speed */
+#ifdef CFG_FAST_CLK
+	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
+#else
+	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
+#endif
+#endif				/* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+	pllcr = CFG_PLLCR;
+#endif				/* CONFIG_M5253 */
+
+	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+	mbar2_writeLong(MCFSIM_PLLCR, cpll);	/* Set the PLL to bypass mode (PSTCLK = crystal) */
+	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* set the clock speed */
+	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
+	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
+	udelay(0x20);		/* Wait for a lock ... */
+#endif				/* #ifndef CFG_PLL_BYPASS */
+
+#endif				/* CONFIG_M5249 || CONFIG_M5253 */
+
+	gd->cpu_clk = CFG_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
 	gd->bus_clk = gd->cpu_clk;
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 6783d4d..686e2a5 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -121,7 +121,7 @@ _start:
 	nop
 	move.w #0x2700,%sr
 
-#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
+#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	move.l	#(CFG_MBAR + 1), %d0		/* set MBAR address + valid flag */
 	move.c	%d0, %MBAR
 
@@ -133,7 +133,7 @@ _start:
 
 	move.l	#(CFG_INIT_RAM_ADDR + 1), %d0
 	movec	%d0, %RAMBAR0
-#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
+#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
 
 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
 	/* Initialize IPSBAR */
@@ -407,7 +407,7 @@ icache_state_access_1:
 	rts
 #endif
 
-#ifdef CONFIG_M5249
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	.globl	icache_enable
 icache_enable:
 	/*
diff --git a/doc/README.m5253evbe b/doc/README.m5253evbe
new file mode 100644
index 0000000..7f2afcf
--- /dev/null
+++ b/doc/README.m5253evbe
@@ -0,0 +1,103 @@
+Freescale Amadeus Plus M5253EVBE board
+======================================
+
+Hayden Fraser(Hayden.Fraser@freescale.com)
+Created 06/05/2007
+===========================================
+
+
+1. SWITCH SETTINGS
+==================
+1.1 N/A
+
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+	linux kernel, you can customize it based on your system requirements:
+	SDR:	0x00000000-0x00ffffff
+	SRAM0:	0x20010000-0x20017fff
+	SRAM1:	0x20000000-0x2000ffff
+	MBAR1:	0x10000000-0x4fffffff 
+	MBAR2:	0x80000000-0xCfffffff
+	Flash:	0xffe00000-0xffffffff 
+
+3. DEFINITIONS AND COMPILATION
+==============================
+3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
+	CONFIG_MCF52x2		Processor family 
+	CONFIG_MCF5253		MCF5253 specific
+	CONFIG_M5253EVBE	Amadeus Plus board specific
+	CFG_CLK			Define Amadeus Plus CPU Clock
+	CFG_MBAR		MBAR base address
+	CFG_MBAR2		MBAR2 base address
+
+3.2 Compilation
+	export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
+	cd u-boot-1-2-x
+	make distclean
+	make M5253EVBE_config
+	make
+
+
+4. SCREEN DUMP
+==============
+4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
+
+CPU:   Freescale Coldfire MCF5253 at 62 MHz
+Board: Freescale MCF5253 EVBE
+DRAM:  16 MB
+FLASH:  2 MB
+In:    serial
+Out:   serial
+Err:   serial
+=> flinfo
+
+Bank # 1: CFI conformant FLASH (16 x 16)  Size: 2 MB in 35 Sectors
+  AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
+  Erase timeout: 16384 ms, write timeout: 1 ms
+
+  Sector Start Addresses:
+  FFE00000   RO   FFE04000   RO   FFE06000   RO   FFE08000   RO   FFE10000   RO
+  FFE20000        FFE30000        FFE40000        FFE50000        FFE60000
+  FFE70000        FFE80000        FFE90000        FFEA0000        FFEB0000
+  FFEC0000        FFED0000        FFEE0000        FFEF0000        FFF00000
+  FFF10000        FFF20000        FFF30000        FFF40000        FFF50000
+  FFF60000        FFF70000        FFF80000        FFF90000        FFFA0000
+  FFFB0000        FFFC0000        FFFD0000        FFFE0000        FFFF0000
+
+=> bdinfo
+boot_params = 0x00F62F90
+memstart    = 0x00000000
+memsize     = 0x01000000
+flashstart  = 0xFFE00000
+flashsize   = 0x00200000
+flashoffset = 0x00000000
+baudrate    = 19200 bps
+
+=> printenv
+bootdelay=5
+baudrate=19200
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 134/8188 bytes
+=> saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+. done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+5. COMPILER
+-----------
+To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
+compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
+You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
+codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 3ee7071..bf7b51b 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -43,11 +43,34 @@
 #define CFG_TMRINTR_NO		(31)
 #define CFG_TMRINTR_MASK	(0x00000400)
 #define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0)		/* Level must include inorder to work */
+#define CFG_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
 #define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5249 */
 
+#ifdef CONFIG_M5253
+#include <asm/immap_5253.h>
+#include <asm/m5249.h>
+#include <asm/m5253.h>
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE		(MMAP_INTC)
+#define CFG_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR1)
+#define CFG_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO		(27)
+#define CFG_TMRINTR_MASK	(0x00000400)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5253 */
+
 #ifdef CONFIG_M5271
 #include <asm/immap_5271.h>
 #include <asm/m5271.h>
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
new file mode 100644
index 0000000..aafbdd0
--- /dev/null
+++ b/include/asm-m68k/immap_5253.h
@@ -0,0 +1,95 @@
+/*
+ * MCF5253 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5249__
+#define __IMMAP_5249__
+
+#define MMAP_INTC		(CFG_MBAR + 0x00000040)
+#define MMAP_DTMR0		(CFG_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CFG_MBAR + 0x00000180)
+#define MMAP_UART0		(CFG_MBAR + 0x000001C0)
+#define MMAP_UART1		(CFG_MBAR + 0x00000200)
+#define MMAP_I2C0		(CFG_MBAR + 0x00000280)
+#define MMAP_QSPI		(CFG_MBAR + 0x00000400)
+#define MMAP_CAN0		(CFG_MBAR + 0x00010000)
+#define MMAP_CAN1		(CFG_MBAR + 0x00011000)
+
+#define MMAP_I2C1		(CFG_MBAR2 + 0x00000440)
+#define MMAP_UART2		(CFG_MBAR2 + 0x00000C00)
+
+/*********************************************************************
+* ATA Module (ATAC)
+*********************************************************************/
+
+/* Register read/write struct */
+typedef struct atac {
+	/* PIO */
+	u8 toff;		/* 0x00 */
+	u8 ton;			/* 0x01 */
+	u8 t1;			/* 0x02 */
+	u8 t2w;			/* 0x03 */
+	u8 t2r;			/* 0x04 */
+	u8 ta;			/* 0x05 */
+	u8 trd;			/* 0x06 */
+	u8 t4;			/* 0x07 */
+	u8 t9;			/* 0x08 */
+
+	/* DMA */
+	u8 tm;			/* 0x09 */
+	u8 tn;			/* 0x0A */
+	u8 td;			/* 0x0B */
+	u8 tk;			/* 0x0C */
+	u8 tack;		/* 0x0D */
+	u8 tenv;		/* 0x0E */
+	u8 trp;			/* 0x0F */
+	u8 tzah;		/* 0x10 */
+	u8 tmli;		/* 0x11 */
+	u8 tdvh;		/* 0x12 */
+	u8 tdzfs;		/* 0x13 */
+	u8 tdvs;		/* 0x14 */
+	u8 tcvh;		/* 0x15 */
+	u8 tss;			/* 0x16 */
+	u8 tcyc;		/* 0x17 */
+
+	/* FIFO */
+	u32 fifo32;		/* 0x18 */
+	u16 fifo16;		/* 0x1C */
+	u8 rsvd0[2];
+	u8 ffill;		/* 0x20 */
+	u8 rsvd1[3];
+
+	/* ATA */
+	u8 cr;			/* 0x24 */
+	u8 rsvd2[3];
+	u8 isr;			/* 0x28 */
+	u8 rsvd3[3];
+	u8 ier;			/* 0x2C */
+	u8 rsvd4[3];
+	u8 icr;			/* 0x30 */
+	u8 rsvd5[3];
+	u8 falarm;		/* 0x34 */
+} atac_t;
+
+#endif				/* __IMMAP_5249__ */
diff --git a/include/asm-m68k/m5253.h b/include/asm-m68k/m5253.h
new file mode 100644
index 0000000..eda3472
--- /dev/null
+++ b/include/asm-m68k/m5253.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef m5253_h
+#define m5253_h
+/****************************************************************************/
+
+/*
+* PLL Module (PLL)
+*/
+
+/* Register read/write macros */
+#define PLL_PLLCR		(0x000180)
+
+#define SIM_RSR			(0x000000)
+#define SIM_SYPCR		(0x000001)
+#define SIM_SWIVR		(0x000002)
+#define SIM_SWSR		(0x000003)
+#define SIM_MPARK		(0x00000C)
+
+/* Bit definitions and macros for RSR */
+#define SIM_RSR_SWTR		(0x20)
+#define SIM_RSR_HRST		(0x80)
+
+/* Register read/write macros */
+#define CIM_MISCCR		(0x000500)
+#define CIM_ATA_DADDR		(0x000504)
+#define CIM_ATA_DCOUNT		(0x000508)
+#define CIM_RTC_TIME		(0x00050C)
+#define CIM_USB_CANCLK		(0x000510)
+
+/* Bit definitions and macros for MISCCR */
+#define CIM_MISCCR_ADTA		(0x00000001)
+#define CIM_MISCCR_ADTD		(0x00000002)
+#define CIM_MISCCR_ADIE		(0x00000004)
+#define CIM_MISCCR_ADIC		(0x00000008)
+#define CIM_MISCCR_ADIP		(0x00000010)
+#define CIM_MISCCR_CPUEND	(0x00000020)
+#define CIM_MISCCR_DMAEND	(0x00000040)
+#define CIM_MISCCR_RTCCLR	(0x00000080)
+#define CIM_MISCCR_RTCPL	(0x00000100)
+#define CIM_MISCCR_URIE		(0x00000800)
+#define CIM_MISCCR_URIC		(0x00001000)
+#define CIM_MISCCR_URIP		(0x00002000)
+
+/* Bit definitions and macros for ATA_DADDR */
+#define CIM_ATA_DADDR_ATAADDR(x)	(((x)&0x00003FFF)<<2)
+#define CIM_ATA_DADDR_RAMADDR(x)	(((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for ATA_DCOUNT */
+#define CIM_ATA_DCOUNT_COUNT(x)		(((x)&0x0000FFFF))
+
+#endif				/* m5253_h */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
new file mode 100644
index 0000000..9ad74e2
--- /dev/null
+++ b/include/configs/M5253EVBE.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253EVBE_H
+#define _M5253EVBE_H
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5253		/* define processor type */
+#define CONFIG_M5253EVBE	/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+#define CONFIG_BOOTDELAY	5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#else
+#define CFG_ENV_ADDR		0xffe04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+/* ATA */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT	1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	2
+
+#define CFG_ATA_BASE_ADDR	(CFG_MBAR2 + 0x800)
+#define CFG_ATA_IDE0_OFFSET	0
+
+#define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#define CFG_ATA_STRIDE		4	/* Interval between registers */
+#define _IO_BASE		0
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR		0x00100000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+
+#undef CFG_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+#	define CFG_PLLCR	0x1243E054
+#	define CFG_CLK		140000000
+#else
+#	define CFG_PLLCR	0x135a4140
+#	define CFG_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE	0x20000
+#else
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x40000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE		0xffe00000
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	1000
+
+#define CFG_FLASH_CFI		1
+#define CFG_FLASH_CFI_DRIVER	1
+#define CFG_FLASH_SIZE		0x200000
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE	16
+
+/* Port configuration */
+#define CFG_FECI2C		0xF0
+
+#define CFG_CSAR0		0xFFE0
+#define CFG_CSMR0		0x001F0021
+#define CFG_CSCR0		0x1D80
+
+#define CFG_CSAR1		0
+#define CFG_CSMR1		0
+#define CFG_CSCR1		0
+
+#define CFG_CSAR2		0
+#define CFG_CSMR2		0
+#define CFG_CSCR2		0
+
+#define CFG_CSAR3		0
+#define CFG_CSMR3		0
+#define CFG_CSCR3		0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CFG_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253EVB_H */
+
diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c
index 8919c0e..1635d6f 100644..100755
--- a/lib_m68k/interrupts.c
+++ b/lib_m68k/interrupts.c
@@ -106,8 +106,6 @@ void int_handler (struct pt_regs *fp)
 	vec = (fp->vector >> 2) & 0xff;
 	if (vec > 0x40)
 		vec -= 0x40;
-	else
-		return;
 
 	if (irq_vecs[vec].handler != NULL) {
 		irq_vecs[vec].handler (irq_vecs[vec].arg);