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| author | stefano babic <sbabic@denx.de> | 2007-11-20 10:37:04 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-02-03 23:46:06 +0100 |
| commit | 96bbfa1e6625ce23a150936863b3ecf4c853eb33 (patch) | |
| tree | b8a2a0d8ebe8b4bfee972bce587b44e5fd3c3934 | |
| parent | 98b742489c09780be6a832eeaa4e5eff824792bb (diff) | |
| download | u-boot-imx-96bbfa1e6625ce23a150936863b3ecf4c853eb33.zip u-boot-imx-96bbfa1e6625ce23a150936863b3ecf4c853eb33.tar.gz u-boot-imx-96bbfa1e6625ce23a150936863b3ecf4c853eb33.tar.bz2 | |
Fix gcc issues in pxa-regs.h
Fix gcc4 issue. With some toolchain, a previous patch that fixes gcc4
issues generates wrong code.
(Problem was reported with gcc-4.0.2-glibc-2.3.6/arm-softfloat-linux-gnu).
This patch fixes the problem and solves the gcc-4 issues as the linux
kernel does.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Dmitry Ivanov <ivadmitry@gmail.com>
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 9b4da3a..e014568 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \ - ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3) +#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) +#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) +#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) +#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) +#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) +#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) +#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) +#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ + ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |