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authorstroese <stroese>2005-05-03 06:12:20 +0000
committerstroese <stroese>2005-05-03 06:12:20 +0000
commit81b83c9ecc5dc9044d805221a44f2eec82b8d57d (patch)
tree693dfacbf7b61bf13c4ec54080d3f2685ca23883
parentdcb2f95a60c094d482574fa9fb01001b2e711a4e (diff)
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* Patch by Matthias Fuchs, 03 May 2005:
Added missing variable declaration in cmd_nand.c Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
-rw-r--r--common/cmd_nand.c2
-rw-r--r--include/configs/PLU405.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 6057dd1..dc268c8 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -1218,6 +1218,8 @@ static int nand_write_page (struct nand_chip *nand,
}
if (nand->bus16) {
for (i = 0; i < nand->oobsize; i += 2) {
+ u16 val;
+
val = READ_NAND (nand->IO_ADDR);
nand->data_buf[i] = val & 0xff;
nand->data_buf[i + 1] = val >> 8;
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 73a7885..7ee95df 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -212,7 +212,7 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */