Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx

5 files changed, 29 insertions, 15 deletions

diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds
index b34de8e..13c1acf 100644
--- a/board/mpc8641hpcn/u-boot.lds
+++ b/board/mpc8641hpcn/u-boot.lds
@@ -120,10 +120,12 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
+  . = .;
   __u_boot_cmd_start = .;
   .u_boot_cmd : { *(.u_boot_cmd) }
   __u_boot_cmd_end = .;
 
+  . = .;
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;
diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c
index 1df6cdc..49820bb 100644
--- a/cpu/mpc86xx/interrupts.c
+++ b/cpu/mpc86xx/interrupts.c
@@ -80,6 +80,26 @@ int interrupt_init(void)
 {
 	int ret;
 
+	/*
+	 * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
+	 * implement PEX10 errata.  As INT is active high, it
+	 * will cause core to take 0x500 interrupt.
+	 *
+	 * Due to the PIC's default pass through mode, as soon
+	 * as interrupts are enabled (MSR[EE] = 1), an interrupt
+	 * will be taken and u-boot will hang.  This is due to a
+	 * hardware change (per an errata fix) on new revisions
+	 * of the board with Rev 2.x parts.
+	 *
+	 * Setting the PIC to mixed mode prevents the hang.
+	 */
+	if ((get_svr() & 0xf0) == 0x20) {
+		volatile immap_t *immr = (immap_t *)CFG_IMMR;
+		immr->im_pic.gcr = MPC86xx_PICGCR_RST;
+		while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
+		immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
+	}
+
 	/* call cpu specific function from $(CPU)/interrupts.c */
 	ret = interrupt_init_cpu(&decrementer_count);
 
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index b18e822..ac9ff81 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -284,9 +284,9 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 	}
 
 	/*
-	 * Adjust DDR II IO voltage biasing.  It just makes it work.
+	 * Adjust DDR II IO voltage biasing.  Rev1 only
 	 */
-	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+	if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) {
 		gur->ddrioovcr = (0
 				  | 0x80000000		/* Enable */
 				  | 0x10000000		/* VSEL to 1.8V */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index a5552c4..0e3fc34 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -721,6 +721,8 @@ typedef struct ccsr_pic {
 	uint	frr;		/* 0x41000 - Feature Reporting Register */
 	char	res10[28];
 	uint	gcr;		/* 0x41020 - Global Configuration Register */
+#define MPC86xx_PICGCR_RST	0x80000000
+#define MPC86xx_PICGCR_MODE	0x20000000
 	char	res11[92];
 	uint	vir;		/* 0x41080 - Vendor Identification Register */
 	char	res12[12];
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 246ac7f..bbe3505 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -212,7 +212,6 @@
 #endif
 
 #if defined(CFG_RAMBOOT)
-#undef CFG_FLASH_CFI_DRIVER
 #undef CONFIG_SPD_EEPROM
 #define CFG_SDRAM_SIZE	256
 #endif
@@ -468,7 +467,6 @@
     #define CFG_ENV_SECT_SIZE		0x40000	/* 256K(one sector) for env */
     #define CFG_ENV_SIZE		0x2000
 #else
-    #define CFG_NO_FLASH		1	/* Flash is not usable now */
     #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
     #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
     #define CFG_ENV_SIZE		0x2000
@@ -486,21 +484,13 @@
 				 | CFG_CMD_SCSI		\
 				 | CFG_CMD_EXT2)	\
 				&			\
-				 ~(CFG_CMD_ENV		\
-				  | CFG_CMD_IMLS	\
-				  | CFG_CMD_FLASH	\
-				  | CFG_CMD_LOADS))
+				 ~(CFG_CMD_ENV))
   #else
     #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
 				 | CFG_CMD_PING		\
-				 | CFG_CMD_I2C		\
-				 | CFG_CMD_SCSI		\
-				 | CGF_CMD_EXT2)	\
+				 | CFG_CMD_I2C)		\
 				&			\
-				 ~(CFG_CMD_ENV		\
-				 | CFG_CMD_IMLS		\
-				 | CFG_CMD_FLASH	\
-				 | CFG_CMD_LOADS))
+				 ~(CFG_CMD_ENV))
   #endif
 #else
   #if defined(CONFIG_PCI)