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| author | Jason Liu <r64343@freescale.com> | 2010-05-26 18:59:24 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2010-05-26 20:31:54 +0800 |
| commit | 161ebc6c0813e3d9adc267c8c58c5f727dc3e44c (patch) | |
| tree | 01bfe437c10a1450aa41c3eab5b1634344696481 | |
| parent | cfc0fd331a95611780d7fe035bde51193de92681 (diff) | |
| download | u-boot-imx-161ebc6c0813e3d9adc267c8c58c5f727dc3e44c.zip u-boot-imx-161ebc6c0813e3d9adc267c8c58c5f727dc3e44c.tar.gz u-boot-imx-161ebc6c0813e3d9adc267c8c58c5f727dc3e44c.tar.bz2 | |
ENGR00123870 MX53: Set AXI_B clock to 200Mhz
The clock for axi_b is set to 100Mhz which will cause IPU module has
insufficient clock rate. This patch will increase axi_b clock to 200M
and keep it not change when do clk config in uboot
Signed-off-by:Jason Liu <r64343@freescale.com>
| -rw-r--r-- | cpu/arm_cortexa8/mx53/generic.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c index 791c0c3..cba38ec 100644 --- a/cpu/arm_cortexa8/mx53/generic.c +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -789,14 +789,13 @@ int config_core_clk(u32 ref, u32 freq) int config_periph_clk(u32 ref, u32 freq) { int ret = 0; - u32 pll = 0; + u32 pll = freq; struct pll_param pll_param; memset(&pll_param, 0, sizeof(struct pll_param)); if (__REG(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { /* Actually this case is not considered here */ - pll = freq; ret = calc_pll_params(ref, pll, &pll_param); if (ret != 0) { printf("Can't find pll parameters: %d\n", @@ -816,9 +815,8 @@ int config_periph_clk(u32 ref, u32 freq) return -1; } } else { - u32 pll3_freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ); u32 old_cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); - u32 cbcdr = 0; + u32 new_cbcdr = calc_per_cbcdr_val(pll, old_cbcmr); /* Switch peripheral to PLL3 */ writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR); @@ -829,7 +827,6 @@ int config_periph_clk(u32 ref, u32 freq) ; /* Setup PLL2 */ - pll = freq; ret = calc_pll_params(ref, pll, &pll_param); if (ret != 0) { printf("Can't find pll parameters: %d\n", @@ -839,8 +836,7 @@ int config_periph_clk(u32 ref, u32 freq) config_pll_clk(PLL2_CLK, &pll_param); /* Switch peripheral back */ - cbcdr = calc_per_cbcdr_val(pll, old_cbcmr); - writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); + writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR); /* Make sure change is effective */ |