diff options
| author | Stefan Roese <sr@denx.de> | 2008-01-14 10:05:05 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-14 10:05:05 +0100 |
| commit | a0dd99d51efa55fe023e19c97ead92683725eb11 (patch) | |
| tree | 96f1cc10ecf76fbcd48e90a9693974c320abc7ae | |
| parent | f43ad53908f1ea83a7c26c3505bbe84382e47aad (diff) | |
| download | u-boot-imx-a0dd99d51efa55fe023e19c97ead92683725eb11.zip u-boot-imx-a0dd99d51efa55fe023e19c97ead92683725eb11.tar.gz u-boot-imx-a0dd99d51efa55fe023e19c97ead92683725eb11.tar.bz2 | |
ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit
Now that bit 29 is the USB PHY reset bit, update the Kilauea port
to remove the USB PHY reset after powerup. The CPLD will keep the
USB PHY in reset (active low) until the bit is set to 1 in
board_early_init_f().
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/amcc/kilauea/kilauea.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 2ee896a..37ef06e 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -192,13 +192,6 @@ int board_early_init_f (void) */ mtsdr(SDR0_SRST, 0); - /* - * Configure FPGA register with PCIe reset - */ - out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */ - mdelay(50); - out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */ - /* Configure 405EX for NAND usage */ val = SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | @@ -214,6 +207,13 @@ int board_early_init_f (void) val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; mtsdr(SDR0_PFC1, val); + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ + return 0; } |