diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-09-24 11:42:12 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:00 +0200 |
| commit | 41410eee472b0f42e03a77f961bbc55ef58f3c01 (patch) | |
| tree | 696428e03aefc4030f0623d278f2d21b59f36f16 | |
| parent | 69710092172409cfcc43b84cd71287f428a4e319 (diff) | |
| download | u-boot-imx-41410eee472b0f42e03a77f961bbc55ef58f3c01.zip u-boot-imx-41410eee472b0f42e03a77f961bbc55ef58f3c01.tar.gz u-boot-imx-41410eee472b0f42e03a77f961bbc55ef58f3c01.tar.bz2 | |
Change UEC PHY interface to RGMII on MPC8568MDS
Change UEC phy interface from GMII to RGMII on MPC8568MDS board
Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable.
Now both UEC1 and UEC2 can work properly under u-boot.
It is also in consistent with the kernel setting for 8568 UEC phy interface.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| -rw-r--r-- | drivers/qe/uec.c | 1 | ||||
| -rw-r--r-- | drivers/qe/uec.h | 1 | ||||
| -rw-r--r-- | drivers/qe/uec_phy.c | 24 | ||||
| -rw-r--r-- | drivers/qe/uec_phy.h | 8 | ||||
| -rw-r--r-- | include/configs/MPC8568MDS.h | 4 |
5 files changed, 36 insertions, 2 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 344c649..85e2ad3 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -424,6 +424,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) upsmr |= (UPSMR_RPM | UPSMR_TBIM); break; case ENET_1000_RGMII_RXID: + case ENET_1000_RGMII_ID: case ENET_1000_RGMII: maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; upsmr |= UPSMR_RPM; diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index e357a92..0b64499 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -642,6 +642,7 @@ typedef enum enet_interface { ENET_100_RGMII, ENET_1000_GMII, ENET_1000_RGMII, + ENET_1000_RGMII_ID, ENET_1000_RGMII_RXID, ENET_1000_TBI, ENET_1000_RTBI diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 186922e..2243d3b 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -376,6 +376,29 @@ static int bcm_init(struct uec_mii_info *mii_info) return 0; } +static int marvell_init(struct uec_mii_info *mii_info) +{ + struct eth_device *edev = mii_info->dev; + uec_private_t *uec = edev->priv; + + if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) { + int temp; + + temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); + temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); + phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); + + temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR); + temp &= ~MII_M1111_HWCFG_MODE_MASK; + temp |= MII_M1111_HWCFG_MODE_RGMII; + phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); + + phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); + } + + return 0; +} + static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -538,6 +561,7 @@ static struct phy_info phy_info_marvell = { .phy_id_mask = 0xffffff00, .name = "Marvell 88E11x1", .features = MII_GBIT_FEATURES, + .init = &marvell_init, .config_aneg = &marvell_config_aneg, .read_status = &marvell_read_status, .ack_interrupt = &marvell_ack_interrupt, diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 6f769fb..7ac1ff9 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -77,6 +77,14 @@ #define MII_M1011_IMASK_INIT 0x6400 #define MII_M1011_IMASK_CLEAR 0x0000 +/* 88E1111 PHY Register */ +#define MII_M1111_PHY_EXT_CR 0x14 +#define MII_M1111_RX_DELAY 0x80 +#define MII_M1111_TX_DELAY 0x2 +#define MII_M1111_PHY_EXT_SR 0x1b +#define MII_M1111_HWCFG_MODE_MASK 0xf +#define MII_M1111_HWCFG_MODE_RGMII 0xb + #define MII_DM9161_SCR 0x10 #define MII_DM9161_SCR_INIT 0x0610 #define MII_DM9161_SCR_RMII_INIT 0x0710 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 80697a5..076137a 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -362,7 +362,7 @@ extern unsigned long get_clock_freq(void); #define CFG_UEC1_TX_CLK QE_CLK16 #define CFG_UEC1_ETH_TYPE GIGA_ETH #define CFG_UEC1_PHY_ADDR 7 -#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -373,7 +373,7 @@ extern unsigned long get_clock_freq(void); #define CFG_UEC2_TX_CLK QE_CLK16 #define CFG_UEC2_ETH_TYPE GIGA_ETH #define CFG_UEC2_PHY_ADDR 1 -#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #endif #endif /* CONFIG_QE */ |