* Patches by Robert Whaley, 29 Nov 2004:

  - update the pxa-regs.h file for PXA27x chips
  - add PXA27x based ADSVIX board
  - add support for MMC on PXA27x processors

* Patch by Andrew E. Mileski, 28 Nov 2004:
  Fix PPC4xx SPD SDRAM detection bug

* Patch by Hiroshi Ito, 26 Nov 2004:
  Fix logic of "test -z" and "test -n" commands

16 files changed, 1946 insertions, 270 deletions

diff --git a/CHANGELOG b/CHANGELOG
index b5d72f3..1fc3698 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,17 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patches by Robert Whaley, 29 Nov 2004:
+  - update the pxa-regs.h file for PXA27x chips
+  - add PXA27x based ADSVIX board
+  - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+  Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+  Fix logic of "test -z" and "test -n" commands
+
 * Patch by Ladislav Michl, 05 Apr 2005:
   Add support for VoiceBlue board.
 
diff --git a/CREDITS b/CREDITS
index 252a4b2..cec74a9 100644
--- a/CREDITS
+++ b/CREDITS
@@ -402,6 +402,10 @@ N: Christian Vejlbo
 E: christian.vejlbo@tellabs.com
 D: FADS860T ethernet support
 
+N: Robert Whaley
+E: rwhaley@applieddata.net
+D: Port to ARM PXA27x adsvix SBC
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
diff --git a/MAKEALL b/MAKEALL
index 426c6a6..69d7760 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -170,9 +170,9 @@ LIST_ARM11="omap2420h4"
 #########################################################################
 
 LIST_pxa="	\
-	cerf250		cradle		csb226		innokom		\
-	lubbock		wepep250	xaeniax		xm250		\
-	xsengine							\
+	adsvix		cerf250		cradle		csb226		\
+	innokom		lubbock		wepep250	xaeniax		\
+	xm250		xsengine							\
 "
 
 LIST_ixp="ixdp425"
diff --git a/Makefile b/Makefile
index f93c86b..63a2c31 100644
--- a/Makefile
+++ b/Makefile
@@ -1432,6 +1432,9 @@ cmc_pu2_config	:	unconfig
 ## XScale Systems
 #########################################################################
 
+adsvix_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa adsvix
+
 cerf250_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa cerf250
 
diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile
new file mode 100644
index 0000000..ae514aa
--- /dev/null
+++ b/board/adsvix/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= adsvix.o pcmcia.o
+SOBJS	:= memsetup.o pxavoltage.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c
new file mode 100644
index 0000000..5e770e9
--- /dev/null
+++ b/board/adsvix/adsvix.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of ADSVIX-Board */
+	gd->bd->bi_arch_number = 620;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
diff --git a/board/adsvix/config.mk b/board/adsvix/config.mk
new file mode 100644
index 0000000..98be4eb
--- /dev/null
+++ b/board/adsvix/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1700000
diff --git a/board/adsvix/memsetup.S b/board/adsvix/memsetup.S
new file mode 100644
index 0000000..7b6abd6
--- /dev/null
+++ b/board/adsvix/memsetup.S
@@ -0,0 +1,468 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc	p15,0,\reg,c2,c0,0
+   mov	\reg,\reg
+   sub	pc,pc,#4
+   .endm
+
+
+/*
+ *	Memory setup
+ */
+
+.globl memsetup
+memsetup:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR3
+	ldr		r1,	=CFG_GPSR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR3
+	ldr		r1,	=CFG_GPCR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR3
+	ldr		r1,	=CFG_GPDR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_L
+	ldr		r1,	=CFG_GAFR3_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_U
+	ldr		r1,	=CFG_GAFR3_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller	    */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type			    */
+
+	/* MSC0: nCS(0,1)						    */
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
+						/* that data latches	    */
+	/* MSC1: nCS(2,3)						    */
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)						    */
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface				    */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register				    */
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing				    */
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing				    */
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
+	/* ---------------------------------------------------------------- */
+	ldr	r2,  =CFG_FLYCNFG_VAL
+	str	r2,  [r1, #FLYCNFG_OFFSET]
+	str	r2,	[r1, #FLYCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
+	/* this to power on defaults + DRI field.			    */
+
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+	ldr	r2,	=0xFFF
+	bic	r4,	r4, r2
+
+	ldr	r3,	=CFG_MDREFR_VAL
+	and	r3,	r3,  r2
+
+	orr	r4,	r4, r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+
+	orr	r4,  r4, #MDREFR_K0RUN
+	orr	r4,  r4, #MDREFR_K0DB4
+	orr	r4,  r4, #MDREFR_K0FREE
+	orr	r4,  r4, #MDREFR_K0DB2
+	orr	r4,  r4, #MDREFR_K1DB2
+	bic	r4,  r4, #MDREFR_K1FREE
+	bic	r4,  r4, #MDREFR_K2FREE
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4			    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits		    */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.						    */
+
+	ldr	r2,  =CFG_SXCNFG_VAL
+	str	r2,  [r1, #SXCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM					    */
+	/* ---------------------------------------------------------------- */
+
+	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*	    configure but not enable each SDRAM partition pair.	    */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
+	/*	    100..200 µsec.					    */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
+	/*	    attempting non-burst read or write accesses to disabled */
+	/*	    SDRAM, as commonly specified in the power up sequence   */
+	/*	    documented in SDRAM data sheets. The address(es) used   */
+	/*	    for this purpose must not be cacheable.		    */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted		    */
+	/*	    (MDCNFG:DEx set to 1).				    */
+
+	ldr	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3,	r3,	#MDCNFG_DE0
+	str	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS.					    */
+
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3,  [r1, #MDREFR_OFFSET]
+	orr	r3,  r3,  #MDREFR_APD
+	str	r3,  [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+setvoltage:
+
+	mov	r10,	lr
+	bl	initPXAvoltage	/* In case the board is rebooting with a    */
+	mov	lr,	r10	/* low voltage raise it up to a good one.   */
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0,	=RCSR
+	ldr	r1,	[r0]
+	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1,	[r0]
+	teq	r1,	#RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0,	=PSSR
+	mov	r1,	#PSSR_PH
+	str	r1,	[r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0,	=PSPR
+	ldr	r1,	[r0]
+	mov	pc,	r1
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller	    */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
+	str	r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation						    */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off on-chip peripheral clocks (except for memory)	    */
+	/* for re-configuration.					    */
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN
+	str	r2,  [r1]
+
+	/* ... and write the core clock config register			    */
+	ldr	r2,  =CFG_CCCR
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MEMC_BASE
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager		    */
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
+	/* has settled.							    */
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#else
+#error "RTC not defined"
+#endif
+
+	/* Interrupt init: Mask all interrupts				    */
+    ldr r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+	/* FIXME */
+
+// #define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End memsetup							    */
+	/* ---------------------------------------------------------------- */
+
+endmemsetup:
+
+	mov	pc, lr
diff --git a/board/adsvix/pcmcia.c b/board/adsvix/pcmcia.c
new file mode 100644
index 0000000..ba5be01
--- /dev/null
+++ b/board/adsvix/pcmcia.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void pcmcia_power_on(void)
+{
+#if 0
+	if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
+		GPCR(81) = GPIO_bit(81);
+		GPSR(82) = GPIO_bit(82);
+	}
+	else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
+		GPCR(81) = GPIO_bit(81);
+		GPCR(82) = GPIO_bit(82);
+	}
+#else
+#warning "Board will only supply 5V, wait for next HW spin for selectable power"
+	/* 5.0V */
+	GPCR(81) = GPIO_bit(81);
+	GPCR(82) = GPIO_bit(82);
+#endif
+
+	udelay(300000);
+
+	/* reset the card */
+	GPSR(52) = GPIO_bit(52);
+
+	/* enable PCMCIA */
+	GPCR(83) = GPIO_bit(83);
+
+	/* clear reset */
+	udelay(10);
+	GPCR(52) = GPIO_bit(52);
+
+	udelay(20000);
+}
+
+void pcmcia_power_off(void)
+{
+	/* 0V */
+	GPSR(81) = GPIO_bit(81);
+	GPSR(82) = GPIO_bit(82);
+	/* disable PCMCIA */
+	GPSR(83) = GPIO_bit(83);
+}
diff --git a/board/adsvix/pxavoltage.S b/board/adsvix/pxavoltage.S
new file mode 100644
index 0000000..5a0359c
--- /dev/null
+++ b/board/adsvix/pxavoltage.S
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+#define LTC1663_ADDR    0x20
+
+#define LTC1663_SY	0x01	/* Sync ACK */
+#define LTC1663_SD	0x04	/* shutdown */
+#define LTC1663_BG	0x04	/* Internal Voltage Ref */
+
+#define VOLT_1_55         18    /* DAC value for 1.55V */
+
+		.global	initPXAvoltage
+
+@ Set the voltage to 1.55V early in the boot process so we can run
+@ at a high clock speed and boot quickly.  Note that this is necessary
+@ because the reset button does not reset the CPU voltage, so if the
+@ voltage was low (say 0.85V) then the CPU would crash without this
+@ routine
+
+@ This routine clobbers r0-r4
+
+initializei2c:
+
+		ldr	r2, =CKEN
+		ldr	r3, [r2]
+		orr	r3, r3, #CKEN15_PWRI2C
+		str	r3, [r2]
+
+		ldr	r2, =PCFR
+		ldr	r3, [r2]
+		orr	r3, r3, #PCFR_PI2C_EN
+		str	r3, [r2]
+
+		/* delay for about 250msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0000
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		ldr	r0, =PWRICR
+		ldr	r1, [r0]
+		bic	r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		ldr	r2, =PWRISR
+		ldr	r3, =0x7ff
+		str	r3, [r2]
+
+		bic	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		mov	r1, #(ICR_GCD | ICR_SCLE)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_IUE
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_FM
+		str	r1, [r0]
+
+		/* delay for about 1msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC00
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, lr
+
+sendbytei2c:
+		ldr	r3, =PWRIDBR
+		str	r0, [r3]
+		ldr	r3, =PWRICR
+		ldr	r0, [r3]
+		orr	r0, r0, r1
+		bic	r0, r0, r2
+		str	r0, [r3]
+		orr	r0, r0, #ICR_TB
+		str	r0, [r3]
+
+		mov	r2, #0x100000
+
+waitfortxemptyi2c:
+
+		ldr	r0, =PWRISR
+		ldr	r1, [r0]
+
+		/* take it from the top if we don't get empty after a while */
+		subs	r2, r2, #1
+		moveq	lr, r4
+		beq	initPXAvoltage
+
+		tst	r1, #ISR_ITE
+
+		beq	waitfortxemptyi2c
+
+		orr	r1, r1, #ISR_ITE
+		str	r1, [r0]
+
+		mov	pc, lr
+
+initPXAvoltage:
+
+		mov	r4, lr
+
+		bl	setleds
+
+		bl	initializei2c
+
+		bl	setleds
+
+		/* now send the real message to set the correct voltage */
+		ldr	r0, =LTC1663_ADDR
+		mov	r0, r0, LSL #1
+		mov	r1, #ICR_START
+		ldr	r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		mov	r0, #LTC1663_BG
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		and	r0, r0, #0xff
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		mov	r0, r0, ASR #8
+		and	r0, r0, #0xff
+		mov	r1, #ICR_STOP
+		mov	r2, #ICR_START
+		bl	sendbytei2c
+
+		bl	setleds
+
+		@ delay a little for the volatage to stablize
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, r4
+
+setleds:
+	mov		pc, lr
+
+	ldr		r5, =0x40e00058
+	ldr		r3, [r5]
+	bic		r3, r3, #0x3
+	str		r3, [r5]
+	ldr		r5, =0x40e0000c
+	ldr		r3, [r5]
+	orr		r3, r3, #0x00010000
+	str		r3, [r5]
+
+	@ inner loop
+	mov		r0, #0x2
+1:
+
+	ldr		r5, =0x40e00018
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+2:
+	subs		r3, r3, #1
+	bne		2b
+
+	ldr		r5, =0x40e00024
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+3:
+	subs		r3, r3, #1
+	bne		3b
+
+	subs		r0, r0, #1
+	bne		1b
+
+	mov		pc, lr
+
diff --git a/board/adsvix/u-boot.lds b/board/adsvix/u-boot.lds
new file mode 100644
index 0000000..58c371d
--- /dev/null
+++ b/board/adsvix/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/common/command.c b/common/command.c
index 64e56af..2b4c554 100644
--- a/common/command.c
+++ b/common/command.c
@@ -136,9 +136,9 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		if (adv == 2) {
 			if (strcmp(ap[0], "-z") == 0)
-				expr = strlen(ap[1]) == 0 ? 0 : 1;
-			else if (strcmp(ap[0], "-n") == 0)
 				expr = strlen(ap[1]) == 0 ? 1 : 0;
+			else if (strcmp(ap[0], "-n") == 0)
+				expr = strlen(ap[1]) == 0 ? 0 : 1;
 			else {
 				expr = 1;
 				break;
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 44e826f..794a72c 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1082,7 +1082,7 @@ void program_rtr (unsigned long* dimm_populated,
 	    case 0x00:
 		refresh_rate = 15625;
 		break;
-	    case 0x011:
+	    case 0x01:
 		refresh_rate = 15625/4;
 		break;
 	    case 0x02:
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index 4495962..f7020ee 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -72,13 +72,11 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 
 	status = MMC_STAT;
 	debug("MMC status %x\n", status);
-	if (status & MMC_STAT_TIME_OUT_RESPONSE)
-	{
+	if (status & MMC_STAT_TIME_OUT_RESPONSE) {
 		return 0;
 	}
 
-	switch (cmdat & 0x3)
-	{
+	switch (cmdat & 0x3) {
 		case MMC_CMDAT_R1:
 		case MMC_CMDAT_R3:
 			words = 3;
@@ -91,8 +89,7 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 		default:
 			return 0;
 	}
-	for (i = words-1; i >= 0; i--)
-	{
+	for (i = words-1; i >= 0; i--) {
 		ulong res_fifo = MMC_RES;
 		int offset = i << 1;
 
@@ -100,8 +97,7 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 		resp[offset+1] = ((uchar *)&res_fifo)[1];
 	}
 #ifdef MMC_DEBUG
-	for (i=0; i<words*2; i += 2)
-	{
+	for (i=0; i<words*2; i += 2) {
 		printf("MMC resp[%d] = %02x\n", i, resp[i]);
 		printf("MMC resp[%d] = %02x\n", i+1, resp[i+1]);
 	}
@@ -118,8 +114,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
 	ushort argh, argl;
 	ulong status;
 
-	if (len == 0)
-	{
+	if (len == 0) {
 		return 0;
 	}
 
@@ -143,16 +138,21 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
 
 
 	MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
-	while (len)
-	{
-		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ)
-		{
+	while (len) {
+		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
+#ifdef CONFIG_PXA27X
+			int i;
+			for (i=min(len,32); i; i--) {
+				*dst++ = * ((volatile uchar *) &MMC_RXFIFO);
+				len--;
+			}
+#else
 			*dst++ = MMC_RXFIFO;
 			len--;
+#endif
 		}
 		status = MMC_STAT;
-		if (status & MMC_STAT_ERRORS)
-		{
+		if (status & MMC_STAT_ERRORS) {
 			printf("MMC_STAT error %lx\n", status);
 			return -1;
 		}
@@ -160,8 +160,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
 	MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
 	while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
 	status = MMC_STAT;
-	if (status & MMC_STAT_ERRORS)
-	{
+	if (status & MMC_STAT_ERRORS) {
 		printf("MMC_STAT error %lx\n", status);
 		return -1;
 	}
@@ -177,8 +176,7 @@ mmc_block_write(ulong dst, uchar *src, int len)
 	ushort argh, argl;
 	ulong status;
 
-	if (len == 0)
-	{
+	if (len == 0) {
 		return 0;
 	}
 
@@ -200,25 +198,20 @@ mmc_block_write(ulong dst, uchar *src, int len)
 			MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
 
 	MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
-	while (len)
-	{
-		if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ)
-		{
+	while (len) {
+		if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
 			int i, bytes = min(32,len);
 
-			for (i=0; i<bytes; i++)
-			{
+			for (i=0; i<bytes; i++) {
 				MMC_TXFIFO = *src++;
 			}
-			if (bytes < 32)
-			{
+			if (bytes < 32) {
 				MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
 			}
 			len -= bytes;
 		}
 		status = MMC_STAT;
-		if (status & MMC_STAT_ERRORS)
-		{
+		if (status & MMC_STAT_ERRORS) {
 			printf("MMC_STAT error %lx\n", status);
 			return -1;
 		}
@@ -228,8 +221,7 @@ mmc_block_write(ulong dst, uchar *src, int len)
 	MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
 	while (!(MMC_I_REG & MMC_I_REG_PRG_DONE));
 	status = MMC_STAT;
-	if (status & MMC_STAT_ERRORS)
-	{
+	if (status & MMC_STAT_ERRORS) {
 		printf("MMC_STAT error %lx\n", status);
 		return -1;
 	}
@@ -245,13 +237,11 @@ mmc_read(ulong src, uchar *dst, int size)
 	ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
 	ulong mmc_block_size, mmc_block_address;
 
-	if (size == 0)
-	{
+	if (size == 0) {
 		return 0;
 	}
 
-	if (!mmc_ready)
-	{
+	if (!mmc_ready) {
 		printf("Please initial the MMC first\n");
 		return -1;
 	}
@@ -269,13 +259,11 @@ mmc_read(ulong src, uchar *dst, int size)
 	/* all block aligned accesses */
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_start)
-	{
+	if (part_start) {
 		part_len = mmc_block_size - part_start;
 		debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(dst, mmc_buf+part_start, part_len);
@@ -284,23 +272,19 @@ mmc_read(ulong src, uchar *dst, int size)
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size)
-	{
+	for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
 		debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
 			return -1;
 		}
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_end && src < end)
-	{
+	if (part_end && src < end) {
 		debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(dst, mmc_buf, part_end);
@@ -316,13 +300,11 @@ mmc_write(uchar *src, ulong dst, int size)
 	ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
 	ulong mmc_block_size, mmc_block_address;
 
-	if (size == 0)
-	{
+	if (size == 0) {
 		return 0;
 	}
 
-	if (!mmc_ready)
-	{
+	if (!mmc_ready) {
 		printf("Please initial the MMC first\n");
 		return -1;
 	}
@@ -340,18 +322,15 @@ mmc_write(uchar *src, ulong dst, int size)
 	/* all block aligned accesses */
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_start)
-	{
+	if (part_start) {
 		part_len = mmc_block_size - part_start;
 		debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		(ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(mmc_buf+part_start, src, part_len);
-		if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
 			return -1;
 		}
 		dst += part_len;
@@ -359,28 +338,23 @@ mmc_write(uchar *src, ulong dst, int size)
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size)
-	{
+	for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
 		debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
 			return -1;
 		}
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_end && dst < end)
-	{
+	if (part_end && dst < end) {
 		debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(mmc_buf, src, part_end);
-		if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
 			return -1;
 		}
 	}
@@ -412,6 +386,11 @@ mmc_init(int verbose)
 	set_GPIO_mode( GPIO8_MMCCS0_MD );
 #endif
 	CKEN |= CKEN12_MMC; /* enable MMC unit clock */
+#if defined(CONFIG_ADSVIX)
+	/* turn on the power */
+	GPCR(114) = GPIO_bit(114);
+	udelay(1000);
+#endif
 
 	mmc_csd.c_size = 0;
 
@@ -423,21 +402,22 @@ mmc_init(int verbose)
 	retries = 10;
 	resp = mmc_cmd(0, 0, 0, 0);
 	resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
-	while (retries-- && resp && !(resp[4] & 0x80))
-	{
+	while (retries-- && resp && !(resp[4] & 0x80)) {
 		debug("resp %x %x\n", resp[0], resp[1]);
+#ifdef CONFIG_PXA27X
+		udelay(10000);
+#else
 		udelay(50);
+#endif
 		resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
 	}
 
 	/* try to get card id */
 	resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2);
-	if (resp)
-	{
+	if (resp) {
 		/* TODO configure mmc driver depending on card attributes */
 		mmc_cid_t *cid = (mmc_cid_t *)resp;
-		if (verbose)
-		{
+		if (verbose) {
 			printf("MMC found. Card desciption is:\n");
 			printf("Manufacturer ID = %02x%02x%02x\n",
 							cid->id[0], cid->id[1], cid->id[2]);
@@ -451,6 +431,7 @@ mmc_init(int verbose)
 		}
 		/* fill in device description */
 		mmc_dev.if_type = IF_TYPE_MMC;
+		mmc_dev.part_type = PART_TYPE_DOS;
 		mmc_dev.dev = 0;
 		mmc_dev.lun = 0;
 		mmc_dev.type = 0;
@@ -468,8 +449,7 @@ mmc_init(int verbose)
 		/* MMC exists, get CSD too */
 		resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
 		resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2);
-		if (resp)
-		{
+		if (resp) {
 			mmc_csd_t *csd = (mmc_csd_t *)resp;
 			memcpy(&mmc_csd, csd, sizeof(csd));
 			rc = 0;
@@ -478,7 +458,11 @@ mmc_init(int verbose)
 		}
 	}
 
+#ifdef CONFIG_PXA27X
+	MMC_CLKRT = 1;	/* 10 MHz - see Intel errata */
+#else
 	MMC_CLKRT = 0;	/* 20 MHz */
+#endif
 	resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
 
 	fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
@@ -496,11 +480,10 @@ int
 mmc2info(ulong addr)
 {
 	/* FIXME hard codes to 32 MB device */
-	if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000)
-	{
+	if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
 		return 1;
 	}
 	return 0;
 }
 
-#endif
+#endif	/* CONFIG_MMC */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a59838c..41d37d7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -22,18 +22,17 @@
 /* FIXME hack so that SA-1111.h will work [cb] */
 
 #ifndef __ASSEMBLY__
-typedef unsigned short  Word16 ;
-typedef unsigned int    Word32 ;
-typedef Word32          Word ;
-typedef Word            Quad [4] ;
-typedef void            *Address ;
-typedef void            (*ExcpHndlr) (void) ;
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
 #endif
 
 /*
  * PXA Chip selects
  */
-
 #define PXA_CS0_PHYS	0x00000000
 #define PXA_CS1_PHYS	0x04000000
 #define PXA_CS2_PHYS	0x08000000
@@ -41,50 +40,46 @@ typedef void            (*ExcpHndlr) (void) ;
 #define PXA_CS4_PHYS	0x10000000
 #define PXA_CS5_PHYS	0x14000000
 
-
 /*
  * Personal Computer Memory Card International Association (PCMCIA) sockets
  */
-
 #define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
-#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
-#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
+#define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
 #define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
-#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
 
-#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
-#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
 #define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
-#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */
 
-#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
-#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
 #define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
-#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */
 
-#define _PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
 			(0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]               */
-#define _PCMCIAAttr(Nb)	        	/* PCMCIA Attribute [0..1]         */ \
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
 			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb)	        	/* PCMCIA Memory [0..1]            */ \
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
 			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
 
-#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0                        */
-#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O                    */
-#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute              */
-#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory                 */
-
-#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1                        */
-#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O                    */
-#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute              */
-#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory                 */
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
 
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
 
 /*
  * DMA Controller
  */
-
 #define DCSR0		__REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
 #define DCSR1		__REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
 #define DCSR2		__REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
@@ -107,6 +102,17 @@ typedef void            (*ExcpHndlr) (void) ;
 #define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
 #define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
 #define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+
+#if defined(CONFIG_PXA27X)
+#define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */
+#define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */
+#endif
+
 #define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
 #define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
 #define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
@@ -156,6 +162,10 @@ typedef void            (*ExcpHndlr) (void) ;
 #define DRCMR38		__REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
 #define DRCMR39		__REG(0x4000019C)  /* Reserved */
 
+#define DRCMR68		       __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69		       __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70		       __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
+
 #define DRCMRRXSADR	DRCMR2
 #define DRCMRTXSADR	DRCMR3
 #define DRCMRRXBTRBR	DRCMR4
@@ -252,11 +262,11 @@ typedef void            (*ExcpHndlr) (void) ;
 #define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
 #define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
 
-#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */
 #define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
 #define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
-#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
+#define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */
 #define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
 #define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
 #define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
@@ -272,11 +282,9 @@ typedef void            (*ExcpHndlr) (void) ;
 #define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
 #define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
 
-
 /*
  * UARTs
  */
-
 /* Full Function UART (FFUART) */
 #define FFUART		FFRBR
 #define FFRBR		__REG(0x40100000)  /* Receive Buffer Register (read only) */
@@ -417,19 +425,24 @@ typedef void            (*ExcpHndlr) (void) ;
 /*
  * I2C registers
  */
-
 #define IBMR		__REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
 #define IDBR		__REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
 #define ICR		__REG(0x40301690)  /* I2C Control Register - ICR */
 #define ISR		__REG(0x40301698)  /* I2C Status Register - ISR */
 #define ISAR		__REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
 
+#define PWRIBMR		__REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR		__REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR		__REG(0x40f00190)  /* Power I2C Control Register - ICR */
+#define PWRISR		__REG(0x40f00198)  /* Power I2C Status Register - ISR */
+#define PWRISAR		__REG(0x40f001A0)  /* Power I2C Slave Address Register-ISAR */
+
 /* ----- Control register bits ---------------------------------------- */
 
 #define ICR_START	0x1		/* start bit */
 #define ICR_STOP	0x2		/* stop bit */
 #define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
-#define ICR_TB		0x8 		/* transfer byte bit */
+#define ICR_TB		0x8		/* transfer byte bit */
 #define ICR_MA		0x10		/* master abort */
 #define ICR_SCLE	0x20		/* master clock enable */
 #define ICR_IUE		0x40		/* unit enable */
@@ -438,33 +451,31 @@ typedef void            (*ExcpHndlr) (void) ;
 #define ICR_IRFIE	0x200		/* enable rx interrupts */
 #define ICR_BEIE	0x400		/* enable bus error ints */
 #define ICR_SSDIE	0x800		/* slave STOP detected int enable */
-#define ICR_ALDIE	0x1000  	/* enable arbitration interrupt */
+#define ICR_ALDIE	0x1000		/* enable arbitration interrupt */
 #define ICR_SADIE	0x2000		/* slave address detected int enable */
 #define ICR_UR		0x4000		/* unit reset */
 #define ICR_FM		0x8000		/* Fast Mode */
 
 /* ----- Status register bits ----------------------------------------- */
 
-#define ISR_RWM         0x1		/* read/write mode */
-#define ISR_ACKNAK      0x2		/* ack/nak status */
-#define ISR_UB          0x4		/* unit busy */
-#define ISR_IBB         0x8		/* bus busy */
-#define ISR_SSD         0x10		/* slave stop detected */
-#define ISR_ALD         0x20		/* arbitration loss detected */
-#define ISR_ITE         0x40            /* tx buffer empty */
-#define ISR_IRF         0x80            /* rx buffer full */
-#define ISR_GCAD        0x100		/* general call address detected */
-#define ISR_SAD         0x200		/* slave address detected */
-#define ISR_BED         0x400           /* bus error no ACK/NAK */
+#define ISR_RWM		0x1		/* read/write mode */
+#define ISR_ACKNAK	0x2		/* ack/nak status */
+#define ISR_UB		0x4		/* unit busy */
+#define ISR_IBB		0x8		/* bus busy */
+#define ISR_SSD		0x10		/* slave stop detected */
+#define ISR_ALD		0x20		/* arbitration loss detected */
+#define ISR_ITE		0x40		/* tx buffer empty */
+#define ISR_IRF		0x80		/* rx buffer full */
+#define ISR_GCAD	0x100		/* general call address detected */
+#define ISR_SAD		0x200		/* slave address detected */
+#define ISR_BED		0x400		/* bus error no ACK/NAK */
 
 /*
  * Serial Audio Controller
  */
-
-
 /* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
- * short defines because there is too much chance of namespace collision */
-
+ * short defines because there is too much chance of namespace collision
+ */
 /*#define SACR0		__REG(0x40400000)  /  Global Control Register */
 /*#define SACR1		__REG(0x40400004)  /  Serial Audio I 2 S/MSB-Justified Control Register */
 /*#define SASR0		__REG(0x4040000C)  /  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
@@ -477,7 +488,6 @@ typedef void            (*ExcpHndlr) (void) ;
 /*
  * AC97 Controller registers
  */
-
 #define POCR		__REG(0x40500000)  /* PCM Out Control Register */
 #define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 
@@ -551,7 +561,6 @@ typedef void            (*ExcpHndlr) (void) ;
 #define PMC_REG_BASE	__REG(0x40500400)  /* Primary Modem Codec */
 #define SMC_REG_BASE	__REG(0x40500500)  /* Secondary Modem Codec */
 
-
 /*
  * USB Device Controller
  */
@@ -710,11 +719,63 @@ typedef void            (*ExcpHndlr) (void) ;
 #define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
 #define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
 
+#if defined(CONFIG_PXA27X)
+/*
+ * USB Host Controller
+ */
+#define UHCREV		__REG(0x4C000000)
+#define UHCHCON		__REG(0x4C000004)
+#define UHCCOMS		__REG(0x4C000008)
+#define UHCINTS		__REG(0x4C00000C)
+#define UHCINTE		__REG(0x4C000010)
+#define UHCINTD		__REG(0x4C000014)
+#define UHCHCCA		__REG(0x4C000018)
+#define UHCPCED		__REG(0x4C00001C)
+#define UHCCHED		__REG(0x4C000020)
+#define UHCCCED		__REG(0x4C000024)
+#define UHCBHED		__REG(0x4C000028)
+#define UHCBCED		__REG(0x4C00002C)
+#define UHCDHEAD	__REG(0x4C000030)
+#define UHCFMI		__REG(0x4C000034)
+#define UHCFMR		__REG(0x4C000038)
+#define UHCFMN		__REG(0x4C00003C)
+#define UHCPERS		__REG(0x4C000040)
+#define UHCLST		__REG(0x4C000044)
+#define UHCRHDA		__REG(0x4C000048)
+#define UHCRHDB		__REG(0x4C00004C)
+#define UHCRHS		__REG(0x4C000050)
+#define UHCRHPS1	__REG(0x4C000054)
+#define UHCRHPS2	__REG(0x4C000058)
+#define UHCRHPS3	__REG(0x4C00005C)
+#define UHCSTAT		__REG(0x4C000060)
+#define UHCHR		__REG(0x4C000064)
+#define UHCHIE		__REG(0x4C000068)
+#define UHCHIT		__REG(0x4C00006C)
+
+#define UHCHR_FSBIR	(1<<0)
+#define UHCHR_FHR	(1<<1)
+#define UHCHR_CGR	(1<<2)
+#define UHCHR_SSDC	(1<<3)
+#define UHCHR_UIT	(1<<4)
+#define UHCHR_SSE	(1<<5)
+#define UHCHR_PSPL	(1<<6)
+#define UHCHR_PCPL	(1<<7)
+#define UHCHR_SSEP0	(1<<9)
+#define UHCHR_SSEP1	(1<<10)
+#define UHCHR_SSEP2	(1<<11)
+
+#define UHCHIE_UPRIE	(1<<13)
+#define UHCHIE_UPS2IE	(1<<12)
+#define UHCHIE_UPS1IE	(1<<11)
+#define UHCHIE_TAIE	(1<<10)
+#define UHCHIE_HBAIE	(1<<8)
+#define UHCHIE_RWIE	(1<<7)
+
+#endif
 
 /*
  * Fast Infrared Communication Port
  */
-
 #define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
 #define ICCR1		__REG(0x40800004)  /* ICP Control Register 1 */
 #define ICCR2		__REG(0x40800008)  /* ICP Control Register 2 */
@@ -722,26 +783,36 @@ typedef void            (*ExcpHndlr) (void) ;
 #define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
 #define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */
 
-
 /*
  * Real Time Clock
  */
-
 #define RCNR		__REG(0x40900000)  /* RTC Count Register */
 #define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
 #define RTSR		__REG(0x40900008)  /* RTC Status Register */
 #define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
-
+#define RDAR1	   __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2	   __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1	   __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2	   __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1	   __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
+#define SWAR2	   __REG(0x40900030)  /* Stopwatch Alarm Register 2 */
+#define PIAR	   __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+#define RDCR	   __REG(0x40900010)  /* RTC Day Count Register. */
+#define RYCR	   __REG(0x40900014)  /* RTC Year Count Register. */
+#define SWCR	   __REG(0x40900028)  /* Stopwatch Count Register */
+#define RTCPICR	   __REG(0x40900034)  /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE  (1 << 15)   /* Peridoc interrupt count enable */
+#define RTSR_PIALE (1 << 14)   /* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL  (1 << 13)   /* Peridoc  interrupt Alarm status */
 #define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
 #define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
 #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
 #define RTSR_AL		(1 << 0)	/* RTC alarm detected */
 
-
 /*
  * OS Timer & Match Registers
  */
-
 #define OSMR0		__REG(0x40A00000)  /* */
 #define OSMR1		__REG(0x40A00004)  /* */
 #define OSMR2		__REG(0x40A00008)  /* */
@@ -763,11 +834,9 @@ typedef void            (*ExcpHndlr) (void) ;
 #define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
 #define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
 
-
 /*
  * Pulse Width Modulator
  */
-
 #define PWM_CTRL0	__REG(0x40B00000)  /* PWM 0 Control Register */
 #define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
 #define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */
@@ -776,11 +845,9 @@ typedef void            (*ExcpHndlr) (void) ;
 #define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
 #define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */
 
-
 /*
  * Interrupt Controller
  */
-
 #define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
 #define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
 #define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
@@ -788,11 +855,9 @@ typedef void            (*ExcpHndlr) (void) ;
 #define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
 #define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */
 
-
 /*
  * General Purpose I/O
  */
-
 #define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
 #define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
 #define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
@@ -831,6 +896,37 @@ typedef void            (*ExcpHndlr) (void) ;
 /* More handy macros.  The argument is a literal GPIO number. */
 
 #define GPIO_bit(x)	(1 << ((x) & 0x1f))
+
+#ifdef CONFIG_PXA27X
+
+/* Interrupt Controller */
+
+#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+#define _GPLR(x)	__REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define _GPDR(x)	__REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define _GPSR(x)	__REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define _GPCR(x)	__REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define _GRER(x)	__REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define _GFER(x)	__REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#define GPLR(x)		((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
+#define GPDR(x)		((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
+#define GPSR(x)		((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
+#define GPCR(x)		((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
+#define GRER(x)		((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
+#define GFER(x)		((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
+#define GEDR(x)		((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
+#define GAFR(x)		((((x) & 0x7f) < 96) ? _GAFR(x) : \
+			 ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+#else
+
 #define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)
 #define GPDR(x)		__REG2(0x40E0000C, ((x) & 0x60) >> 3)
 #define GPSR(x)		__REG2(0x40E00018, ((x) & 0x60) >> 3)
@@ -840,6 +936,8 @@ typedef void            (*ExcpHndlr) (void) ;
 #define GEDR(x)		__REG2(0x40E00048, ((x) & 0x60) >> 3)
 #define GAFR(x)		__REG2(0x40E00054, ((x) & 0x70) >> 2)
 
+#endif
+
 /* GPIO alternate function assignments */
 
 #define GPIO1_RST		1	/* reset */
@@ -968,10 +1066,10 @@ typedef void            (*ExcpHndlr) (void) ;
 #define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
 #define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
 #define GPIO28_BITCLK_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
-#define GPIO29_SDATA_IN_AC97_MD	(29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
 #define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
 #define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
-#define GPIO30_SDATA_OUT_I2S_MD	(30 | GPIO_ALT_FN_1_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
 #define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
 #define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
 #define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
@@ -1038,11 +1136,12 @@ typedef void            (*ExcpHndlr) (void) ;
 #define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
 #define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
 
+#define GPIO117_SCL	     (117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA	     (118 | GPIO_ALT_FN_1_OUT)
 
 /*
  * Power Manager
  */
-
 #define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */
 #define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */
 #define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */
@@ -1054,8 +1153,62 @@ typedef void            (*ExcpHndlr) (void) ;
 #define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
 #define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
 #define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3		__REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
 #define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */
 
+#define	   PSLR	   __REG(0x40F00034)	/* Power Manager Sleep Config Register */
+#define	   PSTR	   __REG(0x40F00038)	/* Power Manager Standby Config Register */
+#define	   PSNR	   __REG(0x40F0003C)	/* Power Manager Sense Config Register */
+#define	   PVCR	   __REG(0x40F00040)	/* Power Manager VoltageControl Register */
+#define	   PKWR	   __REG(0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
+#define	   PKSR	   __REG(0x40F00054)	/* Power Manager KB Level-Detect Register */
+#define	   PCMD(x) __REG(0x40F00080 + x*4)
+#define	   PCMD0   __REG(0x40F00080 + 0 * 4)
+#define	   PCMD1   __REG(0x40F00080 + 1 * 4)
+#define	   PCMD2   __REG(0x40F00080 + 2 * 4)
+#define	   PCMD3   __REG(0x40F00080 + 3 * 4)
+#define	   PCMD4   __REG(0x40F00080 + 4 * 4)
+#define	   PCMD5   __REG(0x40F00080 + 5 * 4)
+#define	   PCMD6   __REG(0x40F00080 + 6 * 4)
+#define	   PCMD7   __REG(0x40F00080 + 7 * 4)
+#define	   PCMD8   __REG(0x40F00080 + 8 * 4)
+#define	   PCMD9   __REG(0x40F00080 + 9 * 4)
+#define	   PCMD10  __REG(0x40F00080 + 10 * 4)
+#define	   PCMD11  __REG(0x40F00080 + 11 * 4)
+#define	   PCMD12  __REG(0x40F00080 + 12 * 4)
+#define	   PCMD13  __REG(0x40F00080 + 13 * 4)
+#define	   PCMD14  __REG(0x40F00080 + 14 * 4)
+#define	   PCMD15  __REG(0x40F00080 + 15 * 4)
+#define	   PCMD16  __REG(0x40F00080 + 16 * 4)
+#define	   PCMD17  __REG(0x40F00080 + 17 * 4)
+#define	   PCMD18  __REG(0x40F00080 + 18 * 4)
+#define	   PCMD19  __REG(0x40F00080 + 19 * 4)
+#define	   PCMD20  __REG(0x40F00080 + 20 * 4)
+#define	   PCMD21  __REG(0x40F00080 + 21 * 4)
+#define	   PCMD22  __REG(0x40F00080 + 22 * 4)
+#define	   PCMD23  __REG(0x40F00080 + 23 * 4)
+#define	   PCMD24  __REG(0x40F00080 + 24 * 4)
+#define	   PCMD25  __REG(0x40F00080 + 25 * 4)
+#define	   PCMD26  __REG(0x40F00080 + 26 * 4)
+#define	   PCMD27  __REG(0x40F00080 + 27 * 4)
+#define	   PCMD28  __REG(0x40F00080 + 28 * 4)
+#define	   PCMD29  __REG(0x40F00080 + 29 * 4)
+#define	   PCMD30  __REG(0x40F00080 + 30 * 4)
+#define	   PCMD31  __REG(0x40F00080 + 31 * 4)
+
+#define	   PCMD_MBC    (1<<12)
+#define	   PCMD_DCE    (1<<11)
+#define	   PCMD_LC     (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define	   PCMD_SQC    (3<<8)  /* currently only bit 8 is changerable, */
+				/* bit 9 should be 0 all day. */
+#define PVCR_VCSA		   (0x1<<14)
+#define PVCR_CommandDelay	   (0xf80)
+/* define MACRO for Power Manager General Configuration Register (PCFR) */
+#define PCFR_FVC		   (0x1 << 10)
+#define PCFR_PI2C_EN		   (0x1 << 6)
+
+#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
 #define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
 #define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
 #define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
@@ -1072,22 +1225,18 @@ typedef void            (*ExcpHndlr) (void) ;
 #define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
 #define RCSR_HWR	(1 << 0)	/* Hardware Reset */
 
-
 /*
  * SSP Serial Port Registers
  */
-
 #define SSCR0		__REG(0x41000000)  /* SSP Control Register 0 */
 #define SSCR1		__REG(0x41000004)  /* SSP Control Register 1 */
 #define SSSR		__REG(0x41000008)  /* SSP Status Register */
 #define SSITR		__REG(0x4100000C)  /* SSP Interrupt Test Register */
 #define SSDR		__REG(0x41000010)  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
 
-
 /*
  * MultiMediaCard (MMC) controller
  */
-
 #define MMC_STRPCL	__REG(0x41100000)  /* Control to start and stop MMC clock */
 #define MMC_STAT	__REG(0x41100004)  /* MMC Status Register (read only) */
 #define MMC_CLKRT	__REG(0x41100008)  /* MMC clock rate */
@@ -1107,24 +1256,37 @@ typedef void            (*ExcpHndlr) (void) ;
 #define MMC_RXFIFO	__REG(0x41100040)  /* Receive FIFO (read only) */
 #define MMC_TXFIFO	__REG(0x41100044)  /* Transmit FIFO (write only) */
 
-
 /*
  * Core Clock
  */
-
 #define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
 #define CKEN		__REG(0x41300004)  /* Clock Enable Register */
 #define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
 
 #define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_PXA27X)
 #define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
 #define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
 
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
+#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
+#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
 #define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
 #define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
 #define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
 #define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
 #define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
+#if defined(CONFIG_PXA27X)
+#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
+#endif
 #define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
 #define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
 #define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
@@ -1137,34 +1299,36 @@ typedef void            (*ExcpHndlr) (void) ;
 #define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
 #define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
 
-#define  CCCR_L09      (0x1F)
-#define  CCCR_L27      (0x1)
-#define  CCCR_L32      (0x2)
-#define  CCCR_L36      (0x3)
-#define  CCCR_L40      (0x4)
-#define  CCCR_L45      (0x5)
-
-#define  CCCR_M1       (0x1 << 5)
-#define  CCCR_M2       (0x2 << 5)
-#define  CCCR_M4       (0x3 << 5)
-
-#define  CCCR_N10      (0x2 << 7)
-#define  CCCR_N15      (0x3 << 7)
-#define  CCCR_N20      (0x4 << 7)
-#define  CCCR_N25      (0x5 << 7)
-#define  CCCR_N30      (0x6 << 7)
+#if !defined(CONFIG_PXA27X)
+#define	 CCCR_L09      (0x1F)
+#define	 CCCR_L27      (0x1)
+#define	 CCCR_L32      (0x2)
+#define	 CCCR_L36      (0x3)
+#define	 CCCR_L40      (0x4)
+#define	 CCCR_L45      (0x5)
+
+#define	 CCCR_M1       (0x1 << 5)
+#define	 CCCR_M2       (0x2 << 5)
+#define	 CCCR_M4       (0x3 << 5)
+
+#define	 CCCR_N10      (0x2 << 7)
+#define	 CCCR_N15      (0x3 << 7)
+#define	 CCCR_N20      (0x4 << 7)
+#define	 CCCR_N25      (0x5 << 7)
+#define	 CCCR_N30      (0x6 << 7)
+#endif
 
 /*
  * LCD
  */
-
 #define LCCR0		__REG(0x44000000)  /* LCD Controller Control Register 0 */
 #define LCCR1		__REG(0x44000004)  /* LCD Controller Control Register 1 */
 #define LCCR2		__REG(0x44000008)  /* LCD Controller Control Register 2 */
 #define LCCR3		__REG(0x4400000C)  /* LCD Controller Control Register 3 */
 #define DFBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
 #define DFBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
-#define LCSR		__REG(0x44000038)  /* LCD Controller Status Register */
+#define LCSR0		__REG(0x44000038)  /* LCD Controller Status Register */
+#define LCSR1		__REG(0x44000034)  /* LCD Controller Status Register */
 #define LIIDR		__REG(0x4400003C)  /* LCD Controller Interrupt ID Register */
 #define TMEDRGBR	__REG(0x44000040)  /* TMED RGB Seed Register */
 #define TMEDCR		__REG(0x44000044)  /* TMED Control Register */
@@ -1192,51 +1356,56 @@ typedef void            (*ExcpHndlr) (void) ;
 #define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
 #define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
 #define LCCR0_PDD_S	12
-#define LCCR0_BM	(1 << 20) 	/* Branch mask */
+#define LCCR0_BM	(1 << 20)	/* Branch mask */
 #define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
+#if defined(CONFIG_PXA27X)
+#define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
+#define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
+#define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
+#endif
 
-#define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
-#define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
+#define LCCR1_PPL	Fld (10, 0)	 /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)		/* Display Width [1..800 pix.]	*/ \
 			(((Pixel) - 1) << FShft (LCCR1_PPL))
 
-#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization     */
-#define LCCR1_HorSnchWdth(Tpix)         /* Horizontal Synchronization     */ \
-					/* pulse Width [1..64 Tpix]       */ \
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	  */
+#define LCCR1_HorSnchWdth(Tpix)		/* Horizontal Synchronization	  */ \
+					/* pulse Width [1..64 Tpix]	  */ \
 			(((Tpix) - 1) << FShft (LCCR1_HSW))
 
-#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait    */
-					/* count - 1 [Tpix]                */
-#define LCCR1_EndLnDel(Tpix)            /*  End-of-Line Delay              */ \
-					/*  [1..256 Tpix]                  */ \
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait	   */
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
 			(((Tpix) - 1) << FShft (LCCR1_ELW))
 
-#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock   */
-					/* Wait count - 1 [Tpix]           */
-#define LCCR1_BegLnDel(Tpix)            /*  Beginning-of-Line Delay        */ \
-					/*  [1..256 Tpix]                  */ \
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
 			(((Tpix) - 1) << FShft (LCCR1_BLW))
 
 
-#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1              */
-#define LCCR2_DisHght(Line)             /*  Display Height [1..1024 lines] */ \
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
 			(((Line) - 1) << FShft (LCCR2_LPP))
 
-#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse  */
-					/* Width - 1 [Tln] (L_FCLK)        */
-#define LCCR2_VrtSnchWdth(Tln)          /*  Vertical Synchronization pulse */ \
-					/*  Width [1..64 Tln]              */ \
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
 			(((Tln) - 1) << FShft (LCCR2_VSW))
 
-#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait    */
-					/* count [Tln]                     */
-#define LCCR2_EndFrmDel(Tln)            /*  End-of-Frame Delay             */ \
-					/*  [0..255 Tln]                   */ \
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait	   */
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
 			((Tln) << FShft (LCCR2_EFW))
 
-#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock   */
-					/* Wait count [Tln]                */
-#define LCCR2_BegFrmDel(Tln)            /*  Beginning-of-Frame Delay       */ \
-					/*  [0..255 Tln]                   */ \
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
 			((Tln) << FShft (LCCR2_BFW))
 
 #if 0
@@ -1257,79 +1426,100 @@ typedef void            (*ExcpHndlr) (void) ;
 #endif
 #define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
 
+#define LCCR3_PDFOR_0	 (0 << 30)
+#define LCCR3_PDFOR_1	 (1 << 30)
+#define LCCR3_PDFOR_2	 (2 << 30)
+#define LCCR3_PDFOR_3	 (3 << 30)
+
 
-#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
-#define LCCR3_PixClkDiv(Div)            /* Pixel Clock Divisor */ \
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)		/* Pixel Clock Divisor */ \
 			(((Div) << FShft (LCCR3_PCD)))
 
 
-#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
-#define LCCR3_Bpp(Bpp)                  /* Bit Per Pixel */ \
-			(((Bpp) << FShft (LCCR3_BPP)))
+#define LCCR3_BPP	Fld (3, 24)	/* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)			/* Bit Per Pixel */ \
+			((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
 
-#define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
-#define LCCR3_Acb(Acb)                  /* BAC Bias */ \
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias */
+#define LCCR3_Acb(Acb)			/* BAC Bias */ \
 			(((Acb) << FShft (LCCR3_ACB)))
 
-#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  Horizontal Synchronization     */
-					/*  pulse active High              */
-#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  Horizontal Synchronization     */
-
-#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  Vertical Synchronization pulse */
-					/*  active High                    */
-#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  Vertical Synchronization pulse */
-					/*  active Low                     */
-
-#define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
-#define LCSR_SOF	(1 << 1)	/* Start of frame */
-#define LCSR_BER	(1 << 2)	/* Bus error */
-#define LCSR_ABC	(1 << 3)	/* AC Bias count */
-#define LCSR_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
-#define LCSR_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
-#define LCSR_OU		(1 << 6)	/* output FIFO underrun */
-#define LCSR_QD		(1 << 7)	/* quick disable */
-#define LCSR_EOF	(1 << 8)	/* end of frame */
-#define LCSR_BS		(1 << 9)	/* branch status */
-#define LCSR_SINT	(1 << 10)	/* subsequent interrupt */
-
-#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
-
-#define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
-#define LCSR_SOF	(1 << 1)	/* Start of frame */
-#define LCSR_BER	(1 << 2)	/* Bus error */
-#define LCSR_ABC	(1 << 3)	/* AC Bias count */
-#define LCSR_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
-#define LCSR_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
-#define LCSR_OU		(1 << 6)	/* output FIFO underrun */
-#define LCSR_QD		(1 << 7)	/* quick disable */
-#define LCSR_EOF	(1 << 8)	/* end of frame */
-#define LCSR_BS		(1 << 9)	/* branch status */
-#define LCSR_SINT	(1 << 10)	/* subsequent interrupt */
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High			   */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low			   */
+
+#define LCSR0_LDD	(1 << 0)	/* LCD Disable Done */
+#define LCSR0_SOF	(1 << 1)	/* Start of frame */
+#define LCSR0_BER	(1 << 2)	/* Bus error */
+#define LCSR0_ABC	(1 << 3)	/* AC Bias count */
+#define LCSR0_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
+#define LCSR0_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
+#define LCSR0_OU	(1 << 6)	/* output FIFO underrun */
+#define LCSR0_QD	(1 << 7)	/* quick disable */
+#define LCSR0_EOF0	(1 << 8)	/* end of frame */
+#define LCSR0_BS	(1 << 9)	/* branch status */
+#define LCSR0_SINT	(1 << 10)	/* subsequent interrupt */
+
+#define LCSR1_SOF1	(1 << 0)
+#define LCSR1_SOF2	(1 << 1)
+#define LCSR1_SOF3	(1 << 2)
+#define LCSR1_SOF4	(1 << 3)
+#define LCSR1_SOF5	(1 << 4)
+#define LCSR1_SOF6	(1 << 5)
+
+#define LCSR1_EOF1	(1 << 8)
+#define LCSR1_EOF2	(1 << 9)
+#define LCSR1_EOF3	(1 << 10)
+#define LCSR1_EOF4	(1 << 11)
+#define LCSR1_EOF5	(1 << 12)
+#define LCSR1_EOF6	(1 << 13)
+
+#define LCSR1_BS1	(1 << 16)
+#define LCSR1_BS2	(1 << 17)
+#define LCSR1_BS3	(1 << 18)
+#define LCSR1_BS4	(1 << 19)
+#define LCSR1_BS5	(1 << 20)
+#define LCSR1_BS6	(1 << 21)
+
+#define LCSR1_IU2	(1 << 25)
+#define LCSR1_IU3	(1 << 26)
+#define LCSR1_IU4	(1 << 27)
+#define LCSR1_IU5	(1 << 28)
+#define LCSR1_IU6	(1 << 29)
 
 #define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
+#if defined(CONFIG_PXA27X)
+#define LDCMD_SOFINT	(1 << 22)
+#define LDCMD_EOFINT	(1 << 21)
+#endif
 
 /*
  * Memory controller
  */
-
 #define MEMC_BASE	__REG(0x48000000)  /* Base of Memory Controller */
-#define MDCNFG_OFFSET   0x0
-#define MDREFR_OFFSET   0x4
-#define MSC0_OFFSET     0x8
-#define MSC1_OFFSET     0xC
-#define MSC2_OFFSET     0x10
-#define MECR_OFFSET     0x14
-#define SXLCR_OFFSET    0x18
-#define SXCNFG_OFFSET   0x1C
-#define FLYCNFG_OFFSET  0x20
-#define SXMRS_OFFSET    0x24
-#define MCMEM0_OFFSET   0x28
-#define MCMEM1_OFFSET   0x2C
-#define MCATT0_OFFSET   0x30
-#define MCATT1_OFFSET   0x34
-#define MCIO0_OFFSET    0x38
-#define MCIO1_OFFSET    0x3C
-#define MDMRS_OFFSET    0x40
+#define MDCNFG_OFFSET	0x0
+#define MDREFR_OFFSET	0x4
+#define MSC0_OFFSET	0x8
+#define MSC1_OFFSET	0xC
+#define MSC2_OFFSET	0x10
+#define MECR_OFFSET	0x14
+#define SXLCR_OFFSET	0x18
+#define SXCNFG_OFFSET	0x1C
+#define FLYCNFG_OFFSET	0x20
+#define SXMRS_OFFSET	0x24
+#define MCMEM0_OFFSET	0x28
+#define MCMEM1_OFFSET	0x2C
+#define MCATT0_OFFSET	0x30
+#define MCATT1_OFFSET	0x34
+#define MCIO0_OFFSET	0x38
+#define MCIO1_OFFSET	0x3C
+#define MDMRS_OFFSET	0x40
 
 #define MDCNFG		__REG(0x48000000)  /* SDRAM Configuration Register 0 */
 #define MDCNFG_DE0	0x00000001
@@ -1369,5 +1559,191 @@ typedef void            (*ExcpHndlr) (void) ;
 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
 
-
-#endif
+#if defined(CONFIG_PXA27X)
+
+#define ARB_CNTRL	__REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK		(1<<29)	   /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
+#define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
+#define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
+#define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
+#define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
+
+/* Interrupt Controller */
+
+#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+/* General Purpose I/O */
+
+#define GAFR3_L		__REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U		__REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
+#define GPLR3		__REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3		__REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3		__REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3		__REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO <127:96> */
+#define GRER3		__REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3		__REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GEDR3		__REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+/* Core Clock */
+
+#define CCSR		__REG(0x4130000C) /* Core Clock Status Register */
+
+#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
+#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
+
+/* Memory controller */
+
+#define MDREFR_K0DB4	(1 << 29)	  /* SDCLK[0] divide by 4 */
+
+/* LCD registers */
+#define LCCR4		__REG(0x44000010)  /* LCD Controller Control Register 4 */
+#define LCCR5		__REG(0x44000014)  /* LCD Controller Control Register 5 */
+#define FBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
+#define FBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
+#define FBR2		__REG(0x44000028)  /* DMA Channel 2 Frame Branch Register */
+#define FBR3		__REG(0x4400002C)  /* DMA Channel 3 Frame Branch Register */
+#define FBR4		__REG(0x44000030)  /* DMA Channel 4 Frame Branch Register */
+#define FDADR2		__REG(0x44000220)  /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2		__REG(0x44000224)  /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2		__REG(0x44000228)  /* DMA Channel 2 Frame ID Register */
+#define LDCMD2		__REG(0x4400022C)  /* DMA Channel 2 Command Register */
+#define FDADR3		__REG(0x44000230)  /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3		__REG(0x44000234)  /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3		__REG(0x44000238)  /* DMA Channel 3 Frame ID Register */
+#define LDCMD3		__REG(0x4400023C)  /* DMA Channel 3 Command Register */
+#define FDADR4		__REG(0x44000240)  /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4		__REG(0x44000244)  /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4		__REG(0x44000248)  /* DMA Channel 4 Frame ID Register */
+#define LDCMD4		__REG(0x4400024C)  /* DMA Channel 4 Command Register */
+#define FDADR5		__REG(0x44000250)  /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5		__REG(0x44000254)  /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5		__REG(0x44000258)  /* DMA Channel 5 Frame ID Register */
+#define LDCMD5		__REG(0x4400025C)  /* DMA Channel 5 Command Register */
+
+#define OVL1C1		__REG(0x44000050)  /* Overlay 1 Control Register 1 */
+#define OVL1C2		__REG(0x44000060)  /* Overlay 1 Control Register 2 */
+#define OVL2C1		__REG(0x44000070)  /* Overlay 2 Control Register 1 */
+#define OVL2C2		__REG(0x44000080)  /* Overlay 2 Control Register 2 */
+#define CCR		__REG(0x44000090)  /* Cursor Control Register */
+
+#define FBR5		__REG(0x44000110)  /* DMA Channel 5 Frame Branch Register */
+#define FBR6		__REG(0x44000114)  /* DMA Channel 6 Frame Branch Register */
+
+#define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
+#define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
+
+#define LCCR5_SOFM1	(1<<0)		/* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3	(1<<2)		/* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4	(1<<3)		/* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5	(1<<4)		/* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6	(1<<5)		/* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1	(1<<8)		/* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2	(1<<9)		/* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3	(1<<10)		/* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4	(1<<11)		/* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5	(1<<12)		/* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6	(1<<13)		/* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1	(1<<16)		/* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2	(1<<17)		/* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3	(1<<18)		/* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4	(1<<19)		/* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5	(1<<20)		/* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6	(1<<21)		/* Branch mask for data command	 (channel 6) */
+
+#define LCCR5_IUM1	(1<<24)		/* Input FIFO Underrun Mask for Overlay 1  */
+#define LCCR5_IUM2	(1<<25)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM3	(1<<26)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM4	(1<<27)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM5	(1<<28)		/* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6	(1<<29)		/* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN	(1<<31)		/* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN	(1<<31)		/* Enable bit for Overlay 2 */
+#define CCR_CEN		(1<<31)		/* Enable bit for Cursor */
+
+/* Keypad controller */
+
+#define KPC		__REG(0x41500000) /* Keypad Interface Control register */
+#define KPDK		__REG(0x41500008) /* Keypad Interface Direct Key register */
+#define KPREC		__REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
+#define KPMK		__REG(0x41500018) /* Keypad Intefcace Matrix Key register */
+#define KPAS		__REG(0x41500020) /* Keypad Interface Automatic Scan register */
+#define KPASMKP0	__REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1	__REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2	__REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3	__REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI		__REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+
+#define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
+#define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
+#define KPC_MI		(0x1 << 22)  /* Matrix interrupt bit */
+#define KPC_IMKP	(0x1 << 21)  /* Ignore Multiple Key Press */
+#define KPC_MS7		(0x1 << 20)  /* Matrix scan line 7 */
+#define KPC_MS6		(0x1 << 19)  /* Matrix scan line 6 */
+#define KPC_MS5		(0x1 << 18)  /* Matrix scan line 5 */
+#define KPC_MS4		(0x1 << 17)  /* Matrix scan line 4 */
+#define KPC_MS3		(0x1 << 16)  /* Matrix scan line 3 */
+#define KPC_MS2		(0x1 << 15)  /* Matrix scan line 2 */
+#define KPC_MS1		(0x1 << 14)  /* Matrix scan line 1 */
+#define KPC_MS0		(0x1 << 13)  /* Matrix scan line 0 */
+#define KPC_ME		(0x1 << 12)  /* Matrix Keypad Enable */
+#define KPC_MIE		(0x1 << 11)  /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL	(0x1 <<	 9)  /* Direct Key Debounce select */
+#define KPC_DI		(0x1 <<	 5)  /* Direct key interrupt bit */
+#define KPC_DEE0	(0x1 <<	 2)  /* Rotary Encoder 0 Enable */
+#define KPC_DE		(0x1 <<	 1)  /* Direct Keypad Enable */
+#define KPC_DIE		(0x1 <<	 0)  /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP	(0x1 << 31)
+#define KPDK_DK7	(0x1 <<	 7)
+#define KPDK_DK6	(0x1 <<	 6)
+#define KPDK_DK5	(0x1 <<	 5)
+#define KPDK_DK4	(0x1 <<	 4)
+#define KPDK_DK3	(0x1 <<	 3)
+#define KPDK_DK2	(0x1 <<	 2)
+#define KPDK_DK1	(0x1 <<	 1)
+#define KPDK_DK0	(0x1 <<	 0)
+
+#define KPREC_OF1	(0x1 << 31)
+#define kPREC_UF1	(0x1 << 30)
+#define KPREC_OF0	(0x1 << 15)
+#define KPREC_UF0	(0x1 << 14)
+
+#define KPMK_MKP	(0x1 << 31)
+#define KPAS_SO		(0x1 << 31)
+#define KPASMKPx_SO	(0x1 << 31)
+
+#define GPIO113_BIT	   (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR	   __REG(0x40F00034)
+#define PSTR	   __REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
+#define PSNR	   __REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
+#define PVCR	   __REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
+#define PKWR	   __REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR	   __REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4	    __REG(0x40A00080)  /* */
+#define OSCR4	    __REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4	    __REG(0x40A000C0)  /* */
+
+#endif	/* CONFIG_PXA27X */
+
+#endif	/* _PXA_REGS_H_ */
diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h
new file mode 100644
index 0000000..b8797d1
--- /dev/null
+++ b/include/configs/adsvix.h
@@ -0,0 +1,352 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL		/* undef for developing */
+#define RTC
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
+#define CONFIG_ADSVIX		1	/* on a Adsvix Board     */
+#define CONFIG_MMC		1
+#define BOARD_LATE_INIT		1
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART on ADSVIX */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE	       38400
+
+#define CONFIG_DOS_PARTITION   1
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SERVERIP		192.168.1.99
+#define CONFIG_BOOTCOMMAND	"run boot_flash"
+#define CONFIG_BOOTARGS		"console=ttyS0,38400 ramdisk_size=12288"\
+				" rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"program_boot_cf="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_cf="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_cf="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_cf="							\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0030000 uzImage && "	\
+				"fatload ide 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"program_boot_mmc="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_mmc="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_mmc="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_mmc="							\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0030000 uzImage && "	\
+				"fatload mmc 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"boot_flash="							\
+			"cp.b 0x1c0000 0xa0800000 0x500000; "		\
+			"bootm 0x40000\0"				\
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+/* #define CONFIG_INITRD_TAG	 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE		0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+
+#define CFG_GPSR0_VAL		0x00018004
+#define CFG_GPSR1_VAL		0x004F0080
+#define CFG_GPSR2_VAL		0x13EFC000
+#define CFG_GPSR3_VAL		0x0006E032
+#define CFG_GPCR0_VAL		0x084AFE1A
+#define CFG_GPCR1_VAL		0x003003F2
+#define CFG_GPCR2_VAL		0x0C014000
+#define CFG_GPCR3_VAL		0x00000C00
+#define CFG_GPDR0_VAL		0xCBC3BFFC
+#define CFG_GPDR1_VAL		0x00FFABF3
+#define CFG_GPDR2_VAL		0x1EEFFC00
+#define CFG_GPDR3_VAL		0x0187EC32
+#define CFG_GAFR0_L_VAL		0x84400000
+#define CFG_GAFR0_U_VAL		0xA51A8010
+#define CFG_GAFR1_L_VAL		0x699A955A
+#define CFG_GAFR1_U_VAL		0x0005A0AA
+#define CFG_GAFR2_L_VAL		0x40000000
+#define CFG_GAFR2_U_VAL		0x0109A400
+#define CFG_GAFR3_L_VAL		0x54000000
+#define CFG_GAFR3_U_VAL		0x00001409
+
+#define CFG_PSSR_VAL		0x20
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN		0x00400200
+#define CFG_CCCR		0x02000290 /*   520Mhz */
+/* #define CFG_CCCR		0x02000210  416 Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL		0x23F2B3DB
+#define CFG_MSC1_VAL		0x0000CCD1
+#define CFG_MSC2_VAL		0x0000B884
+#define CFG_MDCNFG_VAL		0x08000AC8
+#define CFG_MDREFR_VAL		0x0000001E
+#define CFG_MDMRS_VAL		0x00000000
+
+#define CFG_FLYCNFG_VAL		0x00010001
+#define CFG_SXCNFG_VAL		0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000002
+#define CFG_MCMEM0_VAL		0x00004204
+#define CFG_MCMEM1_VAL		0x00000000
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00000000
+#define CFG_MCIO0_VAL		0x00008407
+#define CFG_MCIO1_VAL		0x00000000
+
+#define CONFIG_PXA_PCMCIA 1
+#define CONFIG_PXA_IDE 1
+
+#define CONFIG_PCMCIA_SLOT_A 1
+/* just to keep build system happy  */
+
+#define CFG_PCMCIA_MEM_ADDR     0x28000000
+#define CFG_PCMCIA_MEM_SIZE     0x04000000
+
+
+#define CFG_IDE_MAXBUS		1
+/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1
+/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	0x20000000
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0x1f0
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x1f0
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x3f0
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER	1
+
+#define CFG_MONITOR_BASE	0
+#define CFG_MONITOR_LEN		0x20000
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment     	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+#endif	/* __CONFIG_H */