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authorJason Chen <b02280@freescale.com>2011-03-31 15:30:23 +0800
committerJason Chen <b02280@freescale.com>2011-03-31 15:30:23 +0800
commit0f165488b255c8243284e1fbf6ebd74f2795dd0a (patch)
tree25e2fe1d169f70a87336ce9ebc6d9f5645c6b0af
parent068bed0069dfe66bf01cc72fc4e41a32b2cb94d4 (diff)
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ENGR00141363: change mx53 uart clk parent to pll2
Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat
-rw-r--r--board/freescale/mx53_ard/lowlevel_init.S12
-rw-r--r--board/freescale/mx53_evk/lowlevel_init.S12
-rw-r--r--board/freescale/mx53_evk/mx53_evk.c21
-rw-r--r--board/freescale/mx53_loco/lowlevel_init.S12
-rw-r--r--board/freescale/mx53_smd/lowlevel_init.S12
-rw-r--r--include/configs/mx53_evk.h8
-rw-r--r--include/configs/mx53_evk_android.h8
-rwxr-xr-xinclude/configs/mx53_evk_mfg.h10
8 files changed, 60 insertions, 35 deletions
diff --git a/board/freescale/mx53_ard/lowlevel_init.S b/board/freescale/mx53_ard/lowlevel_init.S
index 249c2f8..2a251f7 100644
--- a/board/freescale/mx53_ard/lowlevel_init.S
+++ b/board/freescale/mx53_ard/lowlevel_init.S
@@ -128,6 +128,12 @@
ldr r1, CCM_VAL_0x00016154
str r1, [r0, #CLKCTL_CBCMR]
+ /*change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
@@ -150,10 +156,10 @@
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
+ /* make uart div=6*/
ldr r1, [r0, #CLKCTL_CSCDR1]
- orr r1, r1, #0x3f
- eor r1, r1, #0x3f
- orr r1, r1, #0x21
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
/* Restore the default values in the Gate registers */
diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S
index 7b1fbd7..0122353 100644
--- a/board/freescale/mx53_evk/lowlevel_init.S
+++ b/board/freescale/mx53_evk/lowlevel_init.S
@@ -128,6 +128,12 @@
ldr r1, CCM_VAL_0x00016154
str r1, [r0, #CLKCTL_CBCMR]
+ /*change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
@@ -150,10 +156,10 @@
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
+ /* make uart div=6*/
ldr r1, [r0, #CLKCTL_CSCDR1]
- orr r1, r1, #0x3f
- eor r1, r1, #0x3f
- orr r1, r1, #0x21
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
/* Restore the default values in the Gate registers */
diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
index aea2adb..1b8fbaa 100644
--- a/board/freescale/mx53_evk/mx53_evk.c
+++ b/board/freescale/mx53_evk/mx53_evk.c
@@ -490,26 +490,27 @@ static int _identify_board_fix_up(int id0, int id1)
int ret = 0;
#ifdef CONFIG_CMD_CLOCK
- /* For EVK RevB, set DDR to 400MHz */
- if (id0 == 21 && id1 == 15) {
- ret = clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK);
+ /* For EVK RevA, set DDR to 300MHz */
+ if (id0 == 21 && (id1 == 18 || id1 == 19)) {
+ ret = clk_config(CONFIG_REF_CLK_FREQ, 600, PERIPH_CLK);
if (ret < 0)
return ret;
- ret = clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
+ /*reinit serial*/
+ serial_init();
+
+ ret = clk_config(CONFIG_REF_CLK_FREQ, 300, DDR_CLK);
if (ret < 0)
return ret;
+ }
- /* set up rev #2 for EVK RevB board */
+ /* set up rev #2 for EVK RevB board */
+ if (id0 == 21 && id1 == 15)
setup_board_rev(2);
- }
/* For ARM2 board */
- if (id0 == -1) {
- if (clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK) >= 0)
- clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
+ if (id0 == -1)
setup_board_rev(1);
- }
#endif
return ret;
diff --git a/board/freescale/mx53_loco/lowlevel_init.S b/board/freescale/mx53_loco/lowlevel_init.S
index 5b76063..ff879a6 100644
--- a/board/freescale/mx53_loco/lowlevel_init.S
+++ b/board/freescale/mx53_loco/lowlevel_init.S
@@ -126,6 +126,12 @@
ldr r1, CCM_VAL_0x00016154
str r1, [r0, #CLKCTL_CBCMR]
+ /*change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
@@ -148,10 +154,10 @@
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
+ /* make uart div=6*/
ldr r1, [r0, #CLKCTL_CSCDR1]
- orr r1, r1, #0x3f
- eor r1, r1, #0x3f
- orr r1, r1, #0x21
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
/* Restore the default values in the Gate registers */
diff --git a/board/freescale/mx53_smd/lowlevel_init.S b/board/freescale/mx53_smd/lowlevel_init.S
index 60ee843..07af735 100644
--- a/board/freescale/mx53_smd/lowlevel_init.S
+++ b/board/freescale/mx53_smd/lowlevel_init.S
@@ -126,6 +126,12 @@
ldr r1, CCM_VAL_0x00016154
str r1, [r0, #CLKCTL_CBCMR]
+ /*change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
@@ -148,10 +154,10 @@
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
+ /* make uart div=6*/
ldr r1, [r0, #CLKCTL_CSCDR1]
- orr r1, r1, #0x3f
- eor r1, r1, #0x3f
- orr r1, r1, #0x21
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
/* Restore the default values in the Gate registers */
diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
index e2458a0..4ddc10d 100644
--- a/include/configs/mx53_evk.h
+++ b/include/configs/mx53_evk.h
@@ -39,10 +39,10 @@
#define CONFIG_ARCH_MMU
#define CONFIG_MX53_HCLK_FREQ 24000000
-#define CONFIG_SYS_PLL2_FREQ 600
-#define CONFIG_SYS_AHB_PODF 4
-#define CONFIG_SYS_AXIA_PODF 1
-#define CONFIG_SYS_AXIB_PODF 2
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_evk_android.h b/include/configs/mx53_evk_android.h
index bceb849..ed9562d 100644
--- a/include/configs/mx53_evk_android.h
+++ b/include/configs/mx53_evk_android.h
@@ -39,10 +39,10 @@
#define CONFIG_ARCH_MMU
#define CONFIG_MX53_HCLK_FREQ 24000000
-#define CONFIG_SYS_PLL2_FREQ 600
-#define CONFIG_SYS_AHB_PODF 4
-#define CONFIG_SYS_AXIA_PODF 1
-#define CONFIG_SYS_AXIB_PODF 2
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_evk_mfg.h b/include/configs/mx53_evk_mfg.h
index bac8515..cb7ec8f 100755
--- a/include/configs/mx53_evk_mfg.h
+++ b/include/configs/mx53_evk_mfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
*
* Configuration settings for the MX53-EVK Freescale board.
*
@@ -40,10 +40,10 @@
#define CONFIG_ARCH_MMU
#define CONFIG_MX53_HCLK_FREQ 24000000
-#define CONFIG_SYS_PLL2_FREQ 600
-#define CONFIG_SYS_AHB_PODF 4
-#define CONFIG_SYS_AXIA_PODF 1
-#define CONFIG_SYS_AXIB_PODF 2
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
generated by cgit v1.1 at 2024-11-21 12:27:49 +0000