ENGR00137372 MX53: Switch back to use DCD and update DDR scripts

1. This patch is used to switch back to use DCD for flash header
instead of plug-in. This change request is due to the following
reasons:
1) U-boot community doesn't accept current plug-in solution when
upstreaming.
2) Plug-in isn't supported by MX53 ROM serial download mode.
No effective workaround is found now. To use the same code
base to support normal U-Boot and MFG tool better, adopt
DCD solution firstly.
3) Current MX53 DDR scripts don't exceed the length limitation
of DCD.

For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after
VCC and VDDA voltages are raised as 1.3V.
Since ARM2 CPU2 board share the same script with EVK, delete ARM2
CPU2 config files. ARM2 CPU2 board can share the same bootloader
with EVK.

2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards
The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under
http://compass.freescale.net/livelink/livelink?
func=ll&objId=221058910&objAction=browse&viewType=1
This script is published by ATX and FIL team on Dec 16th, 2010

3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc"
under the same compass folder

Signed-off-by: Lily Zhang <r58066@freescale.com>

14 files changed, 259 insertions, 1022 deletions

diff --git a/board/freescale/mx53_rd/flash_header.S b/board/freescale/mx53_rd/flash_header.S
index c153934..8496789 100644
--- a/board/freescale/mx53_rd/flash_header.S
+++ b/board/freescale/mx53_rd/flash_header.S
@@ -25,427 +25,162 @@
 # error "Must define the offset of flash header"
 #endif
 
+#define CPU_2_BE_32(l) \
+       ((((l) & 0x000000FF) << 24) | \
+	(((l) & 0x0000FF00) << 8)  | \
+	(((l) & 0x00FF0000) >> 8)  | \
+	(((l) & 0xFF000000) >> 24))
+
+#define MXC_DCD_ITEM(i, addr, val)   \
+dcd_node_##i:                        \
+        .word CPU_2_BE_32(addr) ;     \
+        .word CPU_2_BE_32(val)  ;     \
+
 .section ".text.flasheader", "x"
 	b	_start
 	.org	CONFIG_FLASH_HEADER_OFFSET
-
-ivt_header:             .long 0x402000D1    /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-app_code_jump_v:        .long (0xF8006000 + (plugin_start - TEXT_BASE))
-reserv1:                .long 0x0
-dcd_ptr:                .long 0x0
-boot_data_ptr:          .long (0xF8006000 + (boot_data - TEXT_BASE))
-self_ptr:               .long (0xF8006000 + (ivt_header - TEXT_BASE))
-app_code_csf:           .long 0x0
-reserv2:                .long 0x0
-boot_data:              .long 0xF8006000
-image_len:              .long 2*1024
-plugin:                 .long 0x1
-
-/* Second IVT to give entry point into the bootloader copied to DDR */
-ivt2_header:            .long 0x402000D1    /*Tag=0xD1, Len=0x0020, Ver=0x40 */
-app2_code_jump_v:       .long _start   /* Entry point for the bootloader */
-reserv3:                .long 0x0
-dcd2_ptr:               .long 0x0
-boot_data2_ptr:         .long boot_data2
-self_ptr2:              .long ivt2_header
-app_code_csf2:          .long 0x0
-reserv4:                .long 0x0
-boot_data2:             .long TEXT_BASE
-image_len2:             .long  _end - TEXT_BASE
-plugin2:                .long 0x0
-
-
-/* Here starts the plugin code */
-plugin_start:
-    /* Save the return address and the function arguments */
-    push    {r0-r3, lr}
-
-    ldr r0, =ROM_SI_REV
-    ldr r1, [r0]
-
-    cmp r1, #0x20
-
-/* DDR2 script for EVK, ARD, and ARM2 CPU2 boards */
+ivt_header:       .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:  .word _start
+reserv1:          .word 0x0
+dcd_ptr:          .word dcd_hdr
+boot_data_ptr:	  .word boot_data
+self_ptr:         .word ivt_header
+app_code_csf:     .word 0x0
+reserv2:          .word 0x0
+
+boot_data:        .word 0x77800000
+image_len:        .word _end - TEXT_BASE
+plugin:           .word 0x0
+
+/* TO1.0/TO2.0 DDR2 scripts for EVK, ARD and ARM2 CPU2 board */
 #if !defined(CONFIG_MX53_ARM2_DDR3)
-
-    /* IOMUX Setup */
-    ldr r0, =0x53fa8500
-    moveq r1, #0x00200000
-    movne r1, #0x00380000
-    add r2, r1, #0x40
-    mov r3, #0x00280000
-    mov r4, #0x00200000
-
-    str r1, [r0, #0x54]
-    str r1, [r0, #0x60]
-    str r1, [r0, #0x94]
-    str r1, [r0, #0x84]
-    str r2, [r0, #0x58]
-    str r2, [r0, #0x68]
-    str r2, [r0, #0x90]
-    str r2, [r0, #0x7c]
-    str r2, [r0, #0x64]
-    str r2, [r0, #0x80]
-
-    streq r1, [r0, #0x70]
-#if defined(CONFIG_MX53_EVK)
-    strne r4, [r0, #0x70]
-#else
-    strne r1, [r0, #0x70]
-#endif
-    str r3, [r0, #0x74]
-    streq r1, [r0, #0x78]
-#if defined(CONFIG_MX53_EVK)
-    strne r4, [r0, #0x78]
-#else
-    strne r1, [r0, #0x78]
-#endif
-    str r3, [r0, #0x88]
-
-    ldr r0, =0x53fa86f0
-    str r3, [r0, #0x0]
-    mov r2, #0x00000200
-    str r2, [r0, #0x4]
-    mov r2, #0x00000000
-    str r2, [r0, #0xc]
-
-    ldr r0, =0x53fa8700
-    str r2, [r0, #0x14]
-    str r1, [r0, #0x18]
-    str r1, [r0, #0x1c]
-    str r3, [r0, #0x20]
-
-    moveq r2, #0x02000000
-    movne r2, #0x06000000
-
-    str r2, [r0, #0x24]
-    str r1, [r0, #0x28]
-    str r1, [r0, #0x2c]
-
-    /* Initialize DDR2 memory - Hynix H5PS2G83AFR */
-    ldr r0, =ESDCTL_BASE_ADDR
-
-    ldreq r1, =0x34333936
-    ldrne r1, =0x2b2f322f
-
-    str r1, [r0, #0x088]
-
-    ldreq r1, =0x49434942
-    ldrne r1, =0x43403a3a
-    str r1, [r0, #0x090]
-
-    /* add 3 logic unit of delay to sdclk  */
-    ldr r1, =0x00000f00
-    strne r1, [r0, #0x098]
-
-    ldr r1, =0x00000800
-    str r1, [r0, #0x0F8]
-
-    ldreq r1, =0x01350138
-    ldrne r1, =0x020c0211
-
-    str r1, [r0, #0x07c]
-
-    ldreq r1, =0x01380139
-    ldrne r1, =0x0133014b
-
-    str r1, [r0, #0x080]
-
-    /* Enable bank interleaving, RALAT = 0x4, DDR2_EN = 1 */
-    ldr r1, =0x00001710
-    str r1, [r0, #0x018]
-
-    ldr r1, =0xc4110000
-    str r1, [r0, #0x00]
-
-    ldr r1, =0x4d5122d2
-    str r1, [r0, #0x0C]
-
-    ldr r1, =0x92d18a22
-    str r1, [r0, #0x10]
-
-    ldr r1, =0x00c70092
-    str r1, [r0, #0x14]
-
-    ldr r1, =0x000026d2
-    str r1, [r0, #0x2C]
-
-    ldr r1, =0x009f000e
-    str r1, [r0, #0x30]
-
-    ldr r1, =0x12272000
-    str r1, [r0, #0x08]
-
-    ldr r1, =0x00030012
-    str r1, [r0, #0x04]
-
-    ldr r1, =0x04008010
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008032
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008033
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008031
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0b5280b0
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x04008010
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008020
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008020
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0a528030
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x03c68031
-    str r1, [r0, #0x1C]
-
-    ldreq r1, =0x00448031
-    ldrne r1, =0x00468031
-    str r1, [r0, #0x1C]
-
-    /* Even though Rev B does not have DDR on CSD1, keep these
-      * mode register initialization sequences for future uses since
-      * it does not hurt to keep them
-      */
-    ldr r1, =0x04008018
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0000803a
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0000803b
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008039
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0b528138
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x04008018
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008028
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008028
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0a528038
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x03c68039
-    str r1, [r0, #0x1C]
-
-    ldreq r1, =0x00448039
-    ldrne r1, =0x00468039
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00005800
-    str r1, [r0, #0x20]
-
-    /* Enable 50ohm ODT for TO2*/
-    ldreq r1, =0x00033335
-    ldrne r1, =0x00033337
-    str r1, [r0, #0x58]
-
-    ldr r1, =0x00000000
-    str r1, [r0, #0x1C]
-
-/* Enable ZQ calibration for TO2 */
-    ldr r1, =0x04b80003
-    streq r1, [r0, #0x40]
-
-/* For TO2 only, set LDO to 1.3V */
-    ldr r0, =0x53fa8000
-    ldr r1, =0x00194005
-    streq r1, [r0, #0x04]
-
-/* DDR3 script for SMD and ARM2 CPU3 board */
-#else
-
-    /* IOMUX Setup */
-    ldr r0, =0x53fa8500
-    mov r1, #0x00300000
-    add r2, r1, #0x40
-
-    str r1, [r0, #0x54]
-    str r2, [r0, #0x58]
-    str r1, [r0, #0x60]
-    str r2, [r0, #0x64]
-    str r2, [r0, #0x68]
-
-    str r1, [r0, #0x70]
-    str r1, [r0, #0x74]
-    str r1, [r0, #0x78]
-    str r2, [r0, #0x7c]
-    str r2, [r0, #0x80]
-    str r1, [r0, #0x84]
-    str r1, [r0, #0x88]
-    str r2, [r0, #0x90]
-    str r1, [r0, #0x94]
-
-    ldr r0, =0x53fa86f0
-    str r1, [r0, #0x0]
-    mov r2, #0x00000000
-    str r2, [r0, #0x4]
-    str r2, [r0, #0xc]
-
-    ldr r0, =0x53fa8700
-    str r2, [r0, #0x14]
-    str r1, [r0, #0x18]
-    str r1, [r0, #0x1c]
-    str r1, [r0, #0x20]
-
-    mov r2, #0x04000000
-    str r2, [r0, #0x24]
-    str r1, [r0, #0x28]
-    str r1, [r0, #0x2c]
-
-    /* Initialize DDR3 memory */
-    ldr r0, =ESDCTL_BASE_ADDR
-
-    ldr r1, =0x32383535
-    str r1, [r0, #0x088]
-
-    ldr r1, =0x40383538
-    str r1, [r0, #0x090]
-
-    ldr r1, =0x0136014d
-    str r1, [r0, #0x07c]
-
-    ldr r1, =0x01510141
-    str r1, [r0, #0x080]
-
-    ldr r1, =0x00091740
-    str r1, [r0, #0x018]
-
-    ldr r1, =0xc4190000
-    str r1, [r0, #0x00]
-
-    ldr r1, =0x565a7543
-    str r1, [r0, #0x0C]
-
-    ldr r1, =0xb6ae8aa3
-    str r1, [r0, #0x10]
-
-    ldr r1, =0x01ff00db
-    str r1, [r0, #0x14]
-
-    ldr r1, =0x000026d2
-    str r1, [r0, #0x2C]
-
-    ldr r1, =0x009f0e21
-    str r1, [r0, #0x30]
-
-    ldr r1, =0x12272000
-    str r1, [r0, #0x08]
-
-    ldr r1, =0x00030012
-    str r1, [r0, #0x04]
-
-    ldr r1, =0x00008032
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00008033
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00028031
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x092080b0
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x04008040
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0000803a
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x0000803b
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00028039
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x09208138
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x04008048
-    str r1, [r0, #0x1C]
-
-    ldr r1, =0x00001800
-    str r1, [r0, #0x20]
-
-    ldr r1, =0x04b80003
-    str r1, [r0, #0x40]
-
-    ldr r1, =0x00022227
-    str r1, [r0, #0x58]
-
-    ldr r1, =0x00000000
-    str r1, [r0, #0x1C]
+dcd_hdr:          .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */
+
+/* DCD */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00200000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x560, 0x00200000)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x594, 0x00200000)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x584, 0x00200000)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x558, 0x00200040)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x568, 0x00200040)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x590, 0x00200040)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00200040)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x564, 0x00200040)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00200040)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x570, 0x00200000)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x578, 0x00200000)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x72c, 0x00200000)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x728, 0x00200000)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x71c, 0x00200000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x718, 0x00200000)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x574, 0x00280000)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x588, 0x00280000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x6f0, 0x00280000)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x720, 0x00280000)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x724, 0x06000000)
+MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x34333936)
+MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x49434942)
+MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800)
+MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x01350138)
+MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x01380139)
+MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710)
+MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4110000)
+MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2)
+MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22)
+MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092)
+MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e)
+MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
+MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
+MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
+MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
+MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031)
+MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0)
+MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
+MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
+MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
+MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030)
+MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031)
+MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00448031)
+MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
+MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
+MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
+MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039)
+MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138)
+MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
+MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
+MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
+MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038)
+MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039)
+MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00448039)
+MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033335)
+MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x040, 0x04b80003)
+
+
+#elif defined(CONFIG_MX53_ARM2_DDR3)
+dcd_hdr:          .word 0x40A801D2 /* Tag=0xD2, Len=52*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04A401CC /* Tag=0xCC, Len=52*8 + 4, Param=4 */
+
+/* DCD */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00300000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x560, 0x00300000)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x594, 0x00300000)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x584, 0x00300000)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x558, 0x00300040)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x568, 0x00300040)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x590, 0x00300040)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00300040)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x564, 0x00300040)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00300040)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x570, 0x00300000)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x578, 0x00300000)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x72c, 0x00300000)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x728, 0x00300000)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x71c, 0x00300000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x718, 0x00300000)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x574, 0x00300000)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x588, 0x00300000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x6f0, 0x00300000)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x720, 0x00300000)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x724, 0x00000000)
+MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x098, 0x00000a00)
+MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x088, 0x32383535)
+MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x090, 0x40383538)
+MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x0136014d)
+MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x01510141)
+MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00091740)
+MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4190000)
+MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00C, 0x565a7543)
+MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0xb6ae8aa3)
+MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x01ff00db)
+MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f0e21)
+MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
+MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
+MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x02008032)
+MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x092080b0)
+MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0200803a)
+MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
+MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00428039)
+MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x09208138)
+MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x04008048)
+MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x020, 0x00001800)
+MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x040, 0x04b80003)
+MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x058, 0x00002225)
+MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
 
 #endif
-
-/*
-  *  The following is to fill in those arguments for this ROM function
-  * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
-  *
-  *  This function is used to copy data from the storage media into DDR.
-  *
-  *  start - Initial (possibly partial) image load address on entry. Final image
-  *            load address on exit.
-  *  bytes - Initial (possibly partial) image size on entry. Final image size on
-  *             exit.
-  *  boot_data - Initial @ref ivt Boot Data load address.
-  */
-    adr r0, DDR_DEST_ADDR
-    adr r1, COPY_SIZE
-    adr r2, BOOT_DATA
-before_calling_rom___pu_irom_hwcnfg_setup:
-
-    /* Different ROM address for TO 1.0 & TO 2.0 */
-    moveq r4, #0x1800
-    addeq r4, r4, #0x4d
-    beq 2f
-    mov r4, #0x400000
-    add r4, r4, #0x5000
-    add r4, r4, #0xc7
-
-2:  blx r4 /* This address might change in future ROM versions */
-after_calling_rom___pu_irom_hwcnfg_setup:
-
-/* To return to ROM from plugin, we need to fill in these argument.
-  * Here is what need to do:
-  * Need to construct the paramters for this function before return to ROM:
-  * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
-  */
-    pop {r0-r3, lr}
-    ldr r4, DDR_DEST_ADDR
-    str r4, [r0]
-    ldr r4, COPY_SIZE
-    str r4, [r1]
-    mov r4, #0x400  /* Point to the second IVT table at offset 0x42C */
-    add r4, r4, #0x2C
-    str r4, [r2]
-    mov r0, #1
-
-    bx lr          /* return back to ROM code */
-
-DDR_DEST_ADDR:    .word   TEXT_BASE
-COPY_SIZE:        .word   _end - TEXT_BASE
-BOOT_DATA:        .word   TEXT_BASE
-                  .word   _end - TEXT_BASE
-                  .word   0
 #endif
diff --git a/board/freescale/mx53_rd/lowlevel_init.S b/board/freescale/mx53_rd/lowlevel_init.S
index dbf344c..4c5d78d 100644
--- a/board/freescale/mx53_rd/lowlevel_init.S
+++ b/board/freescale/mx53_rd/lowlevel_init.S
@@ -84,6 +84,15 @@
 .endm
 
 .macro init_clock
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+	cmp r1, #0x20
+
+	/* For TO2 only, set LDO to 1.3V */
+	ldr r0, =0x53fa8000
+	ldr r1, =0x00194005
+	streq r1, [r0, #0x04]
+
 	ldr r0, CCM_BASE_ADDR_W
 
 	/* Switch ARM to step clock */
@@ -92,10 +101,37 @@
 
 	setup_pll PLL1_BASE_ADDR, 800
 
-      /* Allow PLL2/DDR to remain at 333 MHz as setup by ROM (must set
-        * BOOT_CFG2[4]=1). VCC and VDDA need to be boosted before DDR
-        * is run at 400 MHz.
-        */
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, CCM_VAL_0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, CCM_VAL_0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, CCM_VAL_0x00808145
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_VAL_0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
 
         setup_pll PLL3_BASE_ADDR, 216
 
@@ -172,6 +208,10 @@ lowlevel_init:
 
 /* Board level setting value */
 CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+CCM_VAL_0x00016154:     .word 0x00016154
+CCM_VAL_0x00808145:     .word 0x00808145
+CCM_VAL_0x00015154:     .word 0x00015154
+CCM_VAL_0x02888945:     .word 0x02888945
 W_DP_OP_800:           	.word DP_OP_800
 W_DP_MFD_800:           .word DP_MFD_800
 W_DP_MFN_800:           .word DP_MFN_800
diff --git a/board/freescale/mx53_rd/mx53_rd.c b/board/freescale/mx53_rd/mx53_rd.c
index 5baa5d0..061b65b 100644
--- a/board/freescale/mx53_rd/mx53_rd.c
+++ b/board/freescale/mx53_rd/mx53_rd.c
@@ -358,12 +358,14 @@ void setup_core_voltages(void)
 	if (i2c_write(0x8, 24, 1, buf, 3))
 		return;
 
-	/* Set DDR voltage VDDA to 1.25V */
-	buf[0] = 0;
-	buf[1] = 0;
-	buf[2] = 0x1a;
-	if (i2c_write(0x8, 26, 1, buf, 3))
-		return;
+	if (is_soc_rev(CHIP_REV_1_0) == 0) {
+		/* Set DDR voltage VDDA to 1.25V */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1a;
+		if (i2c_write(0x8, 26, 1, buf, 3))
+			return;
+	}
 
 	if (is_soc_rev(CHIP_REV_2_0) == 0) {
 		/* Set VCC to 1.3V for TO2 */
@@ -388,7 +390,7 @@ void setup_core_voltages(void)
 	writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 }
 
-#ifdef CONFIG_MX53_EVK
+#if defined(CONFIG_MX53_EVK) || defined(CONFIG_MX53_ARM2_DDR3)
 static int __read_adc_channel(unsigned int chan)
 {
 	unsigned char buf[4] = { 0 };
@@ -512,9 +514,10 @@ static int __print_board_info(int id0, int id1)
 		}
 
 		break;
+
 	default:
 		printf("Unkown board id0:%d\n", id0);
-
+		ret =  -1;
 		break;
 	}
 
@@ -539,6 +542,14 @@ static int _identify_board_fix_up(int id0, int id1)
 		/* set up rev #2 for EVK RevB board */
 		setup_board_rev(2);
 	}
+
+	/* For ARM2 board */
+	if (id0 == -1) {
+		if (clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK) >= 0)
+			clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
+		setup_board_rev(1);
+	}
+
 #endif
 	return ret;
 }
@@ -568,8 +579,11 @@ int identify_board_id(void)
 		return ret;
 
 	ret = __print_board_info(bd_id0, bd_id1);
-	if (ret < 0)
-		return ret;
+	if (ret < 0) {
+		/* Treat it as ARM2 board if it's not recognized */
+		printf("Treat it as MX53 ARM2 board\n");
+		bd_id0 = -1;
+	}
 
 	ret = _identify_board_fix_up(bd_id0, bd_id1);
 
@@ -1255,9 +1269,6 @@ int board_init(void)
 #endif
 	setup_boot_device();
 	setup_soc_rev();
-#if defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
-	setup_board_rev(1);
-#endif
 
 #if defined(CONFIG_MX53_ARD)
 	gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD;
@@ -1419,19 +1430,10 @@ int checkboard(void)
 {
 	printf("Board: ");
 
-/* On EVK, DDR frequency will be bumped up to 400 MHz in identify_board_id() */
-#if !defined(CONFIG_MX53_EVK)
-	/* Bump up the DDR frequency to 400 MHz */
-	if (clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK) >= 0)
-		clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
-#endif
-
 #if defined(CONFIG_MX53_ARD)
 	printf("MX53-ARD 1.0 [");
-#elif defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
-	printf("Board: MX53 ARMADILLO2 ");
 	printf("1.0 [");
-#elif defined(CONFIG_MX53_EVK)
+#elif defined(CONFIG_MX53_EVK) || defined(CONFIG_MX53_ARM2_DDR3)
 #ifdef CONFIG_I2C_MXC
 	identify_board_id();
 
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
index 3d0772d..3e3571e 100644
--- a/cpu/arm_cortexa8/mx53/generic.c
+++ b/cpu/arm_cortexa8/mx53/generic.c
@@ -739,9 +739,13 @@ static int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param)
 		writel(ccsr & ~0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
 		break;
 	case PLL2_CLK:
+		/* Switch to pll2 bypass clock */
+		writel(ccsr | 0x2, CCM_BASE_ADDR + CLKCTL_CCSR);
 		CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
+		/* Switch back */
+		writel(ccsr & ~0x2, CCM_BASE_ADDR + CLKCTL_CCSR);
 		break;
 	case PLL3_CLK:
 		/* Switch to pll3 bypass clock */
@@ -842,8 +846,8 @@ static int config_periph_clk(u32 ref, u32 freq)
 		u32 old_nfc = __get_nfc_clk();
 
 		/* Switch peripheral to PLL3 */
-		writel((old_cbcmr & ~0x3000) | (1 << 12),
-			CCM_BASE_ADDR + CLKCTL_CBCMR);
+		writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR);
+		writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR);
 
 		/* Make sure change is effective */
 		while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
@@ -859,6 +863,7 @@ static int config_periph_clk(u32 ref, u32 freq)
 		config_pll_clk(PLL2_CLK, &pll_param);
 
 		/* Switch peripheral back */
+		writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
 		writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR);
 
 		/* Make sure change is effective */
diff --git a/include/asm-arm/arch-mx53/mx53.h b/include/asm-arm/arch-mx53/mx53.h
index d574841..eb83ae5 100644
--- a/include/asm-arm/arch-mx53/mx53.h
+++ b/include/asm-arm/arch-mx53/mx53.h
@@ -24,10 +24,9 @@
 #define __REG8(x)       (*((volatile u8 *)(x)))
 
 /*
-  * ROM address which denotes silicon rev
-  */
-#define ROM_SI_REV	0x48
-
+ *ROM address which denotes silicon rev
+ */
+#define ROM_SI_REV     0x48
 /*
  * SATA
  */
diff --git a/include/configs/mx53_ard.h b/include/configs/mx53_ard.h
index d47635d..9dcb980 100644
--- a/include/configs/mx53_ard.h
+++ b/include/configs/mx53_ard.h
@@ -39,6 +39,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    400
+#define CONFIG_SYS_AHB_PODF     2
+#define CONFIG_SYS_AXIA_PODF    0
+#define CONFIG_SYS_AXIB_PODF    1
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_ard_mfg.h b/include/configs/mx53_ard_mfg.h
index da84acd..488d4d1 100755
--- a/include/configs/mx53_ard_mfg.h
+++ b/include/configs/mx53_ard_mfg.h
@@ -40,6 +40,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    400
+#define CONFIG_SYS_AHB_PODF     2
+#define CONFIG_SYS_AXIA_PODF    0
+#define CONFIG_SYS_AXIB_PODF    1
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_arm2.h b/include/configs/mx53_arm2.h
deleted file mode 100644
index 061ee68..0000000
--- a/include/configs/mx53_arm2.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53-ARM2 Freescale board.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/mx53.h>
-
- /* High Level Configuration Options */
-#define CONFIG_ARMV7		/* This is armv7 Cortex-A8 CPU core */
-#define CONFIG_MXC
-#define CONFIG_MX53
-#define CONFIG_MX53_ARM2
-#define CONFIG_FLASH_HEADER
-#define CONFIG_FLASH_HEADER_OFFSET 0x400
-#define CONFIG_MX53_CLK32	32768
-
-#define CONFIG_SKIP_RELOCATE_UBOOT
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_ARCH_MMU
-
-#define CONFIG_MX53_HCLK_FREQ	24000000
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_64BIT_VSPRINTF
-
-#define BOARD_LATE_INIT
-/*
- * Disabled for now due to build problems under Debian and a significant
- * increase in the final file size: 144260 vs. 109536 Bytes.
- */
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-
-/*
- * Hardware drivers
- */
-#define CONFIG_MXC_UART 1
-#define CONFIG_UART_BASE_ADDR   UART1_BASE_ADDR
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_NET_RETRY_COUNT  100
-#define CONFIG_NET_MULTI 1
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_ENV
-
-#define CONFIG_CMD_IIM
-
-#define CONFIG_CMD_CLOCK
-#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
-
-#define CONFIG_CMD_SATA
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY	3
-
-#define CONFIG_PRIME	"FEC0"
-
-#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
-#define CONFIG_RD_LOADADDR	(CONFIG_LOADADDR + 0x300000)
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-		"netdev=eth0\0"						\
-		"ethprime=FEC0\0"					\
-		"uboot=u-boot.bin\0"			\
-		"kernel=uImage\0"				\
-		"nfsroot=/opt/eldk/arm\0"				\
-		"bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
-		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
-			"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
-		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
-			"tftpboot ${loadaddr} ${kernel}; bootm\0"	\
-		"bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp "     \
-			"root=/dev/mmcblk0p2 rootwait\0"                \
-		"bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0"   \
-		"bootcmd=run bootcmd_net\0"                             \
-
-
-#define CONFIG_ARP_TIMEOUT	200UL
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"ARM2 U-Boot > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x10000
-
-#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-#define CONFIG_SYS_HZ				1000
-
-#define CONFIG_CMDLINE_EDITING	1
-
-#define CONFIG_FEC0_IOBASE	FEC_BASE_ADDR
-#define CONFIG_FEC0_PINMUX	-1
-#define CONFIG_FEC0_PHY_ADDR	-1
-#define CONFIG_FEC0_MIIBASE 	-1
-
-#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#define CONFIG_IIM_MAC_ADDR_OFFSET      0x24
-
-#define CONFIG_MXC_FEC
-#define CONFIG_MII
-#define CONFIG_MII_GASKET
-#define CONFIG_DISCOVER_PHY
-
-/*
- * FUSE Configs
- * */
-#ifdef CONFIG_CMD_IIM
-	#define CONFIG_IMX_IIM
-	#define IMX_IIM_BASE    IIM_BASE_ADDR
-	#define CONFIG_IIM_MAC_BANK     1
-	#define CONFIG_IIM_MAC_ROW      9
-#endif
-
-/*
- * I2C Configs
- */
-#define CONFIG_CMD_I2C          1
-#define CONFIG_HARD_I2C         1
-#define CONFIG_I2C_MXC          1
-#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED            100000
-#define CONFIG_SYS_I2C_SLAVE            0xfe
-
-
-/*
- * SPI Configs
- */
-#define CONFIG_FSL_SF		1
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_IMX_ATMEL	1
-#define CONFIG_SPI_FLASH_CS	1
-#define CONFIG_IMX_ECSPI
-#define IMX_CSPI_VER_2_3        1
-#define MAX_SPI_BYTES		(64 * 4)
-
-/*
- * MMC Configs
- */
-#ifdef CONFIG_CMD_MMC
-	#define CONFIG_MMC				1
-	#define CONFIG_GENERIC_MMC
-	#define CONFIG_IMX_MMC
-	#define CONFIG_SYS_FSL_ESDHC_NUM        2
-	#define CONFIG_SYS_FSL_ESDHC_ADDR       0
-	#define CONFIG_SYS_MMC_ENV_DEV  1
-	#define CONFIG_DOS_PARTITION	1
-	#define CONFIG_CMD_FAT		1
-	#define CONFIG_CMD_EXT2		1
-
-	#define CONFIG_BOOT_PARTITION_ACCESS
-	#define CONFIG_EMMC_DDR_PORT_DETECT
-	#define CONFIG_DYNAMIC_MMC_DEVNO
-#endif
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-	#define CONFIG_DWC_AHSATA
-	#define CONFIG_SYS_SATA_MAX_DEVICE	1
-	#define CONFIG_DWC_AHSATA_PORT_ID	0
-	#define CONFIG_DWC_AHSATA_BASE_ADDR 	SATA_BASE_ADDR
-	#define CONFIG_LBA48
-	#define CONFIG_LIBATA
-#endif
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE	(1024 * 1024 * 1024)
-#define iomem_valid_addr(addr, size) \
-	(addr >= PHYS_SDRAM_1 && addr <= \
-		(unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_NO_FLASH
-
-/* Monitor at beginning of flash */
-#define CONFIG_FSL_ENV_IN_MMC
-
-#define CONFIG_ENV_SECT_SIZE    (128 * 1024)
-#define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
-
-#if defined(CONFIG_FSL_ENV_IN_NAND)
-	#define CONFIG_ENV_IS_IN_NAND 1
-	#define CONFIG_ENV_OFFSET	0x100000
-#elif defined(CONFIG_FSL_ENV_IN_MMC)
-	#define CONFIG_ENV_IS_IN_MMC	1
-	#define CONFIG_ENV_OFFSET	(768 * 1024)
-#elif defined(CONFIG_FSL_ENV_IN_SF)
-	#define CONFIG_ENV_IS_IN_SPI_FLASH	1
-	#define CONFIG_ENV_SPI_CS		1
-	#define CONFIG_ENV_OFFSET       (768 * 1024)
-#else
-	#define CONFIG_ENV_IS_NOWHERE	1
-#endif
-#endif				/* __CONFIG_H */
diff --git a/include/configs/mx53_arm2_android.h b/include/configs/mx53_arm2_android.h
deleted file mode 100644
index 157653b..0000000
--- a/include/configs/mx53_arm2_android.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53-ARM2 Freescale board.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/mx53.h>
-
- /* High Level Configuration Options */
-#define CONFIG_ARMV7		/* This is armv7 Cortex-A8 CPU core */
-#define CONFIG_MXC
-#define CONFIG_MX53
-#define CONFIG_MX53_ARM2
-#define CONFIG_FLASH_HEADER
-#define CONFIG_FLASH_HEADER_OFFSET 0x400
-#define CONFIG_MX53_CLK32	32768
-
-#define CONFIG_SKIP_RELOCATE_UBOOT
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_ARCH_MMU
-
-#define CONFIG_MX53_HCLK_FREQ	24000000
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_64BIT_VSPRINTF
-
-#define BOARD_LATE_INIT
-/*
- * Disabled for now due to build problems under Debian and a significant
- * increase in the final file size: 144260 vs. 109536 Bytes.
- */
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-
-/*
- * Hardware drivers
- */
-#define CONFIG_MXC_UART 1
-#define CONFIG_UART_BASE_ADDR   UART1_BASE_ADDR
-
-/*
- * Android support Configs
- */
-#include <asm/mxc_key_defs.h>
-
-#define CONFIG_ANDROID_RECOVERY
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \
-	"setenv bootargs ${bootargs} init=/init root=/dev/mmcblk0p4 rootfs=ext4"
-#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC  \
-	"run bootargs_base bootargs_android_recovery;mmc read 0 ${loadaddr} 0x800 0x1800;bootm"
-#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
-#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_NET_RETRY_COUNT  100
-#define CONFIG_NET_MULTI 1
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_ENV
-
-#define CONFIG_CMD_IIM
-
-#define CONFIG_CMD_CLOCK
-#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
-
-#define CONFIG_CMD_SATA
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY	3
-
-#define CONFIG_PRIME	"FEC0"
-
-#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
-#define CONFIG_RD_LOADADDR	(CONFIG_LOADADDR + 0x300000)
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-		"netdev=eth0\0"						\
-		"ethprime=FEC0\0"					\
-		"uboot=u-boot.bin\0"					\
-		"kernel=uImage\0"					\
-		"loadaddr=0x70800000\0"					\
-		"rd_loadaddr=0x70B00000\0"				\
-		"nfsroot=/opt/eldk/arm\0"				\
-		"bootargs_base=setenv bootargs ${bootargs} "		\
-		"console=ttymxc0,115200\0"				\
-		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
-		     "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
-		"bootargs_android=setenv bootargs ${bootargs} mem=512M " \
-		     "androidboot.console=ttymxc0 init=/init "		\
-		     "video=mxcdi0fb:RGB565,800x480M@55 calibration\0"	\
-		"bootcmd=run bootcmd_SD \0"				\
-		"bootcmd_SD=run bootargs_base bootargs_android;"	\
-		     "mmc read 0 ${loadaddr} 0x800 1800;"		\
-		     "mmc read 0 ${rd_loadaddr} 0x2000 0x258;"		\
-		     "bootm ${loadaddr} ${rd_loadaddr}\0"		\
-		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
-			"tftpboot ${loadaddr} ${kernel}; bootm\0"	\
-		"bootcmd_android_recovery=run bootargs_base"		\
-		     " bootargs_android_recovery;"			\
-		     "mmc read 0 ${loadaddr} 0x800 0x1800;bootm\0"	\
-		"bootargs_android_recovery=setenv bootargs ${bootargs}" \
-		     " init=/init root=/dev/mmcblk0p4 rootfs=ext4\0"	\
-
-#define CONFIG_ARP_TIMEOUT	200UL
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"MX53 ARM2 U-Boot > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x10000
-
-#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-#define CONFIG_SYS_HZ				1000
-
-#define CONFIG_CMDLINE_EDITING	1
-
-#define CONFIG_FEC0_IOBASE	FEC_BASE_ADDR
-#define CONFIG_FEC0_PINMUX	-1
-#define CONFIG_FEC0_PHY_ADDR	-1
-#define CONFIG_FEC0_MIIBASE 	-1
-
-#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#define CONFIG_IIM_MAC_ADDR_OFFSET      0x24
-
-#define CONFIG_MXC_FEC
-#define CONFIG_MII
-#define CONFIG_MII_GASKET
-#define CONFIG_DISCOVER_PHY
-
-/*
- * FUSE Configs
- * */
-#ifdef CONFIG_CMD_MMC
-	#define CONFIG_IMX_IIM
-	#define IMX_IIM_BASE    IIM_BASE_ADDR
-	#define CONFIG_IIM_MAC_BANK     1
-	#define CONFIG_IIM_MAC_ROW      9
-#endif
-
-/*
- * I2C Configs
- */
-#define CONFIG_CMD_I2C          1
-#define CONFIG_HARD_I2C         1
-#define CONFIG_I2C_MXC          1
-#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED            100000
-#define CONFIG_SYS_I2C_SLAVE            0xfe
-
-
-/*
- * SPI Configs
- */
-#define CONFIG_FSL_SF		1
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_IMX_ATMEL	1
-#define CONFIG_SPI_FLASH_CS	1
-#define CONFIG_IMX_ECSPI
-#define IMX_CSPI_VER_2_3        1
-#define MAX_SPI_BYTES		(64 * 4)
-
-/*
- * MMC Configs
- */
-#ifdef CONFIG_CMD_MMC
-	#define CONFIG_MMC				1
-	#define CONFIG_GENERIC_MMC
-	#define CONFIG_IMX_MMC
-	#define CONFIG_SYS_FSL_ESDHC_NUM        2
-	#define CONFIG_SYS_FSL_ESDHC_ADDR       0
-	#define CONFIG_SYS_MMC_ENV_DEV  1
-	#define CONFIG_DOS_PARTITION	1
-	#define CONFIG_CMD_FAT		1
-	#define CONFIG_CMD_EXT2		1
-
-	#define CONFIG_BOOT_PARTITION_ACCESS
-#endif
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-	#define CONFIG_DWC_AHSATA
-	#define CONFIG_SYS_SATA_MAX_DEVICE	1
-	#define CONFIG_DWC_AHSATA_PORT_ID	0
-	#define CONFIG_DWC_AHSATA_BASE_ADDR 	SATA_BASE_ADDR
-	#define CONFIG_LBA48
-	#define CONFIG_LIBATA
-#endif
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE	(1024 * 1024 * 1024)
-#define iomem_valid_addr(addr, size) \
-	(addr >= PHYS_SDRAM_1 && addr <= \
-		(unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_NO_FLASH
-
-/* Monitor at beginning of flash */
-#define CONFIG_FSL_ENV_IN_MMC
-
-#define CONFIG_ENV_SECT_SIZE    (128 * 1024)
-#define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
-
-#if defined(CONFIG_FSL_ENV_IN_NAND)
-	#define CONFIG_ENV_IS_IN_NAND 1
-	#define CONFIG_ENV_OFFSET	0x100000
-#elif defined(CONFIG_FSL_ENV_IN_MMC)
-	#define CONFIG_ENV_IS_IN_MMC	1
-	#define CONFIG_ENV_OFFSET	(768 * 1024)
-#elif defined(CONFIG_FSL_ENV_IN_SF)
-	#define CONFIG_ENV_IS_IN_SPI_FLASH	1
-	#define CONFIG_ENV_SPI_CS		1
-	#define CONFIG_ENV_OFFSET       (768 * 1024)
-#else
-	#define CONFIG_ENV_IS_NOWHERE	1
-#endif
-#endif				/* __CONFIG_H */
diff --git a/include/configs/mx53_arm2_ddr3.h b/include/configs/mx53_arm2_ddr3.h
index b131bea..91e0060 100644
--- a/include/configs/mx53_arm2_ddr3.h
+++ b/include/configs/mx53_arm2_ddr3.h
@@ -39,6 +39,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    600
+#define CONFIG_SYS_AHB_PODF     4
+#define CONFIG_SYS_AXIA_PODF    1
+#define CONFIG_SYS_AXIB_PODF    2
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_arm2_ddr3_android.h b/include/configs/mx53_arm2_ddr3_android.h
index dfc9fde..f56a7a3 100644
--- a/include/configs/mx53_arm2_ddr3_android.h
+++ b/include/configs/mx53_arm2_ddr3_android.h
@@ -39,6 +39,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    600
+#define CONFIG_SYS_AHB_PODF     4
+#define CONFIG_SYS_AXIA_PODF    1
+#define CONFIG_SYS_AXIB_PODF    2
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
index 0da41dc..bc31975 100644
--- a/include/configs/mx53_evk.h
+++ b/include/configs/mx53_evk.h
@@ -39,6 +39,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    600
+#define CONFIG_SYS_AHB_PODF     4
+#define CONFIG_SYS_AXIA_PODF    1
+#define CONFIG_SYS_AXIB_PODF    2
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_evk_android.h b/include/configs/mx53_evk_android.h
index 124012e..197f963 100644
--- a/include/configs/mx53_evk_android.h
+++ b/include/configs/mx53_evk_android.h
@@ -39,6 +39,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    600
+#define CONFIG_SYS_AHB_PODF     4
+#define CONFIG_SYS_AXIA_PODF    1
+#define CONFIG_SYS_AXIB_PODF    2
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx53_evk_mfg.h b/include/configs/mx53_evk_mfg.h
index 2a99ed3..bac8515 100755
--- a/include/configs/mx53_evk_mfg.h
+++ b/include/configs/mx53_evk_mfg.h
@@ -40,6 +40,10 @@
 #define CONFIG_ARCH_MMU
 
 #define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    600
+#define CONFIG_SYS_AHB_PODF     4
+#define CONFIG_SYS_AXIA_PODF    1
+#define CONFIG_SYS_AXIB_PODF    2
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO