FSL DDR: Convert SBC8560 to new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

6 files changed, 122 insertions, 14 deletions

diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile
index bb96d95..6399734 100644
--- a/board/sbc8560/Makefile
+++ b/board/sbc8560/Makefile
@@ -28,10 +28,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c
new file mode 100644
index 0000000..45372f4
--- /dev/null
+++ b/board/sbc8560/ddr.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index d9e598c..dc66170 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -29,7 +29,9 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
@@ -283,7 +285,9 @@ phys_size_t initdram (int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram ();
 #endif
diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds
index ba5ce0b..237a3b6 100644
--- a/board/sbc8560/u-boot.lds
+++ b/board/sbc8560/u-boot.lds
@@ -74,7 +74,6 @@ SECTIONS
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/spd_sdram.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 6033d93..93509ee 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -103,18 +103,34 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
 #undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
 #undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_SPD
 
 #if defined(CONFIG_MPC85xx_REV1)
   #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */
+
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index b244eef..99d328c 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -97,18 +97,34 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module	*/
-#undef  CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_SPD
 
 #if defined(CONFIG_MPC85xx_REV1)
-  #define CONFIG_DDR_DLL		/* possible DLL fix needed	*/
+  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */
+
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)