diff options
| author | Victor Gallardo <vgallardo@amcc.com> | 2008-09-16 06:59:13 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-09-16 20:16:31 +0200 |
| commit | 3eec160a3a405b29ce9c06920f6427b9047dd8a8 (patch) | |
| tree | 14c0a3795543b2ee4d8e5bb0c63e247de469bf37 | |
| parent | c0d2f87d6c450128b88e73eea715fa3654f65b6c (diff) | |
| download | u-boot-imx-3eec160a3a405b29ce9c06920f6427b9047dd8a8.zip u-boot-imx-3eec160a3a405b29ce9c06920f6427b9047dd8a8.tar.gz u-boot-imx-3eec160a3a405b29ce9c06920f6427b9047dd8a8.tar.bz2 | |
ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/amcc/kilauea/kilauea.c | 31 | ||||
| -rw-r--r-- | cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 5 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 6 |
3 files changed, 37 insertions, 5 deletions
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index f407e19..1caa2fd 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -374,3 +374,34 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) +/* + * This is for quicker auto calibration boot up once WRDTR and CLKTR + * values for the kilauea board were determined and are therefore known. + * + * Use these scan options for PLB bus greater than or equal 200MHz + * else use the defaults. These options are known to return a cycle + * delay of T2 or better with a 200MHz PLB bus. Scanning the + * full list of WDTR/CLKTR should work, but currently it does not. + * HW team is investigating. + */ +/* List of (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CLKP]) pairs to try */ +struct sdram_timing quick_scan_options[] = { + {0, 3}, {1, 1}, {1, 2}, {1, 3}, + {2, 1}, {2, 2}, {2, 3}, {3, 1}, + {3, 2}, {4, 1}, {-1, -1} +}; + +ulong ddr_scan_option(ulong default_val) +{ + PPC4xx_SYS_INFO board_cfg; + + get_sys_info(&board_cfg); + + if (board_cfg.freqPLB >= 200000000) + return (ulong)(quick_scan_options); + else + return (ulong)default_val; +} +#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 83b9883..3ba8176 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -79,11 +79,6 @@ struct ddrautocal { u32 flags; }; -struct sdram_timing { - u32 wrdtr; - u32 clktr; -}; - struct sdram_timing_clks { u32 wrdtr; u32 clktr; diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..2ba5619 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -1403,6 +1403,12 @@ #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ #ifndef __ASSEMBLY__ + +struct sdram_timing { + u32 wrdtr; + u32 clktr; +}; + /* * Prototypes */ |