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author | Vlad Lungu <vlad@comsys.ro> | 2007-10-10 23:02:09 +0300 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-04-24 23:49:00 +0200 |
commit | 386563197e3a50b0e97ad9aae87f57d9aab909ab (patch) | |
tree | 5002a019700707004e446e36bcd4d2558a909424 | |
parent | 11ea26fd1cb63c91403fe04a6eea975cd418603f (diff) | |
download | u-boot-imx-386563197e3a50b0e97ad9aae87f57d9aab909ab.zip u-boot-imx-386563197e3a50b0e97ad9aae87f57d9aab909ab.tar.gz u-boot-imx-386563197e3a50b0e97ad9aae87f57d9aab909ab.tar.bz2 |
Fixed pcnet io_base
Bus and phys address are not always the same
Signed-off-by: Vlad Lungu <vlad@comsys.ro>
-rw-r--r-- | drivers/net/pcnet.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 9ec7b83..386fa50 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -169,6 +169,7 @@ static struct pci_device_id supported[] = { int pcnet_initialize (bd_t * bis) { +<<<<<<< HEAD:drivers/net/pcnet.c pci_dev_t devbusfn; struct eth_device *dev; u16 command, status; @@ -197,6 +198,7 @@ int pcnet_initialize (bd_t * bis) */ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *) &dev->iobase); + dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); dev->iobase &= ~0xf; PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", @@ -230,6 +232,59 @@ int pcnet_initialize (bd_t * bis) dev->recv = pcnet_recv; eth_register (dev); +======= + pci_dev_t devbusfn; + struct eth_device* dev; + u16 command, status; + int dev_nr = 0; + + PCNET_DEBUG1("\npcnet_initialize...\n"); + + for (dev_nr = 0; ; dev_nr++) { + + /* + * Find the PCnet PCI device(s). + */ + if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) { + break; + } + + /* + * Allocate and pre-fill the device structure. + */ + dev = (struct eth_device*) malloc(sizeof *dev); + dev->priv = (void *)devbusfn; + sprintf(dev->name, "pcnet#%d", dev_nr); + + /* + * Setup the PCI device. + */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase); + dev->iobase=pci_io_to_phys(devbusfn,dev->iobase); + dev->iobase &= ~0xf; + + PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); + + command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, command); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if ((status & command) != command) { + printf("%s: Couldn't enable IO access or Bus Mastering\n", + dev->name); + free(dev); + continue; + } + + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); + + /* + * Probe the PCnet chip. + */ + if (pcnet_probe(dev, bis, dev_nr) < 0) { + free(dev); + continue; +>>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c } udelay (10 * 1000); |